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dt-bindings: Changes for v5.7-rc1
New IDs are added for clocks that are controlled by the PMC. This replaces older IDs that were erroneously provided by the clock and reset controller. This also adds device tree bindings for XUSB pad controller support on Tegra194 as well as USB role switching on NVIDIA Tegra SoCs. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl5rs5oTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoTKdD/9m2rJ1ekW/7b/LH0vKQaSo/cVcfDfL OjhnM/B9Wslcfdr55d8fna1vJjhyXJaBTKZAR/RiKGCGPdKE+1mDKcLauAH+2Kmd HHA0gDcfumv14B5ZNb6NfKTZt+Gk86m6zv5fp0Wo9BN9EpnfbuRjDzsC7PlYHhJ+ ipO4UujgBuDCKXrhkl8OatoMKIaqyYXIJz+JXMFdE4U5HqGbWw1YpgfpSaU5VBMc LWWTE0qHNut8IxGV0tAm13R+GO1lX24zRScn74zTPfqAS18s0jHkH80pVfIQ5kUp PZHoiIYEFzL5qD02aT0VoCMPNQ6c/c6KUQVZ8cpSHb4NIFLgPgOhn583YBmeXWa0 uVR0GVJ3Wi6wspnN3kagssZIuX/KV+6zIBsVRPqVDwm/wop4fNmcXazUQ5MijNRF AqBS9jylC8P401kt1zN/dxrcyQ+E2gRkrQ1wKz/1DVWz9UdzwoV82w7k4etzkcL8 pv8oLFhir//jKFNWa/U9/y65AUmqvBs6d5wbJa17rRHt9y2uMyXrXMgetAlbkMt/ WBEFIcR3F/dDIEU2UrWPCWtRYpbfBwKx8fGFSGEbyEjzYWDnqWscbf/dFKmeA1nK ATLbQov13qJ9scQXgDIekTXG19kQC/GaKfRofIK0Owg/Kae23McrOtSz6u8U9Nnw ZNPFxLJLJQ/3ew== =nBkr -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.7-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.7-rc1 New IDs are added for clocks that are controlled by the PMC. This replaces older IDs that were erroneously provided by the clock and reset controller. This also adds device tree bindings for XUSB pad controller support on Tegra194 as well as USB role switching on NVIDIA Tegra SoCs. * tag 'tegra-for-5.7-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding dt-bindings: phy: tegra-xusb: Add usb-role-switch dt-bindings: phy: tegra: Add Tegra194 support dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: clock: tegra: Add IDs for OSC clocks Link: https://lore.kernel.org/r/20200313165848.2915133-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
eaf36fbb39
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NVIDIA Tegra Power Management Controller (PMC)
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== Power Management Controller Node ==
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : Should contain one of the following:
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For Tegra20 must contain "nvidia,tegra20-pmc".
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For Tegra30 must contain "nvidia,tegra30-pmc".
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For Tegra114 must contain "nvidia,tegra114-pmc"
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For Tegra124 must contain "nvidia,tegra124-pmc"
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For Tegra132 must contain "nvidia,tegra124-pmc"
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For Tegra210 must contain "nvidia,tegra210-pmc"
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries:
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"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
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Optional properties:
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- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and then
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fed into the ARM GIC. The PMC is not involved in the detection or
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handling of this interrupt signal, merely its inversion.
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- nvidia,suspend-mode : The suspend mode that the platform should use.
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
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1 (LP1): CPU voltage off and DRAM in self-refresh
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2 (LP2): CPU voltage off
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
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is enabled.
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Required properties when nvidia,suspend-mode is specified:
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- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
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- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
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Core power good time in uS.
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- nvidia,core-pwr-off-time : Core power off time in uS.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
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The LP0 vector contains the warm boot code that is executed by AVP when
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
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processor and always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed from the deep
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Hardware-triggered thermal reset:
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On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
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hardware-triggered thermal reset will be enabled.
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Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
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described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
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Tegra K1 Technical Reference Manual.
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- nvidia,bus-addr : Bus address of the PMU on the I2C bus
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- nvidia,reg-addr : I2C register address to write poweroff command to
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- nvidia,reg-data : Poweroff command to write to PMU
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Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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Optional nodes:
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- powergates : This node contains a hierarchy of power domain nodes, which
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should match the powergates on the Tegra SoC. See "Powergate
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Nodes" below.
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Example:
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/ SoC dts including file
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <2000>;
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nvidia,cpu-pwr-off-time = <100>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <458>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
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};
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/ Tegra board dts file
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{
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...
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pmc@7000f400 {
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i2c-thermtrip {
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nvidia,i2c-controller-id = <4>;
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nvidia,bus-addr = <0x40>;
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nvidia,reg-addr = <0x36>;
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nvidia,reg-data = <0x2>;
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};
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};
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...
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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...
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};
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== Powergate Nodes ==
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Each of the powergate nodes represents a power-domain on the Tegra SoC
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that can be power-gated by the Tegra PMC. The name of the powergate node
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should be one of the below. Note that not every powergate is applicable
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to all Tegra devices and the following list shows which powergates are
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applicable to which devices. Please refer to the Tegra TRM for more
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details on the various powergates.
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Name Description Devices Applicable
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3d 3D Graphics Tegra20/114/124/210
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3d0 3D Graphics 0 Tegra30
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3d1 3D Graphics 1 Tegra30
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aud Audio Tegra210
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dfd Debug Tegra210
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dis Display A Tegra114/124/210
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disb Display B Tegra114/124/210
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heg 2D Graphics Tegra30/114/124/210
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iram Internal RAM Tegra124/210
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mpe MPEG Encode All
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nvdec NVIDIA Video Decode Engine Tegra210
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nvjpg NVIDIA JPEG Engine Tegra210
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pcie PCIE Tegra20/30/124/210
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sata SATA Tegra30/124/210
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sor Display interfaces Tegra124/210
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ve2 Video Encode Engine 2 Tegra210
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venc Video Encode Engine All
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vdec Video Decode Engine Tegra20/30/114/124
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vic Video Imaging Compositor Tegra124/210
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xusba USB Partition A Tegra114/124/210
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xusbb USB Partition B Tegra114/124/210
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xusbc USB Partition C Tegra114/124/210
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Required properties:
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- clocks: Must contain an entry for each clock required by the PMC for
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controlling a power-gate. See ../clocks/clock-bindings.txt for details.
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- resets: Must contain an entry for each reset required by the PMC for
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controlling a power-gate. See ../reset/reset.txt for details.
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- #power-domain-cells: Must be 0.
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Example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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powergates {
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pd_audio: aud {
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clocks = <&tegra_car TEGRA210_CLK_APE>,
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<&tegra_car TEGRA210_CLK_APB2APE>;
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resets = <&tegra_car 198>;
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#power-domain-cells = <0>;
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};
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};
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};
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== Powergate Clients ==
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Hardware blocks belonging to a power domain should contain a "power-domains"
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property that is a phandle pointing to the corresponding powergate node.
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Example:
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adma: adma@702e2000 {
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...
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power-domains = <&pd_audio>;
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...
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};
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== Pad Control ==
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On Tegra SoCs a pad is a set of pins which are configured as a group.
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The pin grouping is a fixed attribute of the hardware. The PMC can be
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used to set pad power state and signaling voltage. A pad can be either
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in active or power down mode. The support for power state and signaling
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voltage configuration varies depending on the pad in question. 3.3 V and
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1.8 V signaling voltages are supported on pins where software
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controllable signaling voltage switching is available.
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The pad configuration state nodes are placed under the pmc node and they
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are referred to by the pinctrl client properties. For more information
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see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
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The pad name should be used as the value of the pins property in pin
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configuration nodes.
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The following pads are present on Tegra124 and Tegra132:
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audio bb cam comp
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csia csb cse dsi
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dsib dsic dsid hdmi
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hsic hv lvds mipi-bias
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nand pex-bias pex-clk1 pex-clk2
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pex-cntrl sdmmc1 sdmmc3 sdmmc4
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sys_ddc uart usb0 usb1
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usb2 usb_bias
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The following pads are present on Tegra210:
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audio audio-hv cam csia
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csib csic csid csie
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csif dbg debug-nonao dmic
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dp dsi dsib dsic
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dsid emmc emmc2 gpio
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hdmi hsic lvds mipi-bias
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pex-bias pex-clk1 pex-clk2 pex-cntrl
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sdmmc1 sdmmc3 spi spi-hv
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uart usb0 usb1 usb2
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usb3 usb-bias
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Required pin configuration properties:
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- pins: Must contain name of the pad(s) to be configured.
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Optional pin configuration properties:
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- low-power-enable: Configure the pad into power down mode
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- low-power-disable: Configure the pad into active mode
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- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
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or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
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The values are defined in
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include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
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Note: The power state can be configured on all of the Tegra124 and
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Tegra132 pads. None of the Tegra124 or Tegra132 pads support
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signaling voltage switching.
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Note: All of the listed Tegra210 pads except pex-cntrl support power
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state configuration. Signaling voltage switching is supported on
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following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
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pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
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Pad configuration state example:
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pmc: pmc@7000e400 {
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compatible = "nvidia,tegra210-pmc";
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reg = <0x0 0x7000e400 0x0 0x400>;
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clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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...
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sdmmc1_3v3: sdmmc1-3v3 {
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pins = "sdmmc1";
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power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
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};
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sdmmc1_1v8: sdmmc1-1v8 {
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pins = "sdmmc1";
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power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
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};
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hdmi_off: hdmi-off {
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pins = "hdmi";
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low-power-enable;
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}
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hdmi_on: hdmi-on {
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pins = "hdmi";
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low-power-disable;
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}
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};
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Pinctrl client example:
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sdmmc1: sdhci@700b0000 {
|
||||
...
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pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
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||||
pinctrl-0 = <&sdmmc1_3v3>;
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pinctrl-1 = <&sdmmc1_1v8>;
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};
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...
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sor@54540000 {
|
||||
...
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||||
pinctrl-0 = <&hdmi_off>;
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||||
pinctrl-1 = <&hdmi_on>;
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||||
pinctrl-names = "hdmi-on", "hdmi-off";
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||||
};
|
@ -0,0 +1,354 @@
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# SPDX-License-Identifier: GPL-2.0
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||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Tegra Power Management Controller (PMC)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jonathan Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra30-pmc
|
||||
- nvidia,tegra114-pmc
|
||||
- nvidia,tegra124-pmc
|
||||
- nvidia,tegra210-pmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
Offset and length of the register set for the device.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: clk32k_in
|
||||
description:
|
||||
Must includes entries pclk and clk32k_in.
|
||||
pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
|
||||
input to Tegra.
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
description:
|
||||
Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clocks-bindings.txt for details.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
|
||||
PMC also has blink control which allows 32Khz clock output to
|
||||
Tegra blink pad.
|
||||
Consumer of PMC clock should specify the desired clock by having
|
||||
the clock ID in its "clocks" phandle cell with pmc clock provider.
|
||||
See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
|
||||
clock IDs.
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
description:
|
||||
Specifies number of cells needed to encode an interrupt source.
|
||||
The value must be 2.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
nvidia,invert-interrupt:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Inverts the PMU interrupt signal.
|
||||
The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and
|
||||
then fed into the ARM GIC. The PMC is not involved in the detection
|
||||
or handling of this interrupt signal, merely its inversion.
|
||||
|
||||
nvidia,core-power-req-active-high:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Core power request active-high.
|
||||
|
||||
nvidia,sys-clock-req-active-high:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: System clock request active-high.
|
||||
|
||||
nvidia,combined-power-req:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: combined power request for CPU and Core.
|
||||
|
||||
nvidia,cpu-pwr-good-en:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
CPU power good signal from external PMIC to PMC is enabled.
|
||||
|
||||
nvidia,suspend-mode:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [0, 1, 2]
|
||||
description:
|
||||
The suspend mode that the platform should use.
|
||||
Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
|
||||
Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
|
||||
Mode 2 is for LP2, CPU voltage off
|
||||
|
||||
nvidia,cpu-pwr-good-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: CPU power good time in uSec.
|
||||
|
||||
nvidia,cpu-pwr-off-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: CPU power off time in uSec.
|
||||
|
||||
nvidia,core-pwr-good-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
<Oscillator-stable-time Power-stable-time>
|
||||
Core power good time in uSec.
|
||||
|
||||
nvidia,core-pwr-off-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Core power off time in uSec.
|
||||
|
||||
nvidia,lp0-vec:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
<start length> Starting address and length of LP0 vector.
|
||||
The LP0 vector contains the warm boot code that is executed
|
||||
by AVP when resuming from the LP0 state.
|
||||
The AVP (Audio-Video Processor) is an ARM7 processor and
|
||||
always being the first boot processor when chip is power on
|
||||
or resume from deep sleep mode. When the system is resumed
|
||||
from the deep sleep mode, the warm boot code will restore
|
||||
some PLLs, clocks and then brings up CPU0 for resuming the
|
||||
system.
|
||||
|
||||
i2c-thermtrip:
|
||||
type: object
|
||||
description:
|
||||
On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
|
||||
hardware-triggered thermal reset will be enabled.
|
||||
|
||||
properties:
|
||||
nvidia,i2c-controller-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
ID of I2C controller to send poweroff command to PMU.
|
||||
Valid values are described in section 9.2.148
|
||||
"APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
|
||||
Manual.
|
||||
|
||||
nvidia,bus-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Bus address of the PMU on the I2C bus.
|
||||
|
||||
nvidia,reg-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: PMU I2C register address to issue poweroff command.
|
||||
|
||||
nvidia,reg-data:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Poweroff command to write to PMU.
|
||||
|
||||
nvidia,pinmux-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Pinmux used by the hardware when issuing Poweroff command.
|
||||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
required:
|
||||
- nvidia,i2c-controller-id
|
||||
- nvidia,bus-addr
|
||||
- nvidia,reg-addr
|
||||
- nvidia,reg-data
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
powergates:
|
||||
type: object
|
||||
description: |
|
||||
This node contains a hierarchy of power domain nodes, which should
|
||||
match the powergates on the Tegra SoC. Each powergate node
|
||||
represents a power-domain on the Tegra SoC that can be power-gated
|
||||
by the Tegra PMC.
|
||||
Hardware blocks belonging to a power domain should contain
|
||||
"power-domains" property that is a phandle pointing to corresponding
|
||||
powergate node.
|
||||
The name of the powergate node should be one of the below. Note that
|
||||
not every powergate is applicable to all Tegra devices and the following
|
||||
list shows which powergates are applicable to which devices.
|
||||
Please refer to Tegra TRM for mode details on the powergate nodes to
|
||||
use for each power-gate block inside Tegra.
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9]+$":
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each clock required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../clocks/clock-bindings.txt document for more details.
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each reset required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../reset/reset.txt for more details.
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
description: Must be 0.
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- resets
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
"^[a-f0-9]+-[a-f0-9]+$":
|
||||
type: object
|
||||
description:
|
||||
This is a Pad configuration node. On Tegra SOCs a pad is a set of
|
||||
pins which are configured as a group. The pin grouping is a fixed
|
||||
attribute of the hardware. The PMC can be used to set pad power state
|
||||
and signaling voltage. A pad can be either in active or power down mode.
|
||||
The support for power state and signaling voltage configuration varies
|
||||
depending on the pad in question. 3.3V and 1.8V signaling voltages
|
||||
are supported on pins where software controllable signaling voltage
|
||||
switching is available.
|
||||
|
||||
The pad configuration state nodes are placed under the pmc node and they
|
||||
are referred to by the pinctrl client properties. For more information
|
||||
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
|
||||
The pad name should be used as the value of the pins property in pin
|
||||
configuration nodes.
|
||||
|
||||
The following pads are present on Tegra124 and Tegra132
|
||||
audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
|
||||
hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
|
||||
sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
|
||||
|
||||
The following pads are present on Tegra210
|
||||
audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
|
||||
debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
|
||||
hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
|
||||
|
||||
properties:
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Must contain name of the pad(s) to be configured.
|
||||
|
||||
low-power-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into power down mode.
|
||||
|
||||
low-power-disable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into active mode.
|
||||
|
||||
power-source:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
|
||||
The values are defined in
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
|
||||
Power state can be configured on all Tegra124 and Tegra132
|
||||
pads. None of the Tegra124 or Tegra132 pads support signaling
|
||||
voltage switching.
|
||||
All of the listed Tegra210 pads except pex-cntrl support power
|
||||
state configuration. Signaling voltage switching is supported
|
||||
on below Tegra210 pads.
|
||||
audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, and uart.
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
dependencies:
|
||||
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
|
||||
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
|
||||
"nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
#include <dt-bindings/soc/tegra-pmc.h>
|
||||
|
||||
tegra_pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
#clock-cells = <1>;
|
||||
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <0>;
|
||||
nvidia,cpu-pwr-good-time = <0>;
|
||||
nvidia,cpu-pwr-off-time = <0>;
|
||||
nvidia,core-pwr-good-time = <4587 3876>;
|
||||
nvidia,core-pwr-off-time = <39065>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbss: xusba {
|
||||
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
@ -37,6 +37,7 @@ Required properties:
|
||||
- Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
|
||||
- Tegra210: "nvidia,tegra210-xusb-padctl"
|
||||
- Tegra186: "nvidia,tegra186-xusb-padctl"
|
||||
- Tegra194: "nvidia,tegra194-xusb-padctl"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
- reset-names: Must include the following entries:
|
||||
@ -62,6 +63,10 @@ For Tegra186:
|
||||
- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
|
||||
- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
|
||||
|
||||
For Tegra194:
|
||||
- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
|
||||
3.3 V.
|
||||
- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
|
||||
|
||||
Pad nodes:
|
||||
==========
|
||||
@ -154,6 +159,11 @@ For Tegra210, the list of valid PHY nodes is given below:
|
||||
- sata: sata-0
|
||||
- functions: "usb3-ss", "sata"
|
||||
|
||||
For Tegra194, the list of valid PHY nodes is given below:
|
||||
- usb2: usb2-0, usb2-1, usb2-2, usb2-3
|
||||
- functions: "xusb"
|
||||
- usb3: usb3-0, usb3-1, usb3-2, usb3-3
|
||||
- functions: "xusb"
|
||||
|
||||
Port nodes:
|
||||
===========
|
||||
@ -174,6 +184,12 @@ Required properties:
|
||||
- "device": for USB device mode
|
||||
- "otg": for USB OTG mode
|
||||
|
||||
Required properties for OTG/Peripheral capable USB2 ports:
|
||||
- usb-role-switch: Boolean property to indicate that the port support OTG or
|
||||
peripheral mode. If present, the port supports switching between USB host
|
||||
and peripheral roles. Connector should be added as subnode.
|
||||
See usb/usb-conn-gpio.txt.
|
||||
|
||||
Optional properties:
|
||||
- nvidia,internal: A boolean property whose presence determines that a port
|
||||
is internal. In the absence of this property the port is considered to be
|
||||
@ -221,6 +237,11 @@ Optional properties:
|
||||
is internal. In the absence of this property the port is considered to be
|
||||
external.
|
||||
|
||||
- maximum-speed: Only for Tegra194. A string property that specifies maximum
|
||||
supported speed of a usb3 port. Valid values are:
|
||||
- "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
|
||||
- "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
|
||||
|
||||
For Tegra124 and Tegra132, the XUSB pad controller exposes the following
|
||||
ports:
|
||||
- 3x USB2: usb2-0, usb2-1, usb2-2
|
||||
@ -233,6 +254,9 @@ For Tegra210, the XUSB pad controller exposes the following ports:
|
||||
- 2x HSIC: hsic-0, hsic-1
|
||||
- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
|
||||
|
||||
For Tegra194, the XUSB pad controller exposes the following ports:
|
||||
- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
|
||||
- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
|
||||
|
||||
Examples:
|
||||
=========
|
||||
|
190
Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml
Normal file
190
Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml
Normal file
@ -0,0 +1,190 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra XUSB device mode controller (XUDC)
|
||||
|
||||
description:
|
||||
The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and
|
||||
USB 3.0 SuperSpeed protocols.
|
||||
|
||||
maintainers:
|
||||
- Nagarjuna Kristam <nkristam@nvidia.com>
|
||||
- JC Kuo <jckuo@nvidia.com>
|
||||
- Thierry Reding <treding@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- nvidia,tegra210-xudc # For Tegra210
|
||||
- nvidia,tegra186-xudc # For Tegra186
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
- description: XUSB device controller registers
|
||||
- description: XUSB device PCI Config registers
|
||||
- description: XUSB device registers.
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
- const: base
|
||||
- const: fpci
|
||||
- const: ipfs
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: Must contain the XUSB device interrupt.
|
||||
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
items:
|
||||
- description: Clock to enable core XUSB dev clock.
|
||||
- description: Clock to enable XUSB super speed clock.
|
||||
- description: Clock to enable XUSB super speed dev clock.
|
||||
- description: Clock to enable XUSB high speed dev clock.
|
||||
- description: Clock to enable XUSB full speed dev clock.
|
||||
|
||||
clock-names:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
items:
|
||||
- const: dev
|
||||
- const: ss
|
||||
- const: ss_src
|
||||
- const: fs_src
|
||||
- const: hs_src
|
||||
|
||||
power-domains:
|
||||
maxItems: 2
|
||||
items:
|
||||
- description: XUSBB(device) power-domain
|
||||
- description: XUSBA(superspeed) power-domain
|
||||
|
||||
power-domain-names:
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: dev
|
||||
- const: ss
|
||||
|
||||
nvidia,xusb-padctl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
phandle to the XUSB pad controller that is used to configure the USB pads
|
||||
used by the XUDC controller.
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
description:
|
||||
Must contain an entry for each entry in phy-names.
|
||||
See ../phy/phy-bindings.txt for details.
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: usb2-0
|
||||
- const: usb2-1
|
||||
- const: usb2-2
|
||||
- const: usb2-3
|
||||
- const: usb3-0
|
||||
- const: usb3-1
|
||||
- const: usb3-2
|
||||
- const: usb3-3
|
||||
|
||||
avddio-usb-supply:
|
||||
description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
|
||||
hvdd-usb-supply:
|
||||
description: USB controller power supply. Must supply 3.3 V.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- nvidia,xusb-padctl
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra210-xudc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
reg-names:
|
||||
minItems: 3
|
||||
clocks:
|
||||
minItems: 5
|
||||
clock-names:
|
||||
minItems: 5
|
||||
required:
|
||||
- avddio-usb-supply
|
||||
- hvdd-usb-supply
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra186-xudc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 2
|
||||
reg-names:
|
||||
maxItems: 2
|
||||
clocks:
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
maxItems: 4
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
usb@700d0000 {
|
||||
compatible = "nvidia,tegra210-xudc";
|
||||
reg = <0x0 0x700d0000 0x0 0x8000>,
|
||||
<0x0 0x700d8000 0x0 0x1000>,
|
||||
<0x0 0x700d9000 0x0 0x1000>;
|
||||
reg-names = "base", "fpci", "ipfs";
|
||||
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_SS>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
|
||||
clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
|
||||
|
||||
power-domains = <&pd_xusbdev>, <&pd_xusbss>;
|
||||
power-domain-names = "dev", "ss";
|
||||
|
||||
nvidia,xusb-padctl = <&padctl>;
|
||||
|
||||
phys = <µ_b>;
|
||||
phy-names = "usb2-0";
|
||||
|
||||
avddio-usb-supply = <&vdd_pex_1v05>;
|
||||
hvdd-usb-supply = <&vdd_3v3_sys>;
|
||||
};
|
@ -228,6 +228,8 @@
|
||||
#define TEGRA114_CLK_CLK_M 201
|
||||
#define TEGRA114_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA114_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA114_CLK_OSC_DIV2 202
|
||||
#define TEGRA114_CLK_OSC_DIV4 203
|
||||
#define TEGRA114_CLK_PLL_REF 204
|
||||
#define TEGRA114_CLK_PLL_C 205
|
||||
#define TEGRA114_CLK_PLL_C_OUT1 206
|
||||
@ -274,7 +276,7 @@
|
||||
#define TEGRA114_CLK_CLK_OUT_2 246
|
||||
#define TEGRA114_CLK_CLK_OUT_3 247
|
||||
#define TEGRA114_CLK_BLINK 248
|
||||
/* 249 */
|
||||
#define TEGRA114_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA114_CLK_XUSB_HOST_SRC 252
|
||||
|
@ -227,6 +227,8 @@
|
||||
#define TEGRA124_CLK_CLK_M 201
|
||||
#define TEGRA124_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA124_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA124_CLK_OSC_DIV2 202
|
||||
#define TEGRA124_CLK_OSC_DIV4 203
|
||||
#define TEGRA124_CLK_PLL_REF 204
|
||||
#define TEGRA124_CLK_PLL_C 205
|
||||
#define TEGRA124_CLK_PLL_C_OUT1 206
|
||||
@ -273,7 +275,7 @@
|
||||
#define TEGRA124_CLK_CLK_OUT_2 246
|
||||
#define TEGRA124_CLK_CLK_OUT_3 247
|
||||
#define TEGRA124_CLK_BLINK 248
|
||||
/* 249 */
|
||||
#define TEGRA124_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA124_CLK_XUSB_HOST_SRC 252
|
||||
|
@ -262,6 +262,8 @@
|
||||
#define TEGRA210_CLK_CLK_M 233
|
||||
#define TEGRA210_CLK_CLK_M_DIV2 234
|
||||
#define TEGRA210_CLK_CLK_M_DIV4 235
|
||||
#define TEGRA210_CLK_OSC_DIV2 234
|
||||
#define TEGRA210_CLK_OSC_DIV4 235
|
||||
#define TEGRA210_CLK_PLL_REF 236
|
||||
#define TEGRA210_CLK_PLL_C 237
|
||||
#define TEGRA210_CLK_PLL_C_OUT1 238
|
||||
@ -355,7 +357,7 @@
|
||||
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
|
||||
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
|
||||
/* 325 */
|
||||
/* 326 */
|
||||
#define TEGRA210_CLK_OSC 326
|
||||
/* 327 */
|
||||
/* 328 */
|
||||
/* 329 */
|
||||
|
@ -196,6 +196,8 @@
|
||||
#define TEGRA30_CLK_CLK_M 171
|
||||
#define TEGRA30_CLK_CLK_M_DIV2 172
|
||||
#define TEGRA30_CLK_CLK_M_DIV4 173
|
||||
#define TEGRA30_CLK_OSC_DIV2 172
|
||||
#define TEGRA30_CLK_OSC_DIV4 173
|
||||
#define TEGRA30_CLK_PLL_REF 174
|
||||
#define TEGRA30_CLK_PLL_C 175
|
||||
#define TEGRA30_CLK_PLL_C_OUT1 176
|
||||
@ -243,7 +245,7 @@
|
||||
#define TEGRA30_CLK_HCLK 217
|
||||
#define TEGRA30_CLK_PCLK 218
|
||||
/* 219 */
|
||||
/* 220 */
|
||||
#define TEGRA30_CLK_OSC 220
|
||||
/* 221 */
|
||||
/* 222 */
|
||||
/* 223 */
|
||||
|
16
include/dt-bindings/soc/tegra-pmc.h
Normal file
16
include/dt-bindings/soc/tegra-pmc.h
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H
|
||||
#define _DT_BINDINGS_SOC_TEGRA_PMC_H
|
||||
|
||||
#define TEGRA_PMC_CLK_OUT_1 0
|
||||
#define TEGRA_PMC_CLK_OUT_2 1
|
||||
#define TEGRA_PMC_CLK_OUT_3 2
|
||||
#define TEGRA_PMC_CLK_BLINK 3
|
||||
|
||||
#define TEGRA_PMC_CLK_MAX 4
|
||||
|
||||
#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */
|
Loading…
Reference in New Issue
Block a user