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ARM: tegra: device tree changes for 3.18

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The main highlights are:
 * SATA and PCIe support added to Tegra124, and enabled on Jetson TK1.
 * Touchpad enabled on Venice2 (although the driver still has a few issues
   to be worked out).
 * NVIDIA reference boards rely on the bootloader to program the pinmux.
 * Support added for the Acer Chromebook 13 (CB5).
 * DT nodes added for the Tegra flow controller HW module. This will
   help reduce use of iomap.h in a future code cleanup.
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Merge tag 'tegra-for-3.18-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt

Pull "ARM: tegra: device tree changes for 3.18" from Stephen Warren:

The main highlights are:
* SATA and PCIe support added to Tegra124, and enabled on Jetson TK1.
* Touchpad enabled on Venice2 (although the driver still has a few issues
  to be worked out).
* NVIDIA reference boards rely on the bootloader to program the pinmux.
* Support added for the Acer Chromebook 13 (CB5).
* DT nodes added for the Tegra flow controller HW module. This will
  help reduce use of iomap.h in a future code cleanup.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

* tag 'tegra-for-3.18-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
  ARM: tegra: enable PCIe in Jetson TK1 DT
  ARM: tegra: add PCIe to Tegra124 DT
  ARM: tegra: rely on bootloader pinmux programming on Tegra124
  ARM: tegra: add Acer Chromebook 13 device tree
  ARM: tegra: Move pwm and dpaux labels to tegra124.dtsi
  ARM: tegra: add touchpad to Venice2 DT
  ARM: tegra: Add device tree nodes for flow controller
  ARM: tegra: add PCIe-related pins to the Jetson TK1 pinmux tables
  ARM: tegra: Add SATA and SATA power to Jetson TK1 device tree
  ARM: tegra: Add SATA controller to Tegra124 device tree
This commit is contained in:
Arnd Bergmann 2014-09-25 17:54:32 +02:00
commit ea62edd850
8 changed files with 1357 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -454,6 +454,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra114-roth.dtb \
tegra114-tn7.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \

5
arch/arm/boot/dts/tegra114.dtsi
View File

@ -157,6 +157,11 @@
#reset-cells = <1>;
};
flow-controller@60007000 {
compatible = "nvidia,tegra114-flowctrl";
reg = <0x60007000 0x1000>;
};
apbdma: dma@6000a000 {
compatible = "nvidia,tegra114-apbdma";
reg = <0x6000a000 0x1400>;

98
arch/arm/boot/dts/tegra124-jetson-tk1.dts
View File

@ -16,6 +16,26 @@
reg = <0x0 0x80000000 0x0 0x80000000>;
};
pcie-controller@0,01003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;
dvddio-pex-supply = <&vdd_1v05_run>;
avdd-pex-pll-supply = <&vdd_1v05_run>;
hvdd-pex-supply = <&vdd_3v3_lp0>;
hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
avdd-pll-erefe-supply = <&avdd_1v05_run>;
pci@1,0 {
status = "okay";
};
pci@2,0 {
status = "okay";
};
};
host1x@0,50000000 {
hdmi@0,54280000 {
status = "okay";
@ -31,10 +51,10 @@
};
pinmux: pinmux@0,70000868 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
pinctrl-names = "boot";
pinctrl-0 = <&state_boot>;
state_default: pinmux {
state_boot: pinmux {
clk_32k_out_pa0 {
nvidia,pins = "clk_32k_out_pa0";
nvidia,function = "soc";
@ -1231,6 +1251,41 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pex_l0_rst_n_pdd1 {
nvidia,pins = "pex_l0_rst_n_pdd1";
nvidia,function = "pe0";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pex_l0_clkreq_n_pdd2 {
nvidia,pins = "pex_l0_clkreq_n_pdd2";
nvidia,function = "pe0";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pex_wake_n_pdd3 {
nvidia,pins = "pex_wake_n_pdd3";
nvidia,function = "pe";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pex_l1_rst_n_pdd5 {
nvidia,pins = "pex_l1_rst_n_pdd5";
nvidia,function = "pe1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pex_l1_clkreq_n_pdd6 {
nvidia,pins = "pex_l1_clkreq_n_pdd6";
nvidia,function = "pe1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
clk3_out_pee0 {
nvidia,pins = "clk3_out_pee0";
nvidia,function = "extperiph3";
@ -1515,7 +1570,7 @@
regulator-always-on;
};
ldo0 {
avdd_1v05_run: ldo0 {
regulator-name = "+1.05V_RUN_AVDD";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
@ -1619,6 +1674,18 @@
nvidia,sys-clock-req-active-high;
};
/* Serial ATA */
sata@0,70020000 {
status = "okay";
hvdd-supply = <&vdd_3v3_lp0>;
vddio-supply = <&vdd_1v05_run>;
avdd-supply = <&vdd_1v05_run>;
target-5v-supply = <&vdd_5v0_sata>;
target-12v-supply = <&vdd_12v0_sata>;
};
padctl@0,7009f000 {
pinctrl-0 = <&padctl_default>;
pinctrl-names = "default";
@ -1828,6 +1895,29 @@
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
/* Molex power connector */
vdd_5v0_sata: regulator@13 {
compatible = "regulator-fixed";
reg = <13>;
regulator-name = "+5V_SATA";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
vdd_12v0_sata: regulator@14 {
compatible = "regulator-fixed";
reg = <14>;
regulator-name = "+12V_SATA";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_mux>;
};
};
sound {

1136
arch/arm/boot/dts/tegra124-nyan-big.dts Normal file
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File diff suppressed because it is too large Load Diff

18
arch/arm/boot/dts/tegra124-venice2.dts
View File

@ -36,17 +36,17 @@
nvidia,panel = <&panel>;
};
dpaux: dpaux@0,545c0000 {
dpaux@0,545c0000 {
vdd-supply = <&vdd_3v3_panel>;
status = "okay";
};
};
pinmux: pinmux@0,70000868 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
pinctrl-names = "boot";
pinctrl-0 = <&pinmux_boot>;
pinmux_default: common {
pinmux_boot: common {
dap_mclk1_pw4 {
nvidia,pins = "dap_mclk1_pw4";
nvidia,function = "extperiph1";
@ -587,7 +587,7 @@
status = "okay";
};
pwm: pwm@0,7000a000 {
pwm@0,7000a000 {
status = "okay";
};
@ -606,6 +606,14 @@
i2c@0,7000c400 {
status = "okay";
clock-frequency = <100000>;
trackpad@4b {
compatible = "atmel,maxtouch";
reg = <0x4b>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
linux,gpio-keymap = <0 0 0 BTN_LEFT>;
};
};
i2c@0,7000c500 {

100
arch/arm/boot/dts/tegra124.dtsi
View File

@ -12,6 +12,72 @@
#address-cells = <2>;
#size-cells = <2>;
pcie-controller@0,01003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
0x0 0x01003800 0x0 0x00000800 /* AFI registers */
0x0 0x02000000 0x0 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
interrupt-names = "intr", "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
clocks = <&tegra_car TEGRA124_CLK_PCIE>,
<&tegra_car TEGRA124_CLK_AFI>,
<&tegra_car TEGRA124_CLK_PLL_E>,
<&tegra_car TEGRA124_CLK_CML0>;
clock-names = "pex", "afi", "pll_e", "cml";
resets = <&tegra_car 70>,
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
status = "disabled";
phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
phy-names = "pcie";
pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <2>;
};
pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <1>;
};
};
host1x@0,50000000 {
compatible = "nvidia,tegra124-host1x", "simple-bus";
reg = <0x0 0x50000000 0x0 0x00034000>;
@ -78,7 +144,7 @@
status = "disabled";
};
dpaux@0,545c0000 {
dpaux: dpaux@0,545c0000 {
compatible = "nvidia,tegra124-dpaux";
reg = <0x0 0x545c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
@ -137,6 +203,11 @@
#reset-cells = <1>;
};
flow-controller@0,60007000 {
compatible = "nvidia,tegra124-flowctrl";
reg = <0x0 0x60007000 0x0 0x1000>;
};
gpio: gpio@0,6000d000 {
compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
@ -267,7 +338,7 @@
status = "disabled";
};
pwm@0,7000a000 {
pwm: pwm@0,7000a000 {
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
reg = <0x0 0x7000a000 0x0 0x100>;
#pwm-cells = <2>;
@ -480,6 +551,31 @@
reset-names = "fuse";
};
sata@0,70020000 {
compatible = "nvidia,tegra124-ahci";
reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
<0x0 0x70020000 0x0 0x7000>; /* SATA */
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SATA>,
<&tegra_car TEGRA124_CLK_SATA_OOB>,
<&tegra_car TEGRA124_CLK_CML1>,
<&tegra_car TEGRA124_CLK_PLL_E>;
clock-names = "sata", "sata-oob", "cml1", "pll_e";
resets = <&tegra_car 124>,
<&tegra_car 123>,
<&tegra_car 129>;
reset-names = "sata", "sata-oob", "sata-cold";
phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
phy-names = "sata-phy";
status = "disabled";
};
hda@0,70030000 {
compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
reg = <0x0 0x70030000 0x0 0x10000>;

5
arch/arm/boot/dts/tegra20.dtsi
View File

@ -190,6 +190,11 @@
#reset-cells = <1>;
};
flow-controller@60007000 {
compatible = "nvidia,tegra20-flowctrl";
reg = <0x60007000 0x1000>;
};
apbdma: dma@6000a000 {
compatible = "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1200>;

5
arch/arm/boot/dts/tegra30.dtsi
View File

@ -272,6 +272,11 @@
#reset-cells = <1>;
};
flow-controller@60007000 {
compatible = "nvidia,tegra30-flowctrl";
reg = <0x60007000 0x1000>;
};
apbdma: dma@6000a000 {
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
reg = <0x6000a000 0x1400>;