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perf: RISC-V: Eliminate redundant interrupt enable/disable operations
The interrupt enable/disable operations are already performed by the IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during enable_percpu_irq()/disable_percpu_irq(). It can be done only once. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20240222083946.3977135-7-peterlin@andestech.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
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if (riscv_pmu_use_irq) {
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cpu_hw_evt->irq = riscv_pmu_irq;
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csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
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csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
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enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
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}
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@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
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{
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if (riscv_pmu_use_irq) {
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disable_percpu_irq(riscv_pmu_irq);
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csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
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}
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/* Disable all counters access for user mode now */
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