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clk: qcom: regmap-mux: add pipe clk implementation

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On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
muxes which must be parked to the "safe" source (bi_tcxo) when
corresponding GDSC is turned off and on again. Currently this is
handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
clock. However the same code sequence should be applied in the
pcie-qcom endpoint, USB3 and UFS drivers.

Rather than copying this sequence over and over again, follow the
example of clk_rcg2_shared_ops and implement this parking in the
enable() and disable() clock operations. As we are changing the parent
behind the back of the clock framework, also implement custom
set_parent() and get_parent() operations behaving accroding to the clock
framework expectations (cache the new parent if the clock is in disabled
state, return cached parent).

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220323085010.1753493-2-dmitry.baryshkov@linaro.org
This commit is contained in:
Dmitry Baryshkov 2022-03-23 11:50:06 +03:00 committed by Bjorn Andersson
parent 3123109284
commit e9a4c7f667
2 changed files with 81 additions and 0 deletions
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78
drivers/clk/qcom/clk-regmap-mux.c
View File

@ -49,9 +49,87 @@ static int mux_set_parent(struct clk_hw *hw, u8 index)
return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
}
static u8 mux_safe_get_parent(struct clk_hw *hw)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
unsigned int val;
if (clk_hw_is_enabled(hw))
return mux_get_parent(hw);
val = mux->stored_parent_cfg;
if (mux->parent_map)
return qcom_find_cfg_index(hw, mux->parent_map, val);
return val;
}
static int mux_safe_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
if (clk_hw_is_enabled(hw))
return mux_set_parent(hw, index);
if (mux->parent_map)
index = mux->parent_map[index].cfg;
mux->stored_parent_cfg = index;
return 0;
}
static void mux_safe_disable(struct clk_hw *hw)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
struct clk_regmap *clkr = to_clk_regmap(hw);
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
regmap_read(clkr->regmap, mux->reg, &val);
mux->stored_parent_cfg = (val & mask) >> mux->shift;
val = mux->safe_src_parent;
if (mux->parent_map) {
int index = qcom_find_src_index(hw, mux->parent_map, val);
if (WARN_ON(index < 0))
return;
val = mux->parent_map[index].cfg;
}
val <<= mux->shift;
regmap_update_bits(clkr->regmap, mux->reg, mask, val);
}
static int mux_safe_enable(struct clk_hw *hw)
{
struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
struct clk_regmap *clkr = to_clk_regmap(hw);
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
val = mux->stored_parent_cfg;
val <<= mux->shift;
return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
}
const struct clk_ops clk_regmap_mux_closest_ops = {
.get_parent = mux_get_parent,
.set_parent = mux_set_parent,
.determine_rate = __clk_mux_determine_rate_closest,
};
EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);
const struct clk_ops clk_regmap_mux_safe_ops = {
.enable = mux_safe_enable,
.disable = mux_safe_disable,
.get_parent = mux_safe_get_parent,
.set_parent = mux_safe_set_parent,
.determine_rate = __clk_mux_determine_rate_closest,
};
EXPORT_SYMBOL_GPL(clk_regmap_mux_safe_ops);

3
drivers/clk/qcom/clk-regmap-mux.h
View File

@ -14,10 +14,13 @@ struct clk_regmap_mux {
u32 reg;
u32 shift;
u32 width;
u8 safe_src_parent;
u8 stored_parent_cfg;
const struct parent_map *parent_map;
struct clk_regmap clkr;
};
extern const struct clk_ops clk_regmap_mux_closest_ops;
extern const struct clk_ops clk_regmap_mux_safe_ops;
#endif