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parisc: Implement __smp_store_release and __smp_load_acquire barriers
This patch implements the __smp_store_release and __smp_load_acquire barriers using ordered stores and loads. This avoids the sync instruction present in the generic implementation. Cc: <stable@vger.kernel.org> # 4.14+ Signed-off-by: Dave Anglin <dave.anglin@bell.net> Signed-off-by: Helge Deller <deller@gmx.de>
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@ -26,6 +26,67 @@
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#define __smp_rmb() mb()
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#define __smp_wmb() mb()
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#define __smp_store_release(p, v) \
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do { \
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typeof(p) __p = (p); \
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union { typeof(*p) __val; char __c[1]; } __u = \
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{ .__val = (__force typeof(*p)) (v) }; \
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compiletime_assert_atomic_type(*p); \
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switch (sizeof(*p)) { \
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case 1: \
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asm volatile("stb,ma %0,0(%1)" \
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: : "r"(*(__u8 *)__u.__c), "r"(__p) \
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: "memory"); \
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break; \
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case 2: \
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asm volatile("sth,ma %0,0(%1)" \
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: : "r"(*(__u16 *)__u.__c), "r"(__p) \
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: "memory"); \
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break; \
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case 4: \
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asm volatile("stw,ma %0,0(%1)" \
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: : "r"(*(__u32 *)__u.__c), "r"(__p) \
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: "memory"); \
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break; \
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case 8: \
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if (IS_ENABLED(CONFIG_64BIT)) \
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asm volatile("std,ma %0,0(%1)" \
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: : "r"(*(__u64 *)__u.__c), "r"(__p) \
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: "memory"); \
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break; \
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} \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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union { typeof(*p) __val; char __c[1]; } __u; \
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typeof(p) __p = (p); \
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compiletime_assert_atomic_type(*p); \
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switch (sizeof(*p)) { \
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case 1: \
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asm volatile("ldb,ma 0(%1),%0" \
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: "=r"(*(__u8 *)__u.__c) : "r"(__p) \
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: "memory"); \
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break; \
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case 2: \
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asm volatile("ldh,ma 0(%1),%0" \
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: "=r"(*(__u16 *)__u.__c) : "r"(__p) \
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: "memory"); \
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break; \
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case 4: \
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asm volatile("ldw,ma 0(%1),%0" \
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: "=r"(*(__u32 *)__u.__c) : "r"(__p) \
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: "memory"); \
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break; \
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case 8: \
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if (IS_ENABLED(CONFIG_64BIT)) \
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asm volatile("ldd,ma 0(%1),%0" \
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: "=r"(*(__u64 *)__u.__c) : "r"(__p) \
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: "memory"); \
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break; \
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} \
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__u.__val; \
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})
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#include <asm-generic/barrier.h>
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#endif /* !__ASSEMBLY__ */
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