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Arm FVP/Juno device tree updates for v5.19
The main and bulk of the change is the addition of new platform Arm corstone1000(both FVP and FPGA versions). Also, there are addition of Coresight Cross Trigger Interface(CTI) support on Juno, fix for incorrect SCMI power domain IDs, addition of virtio-rng on FVP which is default disabled as it works only on latest versions of the FVP model. Other miscellanous changes include dropping of useless 'dma-channels/requests' properties and updating virtio device node names as per dtschema. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmJyPcUACgkQAEG6vDF+ 4pizDw/+NzmnScLZFzwXKi8LqKIuC+JlDf+mvWGlidjjz2c1X4Mf45AKPpKvRQmc PyvVKB7t6azo9xHcgS43J7+DOFOziqjY/+RJhiQ7YS8L/SSSuaNDyAO3EpWpIo85 c2QL9sFsiVPqQFmF+E4cLh96gF97xi2QfB2420E5m7feLzCgHQZYYWijhGVlZR5L nsoXLDU/HK9MTts3q9jyen3gA2nBE7NGuU2SacehJNXoHCd+T0W6AQgYWIWzWa+X eq/PbbnFCguFyzNRncbnxzCVOXeg0FS1zTPOtJFNHioG6FnIEqg4VEF9g2hdtnTZ CGEtu4vvVsSKxIr7s2d/vfqlYpOpxwVkJl3XgNcqLXTgk4tHWODW7Rl7RTXwT3hT mgh0j272/4gm+iTDYI+YmanQsEKP/VQiMGXDVTX43da2rgFVXUMU/XT1EHy7Ef0P iULL5sqcA0q9Y895AV6aeMXZdQl9ZHYYgLxQLPecMVt+dMfde1LxaRssH3YQ+aLN u0ZO/SOYRXqe1AbJvgC2xKPH6URmNAHHg6urVsOPI14Zj+q+zdz7M2/Ii1cu6o5O EvISCqoNU0Wazcnfg6Khp6MwnPxKVIHl0w3C0Z4qZjVIzzSF0VTomy1W3FJHEZuf 9HSB0BopmOM8FQzAOJnHYjHIXT7jhhjACmapdi4U1d+XGqw1ih4= =dlOE -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJz4x8ACgkQmmx57+YA GNkV+A/+OUattSEzS2yaSUDbHC9KjWEEZvPZduQr6EI7rjOlpqeWIlkL0Neh4fce UCQNkk3m6VmJmL+b0YljZZPTK+ajH0cPqb8Rp4EDhaqivhLAiaqRW7v6zMj621rQ QXA+7DZ0jh8OXkgJJJaDTAEotFAv+NZ95Ca+AbE31Zi5BfHfe0nQs6s+BJYGmt76 I3hK6ZCgfa4T/ubFariJsFxbZisWbuMjQJIw5Z+PC7sGPYEx00xiws7L/8apBxTt XHz4NF02qA0wV28W6TyQdTN8q+8t/1yAG7wd2cFic5RJl7KNH+SP9WsL2jMLscvM QjoFdEg7RM80slFFHI3HUvcC5+2KiqzkvhKbXAG5lqXtgk1Q0I+aLi795TRRhrXu IxPubqvBqOd8MLUUIeU+qf3KFAVdtB1ly/tRCFaF5m3U4v8naE063rO3IMuojQmk BaCfbBB7vfa50ETSVYwT/APq2U+V6LOH1nvIP8kgltiqd70XZFyGs9cIgdcVZE3w a11PPgl/Ux2kKnf8YaRr4vckn+MZ7ByBEEDaHPmbRRlup+n2sMX8q3w1sfYoVI5C /IVS3XGxBWkVb3FGoOA4PllIdf9FWr00TIC3N/+3R12WpJ76ACVd+kVlB/GVNMkM QY3GaetMUZ4OMm93mXwqg0yACA6arfvRbd/TrTdoRGwb2EYehFs= =o+6w -----END PGP SIGNATURE----- Merge tag 'juno-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt Arm FVP/Juno device tree updates for v5.19 The main and bulk of the change is the addition of new platform Arm corstone1000(both FVP and FPGA versions). Also, there are addition of Coresight Cross Trigger Interface(CTI) support on Juno, fix for incorrect SCMI power domain IDs, addition of virtio-rng on FVP which is default disabled as it works only on latest versions of the FVP model. Other miscellanous changes include dropping of useless 'dma-channels/requests' properties and updating virtio device node names as per dtschema. * tag 'juno-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: Drop useless 'dma-channels/requests' properties arm64: dts: fvp: Align virtio device node names with dtschema arm64: dts: fvp: Add virtio-rng support arm64: dts: Add Arm corstone1000 platform support dt-bindings: Add Arm corstone1000 platform arm64: dts: juno: add CTI entries to device tree arm64: dts: juno: Fix SCMI power domain IDs for ETF and CS funnel Link: https://lore.kernel.org/r/20220504112917.3492009-1-sudeep.holla@arm.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
e8bcacdaf1
45
Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
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45
Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
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@ -0,0 +1,45 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Corstone1000 Device Tree Bindings
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maintainers:
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- Vishnu Banavath <vishnu.banavath@arm.com>
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- Rui Miguel Silva <rui.silva@linaro.org>
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description: |+
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ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
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provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
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processors.
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Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
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systems for M-Class (or other) processors for adding sensors, connectivity,
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video, audio and machine learning at the edge System and security IPs to build
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a secure SoC for a range of rich IoT applications, for example gateways, smart
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cameras and embedded systems.
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Integrated Secure Enclave providing hardware Root of Trust and supporting
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seamless integration of the optional CryptoCell™-312 cryptographic
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accelerator.
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
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implementation of the Corstone1000 in the MPS3 prototyping board. See
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ARM document DAI0550.
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items:
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- const: arm,corstone1000-mps3
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- description: Corstone1000 FVP is the Fixed Virtual Platform
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implementation of this system. See ARM ecosystems FVP's.
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items:
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- const: arm,corstone1000-fvp
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additionalProperties: true
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...
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@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju
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dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
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51
arch/arm64/boot/dts/arm/corstone1000-fvp.dts
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51
arch/arm64/boot/dts/arm/corstone1000-fvp.dts
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@ -0,0 +1,51 @@
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// SPDX-License-Identifier: GPL-2.0 or MIT
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* Copyright (c) 2022, Linaro Limited. All rights reserved.
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*
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*/
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/dts-v1/;
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#include "corstone1000.dtsi"
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/ {
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model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
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compatible = "arm,corstone1000-fvp";
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smsc: ethernet@4010000 {
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compatible = "smsc,lan91c111";
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reg = <0x40100000 0x10000>;
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phy-mode = "mii";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <2>;
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};
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vmmc_v3_3d: fixed_v3_3d {
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compatible = "regulator-fixed";
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regulator-name = "vmmc_supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sdmmc0: mmc@40300000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x40300000 0x1000>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <12000000>;
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vmmc-supply = <&vmmc_v3_3d>;
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clocks = <&smbclk>, <&refclk100mhz>;
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clock-names = "smclk", "apb_pclk";
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};
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sdmmc1: mmc@50000000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x50000000 0x10000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <12000000>;
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vmmc-supply = <&vmmc_v3_3d>;
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clocks = <&smbclk>, <&refclk100mhz>;
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clock-names = "smclk", "apb_pclk";
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};
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};
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32
arch/arm64/boot/dts/arm/corstone1000-mps3.dts
Normal file
32
arch/arm64/boot/dts/arm/corstone1000-mps3.dts
Normal file
@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0 or MIT
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* Copyright (c) 2022, Linaro Limited. All rights reserved.
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*
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*/
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/dts-v1/;
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#include "corstone1000.dtsi"
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/ {
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model = "ARM Corstone1000 FPGA MPS3 board";
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compatible = "arm,corstone1000-mps3";
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smsc: ethernet@4010000 {
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compatible = "smsc,lan9220", "smsc,lan9115";
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reg = <0x40100000 0x10000>;
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phy-mode = "mii";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <2>;
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smsc,irq-push-pull;
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};
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usb_host: usb@40200000 {
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compatible = "nxp,usb-isp1763";
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reg = <0x40200000 0x100000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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bus-width = <16>;
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dr_mode = "host";
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};
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};
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164
arch/arm64/boot/dts/arm/corstone1000.dtsi
Normal file
164
arch/arm64/boot/dts/arm/corstone1000.dtsi
Normal file
@ -0,0 +1,164 @@
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// SPDX-License-Identifier: GPL-2.0 or MIT
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* Copyright (c) 2022, Linaro Limited. All rights reserved.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0>;
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next-level-cache = <&L2_0>;
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};
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};
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memory@88200000 {
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device_type = "memory";
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reg = <0x88200000 0x77e00000>;
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};
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gic: interrupt-controller@1c000000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1c010000 0x1000>,
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<0x1c02f000 0x2000>,
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<0x1c04f000 0x1000>,
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<0x1c06f000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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};
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refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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smbclk: refclk24mhzx2 {
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/* Reference 24MHz clock x 2 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "smclk";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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uartclk: uartclk {
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/* UART clock - 50MHz */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "uartclk";
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges;
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timer@1a220000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x1a220000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-frequency = <50000000>;
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ranges;
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frame@1a230000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1a230000 0x1000>;
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};
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};
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uart0: serial@1a510000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a510000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: serial@1a520000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a520000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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mhu_hse1: mailbox@1b820000 {
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compatible = "arm,mhuv2-tx", "arm,primecell";
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reg = <0x1b820000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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arm,mhuv2-protocols = <0 0>;
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secure-status = "okay"; /* secure-world-only */
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status = "disabled";
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};
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mhu_seh1: mailbox@1b830000 {
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compatible = "arm,mhuv2-rx", "arm,primecell";
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reg = <0x1b830000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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arm,mhuv2-protocols = <0 0>;
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secure-status = "okay"; /* secure-world-only */
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status = "disabled";
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};
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};
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};
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@ -220,7 +220,7 @@
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clock-names = "uartclk", "apb_pclk";
|
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};
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virtio-block@130000 {
|
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virtio@130000 {
|
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compatible = "virtio,mmio";
|
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reg = <0x130000 0x200>;
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interrupts = <42>;
|
||||
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@ -241,6 +241,7 @@
|
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<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
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<0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -117,7 +117,7 @@
|
||||
* The actual size is just 4K though 64K is reserved. Access to the
|
||||
* unmapped reserved region results in a DECERR response.
|
||||
*/
|
||||
etf@20010000 { /* etf0 */
|
||||
etf_sys0: etf@20010000 { /* etf0 */
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20010000 0 0x1000>;
|
||||
|
||||
@ -141,7 +141,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
tpiu@20030000 {
|
||||
tpiu_sys: tpiu@20030000 {
|
||||
compatible = "arm,coresight-tpiu", "arm,primecell";
|
||||
reg = <0 0x20030000 0 0x1000>;
|
||||
|
||||
@ -194,7 +194,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
etr@20070000 {
|
||||
etr_sys: etr@20070000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20070000 0 0x1000>;
|
||||
iommus = <&smmu_etr 0>;
|
||||
@ -212,7 +212,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
stm@20100000 {
|
||||
stm_sys: stm@20100000 {
|
||||
compatible = "arm,coresight-stm", "arm,primecell";
|
||||
reg = <0 0x20100000 0 0x1000>,
|
||||
<0 0x28000000 0 0x1000000>;
|
||||
@ -289,6 +289,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
cti0: cti@22020000 {
|
||||
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
|
||||
"arm,primecell";
|
||||
reg = <0 0x22020000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
arm,cs-dev-assoc = <&etm0>;
|
||||
};
|
||||
|
||||
funnel@220c0000 { /* cluster0 funnel */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x220c0000 0 0x1000>;
|
||||
@ -349,6 +361,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
cti1: cti@22120000 {
|
||||
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
|
||||
"arm,primecell";
|
||||
reg = <0 0x22120000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
arm,cs-dev-assoc = <&etm1>;
|
||||
};
|
||||
|
||||
cpu_debug2: cpu-debug@23010000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x23010000 0x0 0x1000>;
|
||||
@ -374,6 +398,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
cti2: cti@23020000 {
|
||||
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
|
||||
"arm,primecell";
|
||||
reg = <0 0x23020000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
arm,cs-dev-assoc = <&etm2>;
|
||||
};
|
||||
|
||||
funnel@230c0000 { /* cluster1 funnel */
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x230c0000 0 0x1000>;
|
||||
@ -446,6 +482,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
cti3: cti@23120000 {
|
||||
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
|
||||
"arm,primecell";
|
||||
reg = <0 0x23120000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
arm,cs-dev-assoc = <&etm3>;
|
||||
};
|
||||
|
||||
cpu_debug4: cpu-debug@23210000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x23210000 0x0 0x1000>;
|
||||
@ -471,6 +519,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
cti4: cti@23220000 {
|
||||
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
|
||||
"arm,primecell";
|
||||
reg = <0 0x23220000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
arm,cs-dev-assoc = <&etm4>;
|
||||
};
|
||||
|
||||
cpu_debug5: cpu-debug@23310000 {
|
||||
compatible = "arm,coresight-cpu-debug", "arm,primecell";
|
||||
reg = <0x0 0x23310000 0x0 0x1000>;
|
||||
@ -496,6 +556,100 @@
|
||||
};
|
||||
};
|
||||
|
||||
cti5: cti@23320000 {
|
||||
compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
|
||||
"arm,primecell";
|
||||
reg = <0 0x23320000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
arm,cs-dev-assoc = <&etm5>;
|
||||
};
|
||||
|
||||
cti_sys0: cti@20020000 { /* sys_cti_0 */
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0 0x20020000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
trig-conns@0 {
|
||||
reg = <0>;
|
||||
arm,trig-in-sigs=<2 3>;
|
||||
arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
|
||||
arm,trig-out-sigs=<0 1>;
|
||||
arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
|
||||
arm,cs-dev-assoc = <&etr_sys>;
|
||||
};
|
||||
|
||||
trig-conns@1 {
|
||||
reg = <1>;
|
||||
arm,trig-in-sigs=<0 1>;
|
||||
arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
|
||||
arm,trig-out-sigs=<7 6>;
|
||||
arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
|
||||
arm,cs-dev-assoc = <&etf_sys0>;
|
||||
};
|
||||
|
||||
trig-conns@2 {
|
||||
reg = <2>;
|
||||
arm,trig-in-sigs=<4 5 6 7>;
|
||||
arm,trig-in-types=<STM_TOUT_SPTE STM_TOUT_SW
|
||||
STM_TOUT_HETE STM_ASYNCOUT>;
|
||||
arm,trig-out-sigs=<4 5>;
|
||||
arm,trig-out-types=<STM_HWEVENT STM_HWEVENT>;
|
||||
arm,cs-dev-assoc = <&stm_sys>;
|
||||
};
|
||||
|
||||
trig-conns@3 {
|
||||
reg = <3>;
|
||||
arm,trig-out-sigs=<2 3>;
|
||||
arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
|
||||
arm,cs-dev-assoc = <&tpiu_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
cti_sys1: cti@20110000 { /* sys_cti_1 */
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0 0x20110000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
trig-conns@0 {
|
||||
reg = <0>;
|
||||
arm,trig-in-sigs=<0>;
|
||||
arm,trig-in-types=<GEN_INTREQ>;
|
||||
arm,trig-out-sigs=<0>;
|
||||
arm,trig-out-types=<GEN_HALTREQ>;
|
||||
arm,trig-conn-name = "sys_profiler";
|
||||
};
|
||||
|
||||
trig-conns@1 {
|
||||
reg = <1>;
|
||||
arm,trig-out-sigs=<2 3>;
|
||||
arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
|
||||
arm,trig-conn-name = "watchdog";
|
||||
};
|
||||
|
||||
trig-conns@2 {
|
||||
reg = <2>;
|
||||
arm,trig-out-sigs=<1 6>;
|
||||
arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
|
||||
arm,trig-conn-name = "g_counter";
|
||||
};
|
||||
};
|
||||
|
||||
gpu: gpu@2d000000 {
|
||||
compatible = "arm,juno-mali", "arm,mali-t624";
|
||||
reg = <0 0x2d000000 0 0x10000>;
|
||||
@ -675,8 +829,6 @@
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0x7ff00000 0 0x1000>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
etf@20140000 { /* etf1 */
|
||||
etf_sys1: etf@20140000 { /* etf1 */
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x20140000 0 0x1000>;
|
||||
|
||||
@ -82,4 +82,39 @@
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
cti_sys2: cti@20160000 { /* sys_cti_2 */
|
||||
compatible = "arm,coresight-cti", "arm,primecell";
|
||||
reg = <0 0x20160000 0 0x1000>;
|
||||
|
||||
clocks = <&soc_smc50mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
power-domains = <&scpi_devpd 0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
trig-conns@0 {
|
||||
reg = <0>;
|
||||
arm,trig-in-sigs=<0 1>;
|
||||
arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
|
||||
arm,trig-out-sigs=<0 1>;
|
||||
arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
|
||||
arm,cs-dev-assoc = <&etf_sys1>;
|
||||
};
|
||||
|
||||
trig-conns@1 {
|
||||
reg = <1>;
|
||||
arm,trig-in-sigs=<2 3 4>;
|
||||
arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
|
||||
arm,trig-conn-name = "ela_clus_0";
|
||||
};
|
||||
|
||||
trig-conns@2 {
|
||||
reg = <2>;
|
||||
arm,trig-in-sigs=<5 6 7>;
|
||||
arm,trig-in-types=<ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
|
||||
arm,trig-conn-name = "ela_clus_1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -7,14 +7,18 @@
|
||||
};
|
||||
|
||||
etf@20140000 {
|
||||
power-domains = <&scmi_devpd 0>;
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
|
||||
funnel@20150000 {
|
||||
power-domains = <&scmi_devpd 0>;
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cti_sys2 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
|
||||
&A57_0 {
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
};
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/arm/coresight-cti-dt.h>
|
||||
#include "juno-base.dtsi"
|
||||
#include "juno-cs-r1r2.dtsi"
|
||||
|
||||
@ -313,3 +314,27 @@
|
||||
&cpu_debug5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
&cti0 {
|
||||
cpu = <&A57_0>;
|
||||
};
|
||||
|
||||
&cti1 {
|
||||
cpu = <&A57_1>;
|
||||
};
|
||||
|
||||
&cti2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&cti3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&cti4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&cti5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
@ -7,14 +7,18 @@
|
||||
};
|
||||
|
||||
etf@20140000 {
|
||||
power-domains = <&scmi_devpd 0>;
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
|
||||
funnel@20150000 {
|
||||
power-domains = <&scmi_devpd 0>;
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cti_sys2 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
|
||||
&A72_0 {
|
||||
clocks = <&scmi_dvfs 0>;
|
||||
};
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/arm/coresight-cti-dt.h>
|
||||
#include "juno-base.dtsi"
|
||||
#include "juno-cs-r1r2.dtsi"
|
||||
|
||||
@ -319,3 +320,27 @@
|
||||
&cpu_debug5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
&cti0 {
|
||||
cpu = <&A72_0>;
|
||||
};
|
||||
|
||||
&cti1 {
|
||||
cpu = <&A72_1>;
|
||||
};
|
||||
|
||||
&cti2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&cti3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&cti4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&cti5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
@ -154,6 +154,31 @@
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
|
||||
&cti0 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
&cti1 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
&cti2 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
&cti3 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
&cti4 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
&cti5 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
&cti_sys0 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
&cti_sys1 {
|
||||
power-domains = <&scmi_devpd 8>;
|
||||
};
|
||||
|
||||
&gpu {
|
||||
clocks = <&scmi_dvfs 2>;
|
||||
power-domains = <&scmi_devpd 9>;
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/arm/coresight-cti-dt.h>
|
||||
#include "juno-base.dtsi"
|
||||
|
||||
/ {
|
||||
@ -295,3 +296,27 @@
|
||||
&cpu_debug5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
&cti0 {
|
||||
cpu = <&A57_0>;
|
||||
};
|
||||
|
||||
&cti1 {
|
||||
cpu = <&A57_1>;
|
||||
};
|
||||
|
||||
&cti2 {
|
||||
cpu = <&A53_0>;
|
||||
};
|
||||
|
||||
&cti3 {
|
||||
cpu = <&A53_1>;
|
||||
};
|
||||
|
||||
&cti4 {
|
||||
cpu = <&A53_2>;
|
||||
};
|
||||
|
||||
&cti5 {
|
||||
cpu = <&A53_3>;
|
||||
};
|
||||
|
||||
@ -10,17 +10,24 @@
|
||||
arm,v2m-memory-map = "rs2";
|
||||
|
||||
iofpga-bus@300000000 {
|
||||
virtio-p9@140000 {
|
||||
virtio@140000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x140000 0x200>;
|
||||
interrupts = <43>;
|
||||
};
|
||||
|
||||
virtio-net@150000 {
|
||||
virtio@150000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x150000 0x200>;
|
||||
interrupts = <44>;
|
||||
};
|
||||
|
||||
virtio@200000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x200000 0x200>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -110,7 +110,7 @@
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 3 0 0x200000>;
|
||||
ranges = <0 3 0 0x210000>;
|
||||
|
||||
v2m_sysreg: sysreg@10000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
@ -222,7 +222,7 @@
|
||||
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||
};
|
||||
|
||||
virtio-block@130000 {
|
||||
virtio@130000 {
|
||||
compatible = "virtio,mmio";
|
||||
reg = <0x130000 0x200>;
|
||||
interrupts = <42>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user