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drm/gma500/cdv: Cedarview display cleanups
Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
This commit is contained in:
parent
19519943ef
commit
e85cbbf914
@ -412,8 +412,11 @@ static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
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int refclk,
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struct gma_clock_t *best_clock)
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{
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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struct gma_clock_t clock;
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if (refclk == 27000) {
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switch (refclk) {
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case 27000:
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if (target < 200000) {
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clock.p1 = 2;
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clock.p2 = 10;
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@ -427,7 +430,9 @@ static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
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clock.m1 = 0;
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clock.m2 = 98;
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}
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} else if (refclk == 100000) {
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break;
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case 100000:
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if (target < 200000) {
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clock.p1 = 2;
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clock.p2 = 10;
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@ -441,12 +446,13 @@ static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
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clock.m1 = 0;
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clock.m2 = 133;
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}
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} else
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break;
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default:
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return false;
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clock.m = clock.m2 + 2;
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clock.p = clock.p1 * clock.p2;
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clock.vco = (refclk * clock.m) / clock.n;
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clock.dot = clock.vco / clock.p;
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}
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gma_crtc->clock_funcs->clock(refclk, &clock);
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memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
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return true;
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}
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@ -468,49 +474,6 @@ static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
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return true;
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}
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static bool cdv_intel_single_pipe_active (struct drm_device *dev)
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{
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uint32_t pipe_enabled = 0;
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if (cdv_intel_pipe_enabled(dev, 0))
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pipe_enabled |= FIFO_PIPEA;
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if (cdv_intel_pipe_enabled(dev, 1))
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pipe_enabled |= FIFO_PIPEB;
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DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
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if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
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return true;
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else
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return false;
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}
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static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
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{
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
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if (gma_crtc->pipe != 1)
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return false;
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list_for_each_entry(connector, &mode_config->connector_list, head) {
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struct gma_encoder *gma_encoder =
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gma_attached_encoder(connector);
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if (!connector->encoder
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|| connector->encoder->crtc != crtc)
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continue;
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if (gma_encoder->type == INTEL_OUTPUT_LVDS)
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return true;
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}
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return false;
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}
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void cdv_disable_sr(struct drm_device *dev)
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{
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if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
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@ -535,8 +498,10 @@ void cdv_disable_sr(struct drm_device *dev)
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void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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if (cdv_intel_single_pipe_active(dev)) {
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/* Is only one pipe enabled? */
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if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
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u32 fw;
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fw = REG_READ(DSPFW1);
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@ -557,7 +522,9 @@ void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
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/* ignore FW4 */
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if (is_pipeb_lvds(dev, crtc)) {
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/* Is pipe b lvds ? */
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if (gma_crtc->pipe == 1 &&
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gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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REG_WRITE(DSPFW5, 0x00040330);
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} else {
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fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
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