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clk: tegra: Add stubs needed for compile-testing
Add stubs needed for compile-testing of Tegra memory drivers. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -743,11 +743,6 @@ out:
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return err;
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}
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int __weak tegra210_clk_handle_mbist_war(unsigned int id)
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{
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return 0;
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}
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static int tegra_powergate_power_up(struct tegra_powergate *pg,
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bool disable_clocks)
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{
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@ -123,20 +123,6 @@ static inline void tegra_cpu_clock_resume(void)
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}
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#endif
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extern int tegra210_plle_hw_sequence_start(void);
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extern bool tegra210_plle_hw_sequence_is_enabled(void);
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extern void tegra210_xusb_pll_hw_control_enable(void);
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extern void tegra210_xusb_pll_hw_sequence_start(void);
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extern void tegra210_sata_pll_hw_control_enable(void);
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extern void tegra210_sata_pll_hw_sequence_start(void);
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extern void tegra210_set_sata_pll_seq_sw(bool state);
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extern void tegra210_put_utmipll_in_iddq(void);
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extern void tegra210_put_utmipll_out_iddq(void);
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extern int tegra210_clk_handle_mbist_war(unsigned int id);
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extern void tegra210_clk_emc_dll_enable(bool flag);
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extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
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extern void tegra210_clk_emc_update_setting(u32 emc_src_value);
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struct clk;
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struct tegra_emc;
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@ -144,17 +130,10 @@ typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
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unsigned long min_rate,
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unsigned long max_rate,
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void *arg);
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void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
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void *cb_arg);
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int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
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typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc,
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unsigned long rate);
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typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc,
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unsigned long rate);
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void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
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tegra124_emc_complete_timing_change_cb *complete_cb);
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struct tegra210_clk_emc_config {
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unsigned long rate;
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@ -176,8 +155,87 @@ struct tegra210_clk_emc_provider {
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const struct tegra210_clk_emc_config *config);
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};
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#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
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void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
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void *cb_arg);
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int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
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#else
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static inline void
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tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
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void *cb_arg)
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{
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}
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static inline int
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tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_TEGRA124_CLK_EMC
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void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
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tegra124_emc_complete_timing_change_cb *complete_cb);
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#else
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static inline void
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tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
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tegra124_emc_complete_timing_change_cb *complete_cb)
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{
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}
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#endif
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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int tegra210_plle_hw_sequence_start(void);
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bool tegra210_plle_hw_sequence_is_enabled(void);
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void tegra210_xusb_pll_hw_control_enable(void);
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void tegra210_xusb_pll_hw_sequence_start(void);
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void tegra210_sata_pll_hw_control_enable(void);
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void tegra210_sata_pll_hw_sequence_start(void);
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void tegra210_set_sata_pll_seq_sw(bool state);
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void tegra210_put_utmipll_in_iddq(void);
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void tegra210_put_utmipll_out_iddq(void);
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int tegra210_clk_handle_mbist_war(unsigned int id);
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void tegra210_clk_emc_dll_enable(bool flag);
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void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
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void tegra210_clk_emc_update_setting(u32 emc_src_value);
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int tegra210_clk_emc_attach(struct clk *clk,
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struct tegra210_clk_emc_provider *provider);
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void tegra210_clk_emc_detach(struct clk *clk);
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#else
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static inline int tegra210_plle_hw_sequence_start(void)
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{
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return 0;
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}
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static inline bool tegra210_plle_hw_sequence_is_enabled(void)
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{
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return false;
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}
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static inline int tegra210_clk_handle_mbist_war(unsigned int id)
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{
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return 0;
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}
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static inline int
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tegra210_clk_emc_attach(struct clk *clk,
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struct tegra210_clk_emc_provider *provider)
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{
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return 0;
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}
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static inline void tegra210_xusb_pll_hw_control_enable(void) {}
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static inline void tegra210_xusb_pll_hw_sequence_start(void) {}
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static inline void tegra210_sata_pll_hw_control_enable(void) {}
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static inline void tegra210_sata_pll_hw_sequence_start(void) {}
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static inline void tegra210_set_sata_pll_seq_sw(bool state) {}
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static inline void tegra210_put_utmipll_in_iddq(void) {}
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static inline void tegra210_put_utmipll_out_iddq(void) {}
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static inline void tegra210_clk_emc_dll_enable(bool flag) {}
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static inline void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) {}
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static inline void tegra210_clk_emc_update_setting(u32 emc_src_value) {}
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static inline void tegra210_clk_emc_detach(struct clk *clk) {}
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#endif
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#endif /* __LINUX_CLK_TEGRA_H_ */
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