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clk: st: Adds clockgen-vcc and clockgen-mux clock binding
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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36
Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
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36
Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
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Binding for a ST multiplexed clock driver.
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This binding supports only simple indexed multiplexers, it does not
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support table based parent index to hardware value translations.
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be:
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"st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
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"st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
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"st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
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"st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
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"st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
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"st,stih415-clkgen-a9-mux", "st,clkgen-mux"
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"st,stih416-clkgen-a9-mux", "st,clkgen-mux"
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- #clock-cells : from common clock binding; shall be set to 0.
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- reg : A Base address and length of the register set.
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- clocks : from common clock binding
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Example:
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CLK_M_HVA: CLK_M_HVA {
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#clock-cells = <0>;
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compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
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reg = <0xfd690868 4>;
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clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
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};
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53
Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
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53
Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
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Binding for a type of STMicroelectronics clock crossbar (VCC).
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The crossbar can take up to 4 input clocks and control up to 16
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output clocks. Not all inputs or outputs have to be in use in a
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particular instantiation. Each output can be individually enabled,
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select any of the input clocks and apply a divide (by 1,2,4 or 8) to
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that selected clock.
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be:
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"st,stih416-clkgenc", "st,vcc"
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"st,stih416-clkgenf", "st,vcc"
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- #clock-cells : from common clock binding; shall be set to 1.
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- reg : A Base address and length of the register set.
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- clocks : from common clock binding
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- clock-output-names : From common clock binding. The block has 16
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clock outputs but not all of them in a specific instance
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have to be used in the SoC. If a clock name is left as
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an empty string then no clock will be created for the
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output associated with that string index. If fewer than
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16 strings are provided then no clocks will be created
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for the remaining outputs.
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Example:
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CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
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#clock-cells = <1>;
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compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
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reg = <0xfe8308ac 12>;
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clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
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<&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
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clock-output-names =
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"CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
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"CLK_S_OUT_DVO", "CLK_S_PIX_HD",
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"CLK_S_HDDAC", "CLK_S_DENC",
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"CLK_S_SDDAC", "CLK_S_PIX_MAIN",
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"CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
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"CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
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"CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
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"CLK_S_THSENS";
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};
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