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platform/x86: ISST: Add Intel Speed Select PUNIT MSR interface
While using new non arhitectural features using PUNIT Mailbox and MMIO read/write interface, still there is need to operate using MSRs to control PUNIT. User space could have used user user-space MSR interface for this, but when user space MSR access is disabled, then it can't. Here only limited number of MSRs are allowed using this new interface. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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@ -25,6 +25,11 @@
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static struct isst_if_cmd_cb punit_callbacks[ISST_IF_DEV_MAX];
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static int punit_msr_white_list[] = {
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MSR_TURBO_RATIO_LIMIT,
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MSR_CONFIG_TDP_CONTROL,
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};
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struct isst_valid_cmd_ranges {
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u16 cmd;
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u16 sub_cmd_beg;
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@ -229,6 +234,54 @@ static long isst_if_proc_phyid_req(u8 *cmd_ptr, int *write_only, int resume)
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return 0;
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}
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static bool match_punit_msr_white_list(int msr)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(punit_msr_white_list); ++i) {
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if (punit_msr_white_list[i] == msr)
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return true;
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}
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return false;
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}
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static long isst_if_msr_cmd_req(u8 *cmd_ptr, int *write_only, int resume)
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{
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struct isst_if_msr_cmd *msr_cmd;
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int ret;
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msr_cmd = (struct isst_if_msr_cmd *)cmd_ptr;
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if (!match_punit_msr_white_list(msr_cmd->msr))
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return -EINVAL;
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if (msr_cmd->logical_cpu >= nr_cpu_ids)
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return -EINVAL;
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if (msr_cmd->read_write) {
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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ret = wrmsrl_safe_on_cpu(msr_cmd->logical_cpu,
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msr_cmd->msr,
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msr_cmd->data);
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*write_only = 1;
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} else {
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u64 data;
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ret = rdmsrl_safe_on_cpu(msr_cmd->logical_cpu,
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msr_cmd->msr, &data);
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if (!ret) {
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msr_cmd->data = data;
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*write_only = 0;
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}
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}
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return ret;
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}
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static long isst_if_exec_multi_cmd(void __user *argp, struct isst_if_cmd_cb *cb)
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{
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unsigned char __user *ptr;
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@ -309,6 +362,12 @@ static long isst_if_def_ioctl(struct file *file, unsigned int cmd,
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if (cb->registered)
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ret = isst_if_exec_multi_cmd(argp, cb);
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break;
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case ISST_IF_MSR_COMMAND:
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cmd_cb.cmd_size = sizeof(struct isst_if_msr_cmd);
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cmd_cb.offset = offsetof(struct isst_if_msr_cmds, msr_cmd);
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cmd_cb.cmd_callback = isst_if_msr_cmd_req;
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ret = isst_if_exec_multi_cmd(argp, &cmd_cb);
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break;
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default:
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break;
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}
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@ -132,9 +132,41 @@ struct isst_if_mbox_cmds {
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struct isst_if_mbox_cmd mbox_cmd[1];
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};
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/**
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* struct isst_if_msr_cmd - Structure to define msr command
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* @read_write: Value 0: Read, 1: Write
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* @logical_cpu: Logical CPU number
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* @msr: MSR number
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* @data: For write operation, data to write, for read
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* place holder
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*
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* Structure to specify MSR command related to PUNIT.
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*/
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struct isst_if_msr_cmd {
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__u32 read_write; /* Read:0, Write:1 */
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__u32 logical_cpu;
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__u64 msr;
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__u64 data;
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};
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/**
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* struct isst_if_msr_cmds - structure for msr commands
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* @cmd_count: Number of mailbox commands in msr_cmd[]
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* @msr_cmd[]: Holds one or more msr commands
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*
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* This structure used with ioctl ISST_IF_MSR_COMMAND to send
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* one or more MSR commands. IOCTL return value indicates number of
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* commands sent or error number if no commands have been sent.
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*/
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struct isst_if_msr_cmds {
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__u32 cmd_count;
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struct isst_if_msr_cmd msr_cmd[1];
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};
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#define ISST_IF_MAGIC 0xFE
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#define ISST_IF_GET_PLATFORM_INFO _IOR(ISST_IF_MAGIC, 0, struct isst_if_platform_info *)
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#define ISST_IF_GET_PHY_ID _IOWR(ISST_IF_MAGIC, 1, struct isst_if_cpu_map *)
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#define ISST_IF_IO_CMD _IOW(ISST_IF_MAGIC, 2, struct isst_if_io_regs *)
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#define ISST_IF_MBOX_COMMAND _IOWR(ISST_IF_MAGIC, 3, struct isst_if_mbox_cmds *)
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#define ISST_IF_MSR_COMMAND _IOWR(ISST_IF_MAGIC, 4, struct isst_if_msr_cmds *)
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#endif
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