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drm/amdkfd: Clean up reference of radeon
Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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@ -20,8 +20,8 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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*/
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#ifndef HSA_RADEON_CIK_INT_H_INCLUDED
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#ifndef CIK_INT_H_INCLUDED
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#define HSA_RADEON_CIK_INT_H_INCLUDED
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#define CIK_INT_H_INCLUDED
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#include <linux/types.h>
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#include <linux/types.h>
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@ -34,7 +34,6 @@ struct cik_ih_ring_entry {
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#define CIK_INTSRC_CP_END_OF_PIPE 0xB5
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#define CIK_INTSRC_CP_END_OF_PIPE 0xB5
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#define CIK_INTSRC_CP_BAD_OPCODE 0xB7
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#define CIK_INTSRC_CP_BAD_OPCODE 0xB7
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#define CIK_INTSRC_DEQUEUE_COMPLETE 0xC6
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#define CIK_INTSRC_SDMA_TRAP 0xE0
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#define CIK_INTSRC_SDMA_TRAP 0xE0
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#define CIK_INTSRC_SQ_INTERRUPT_MSG 0xEF
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#define CIK_INTSRC_SQ_INTERRUPT_MSG 0xEF
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#define CIK_INTSRC_GFX_PAGE_INV_FAULT 0x92
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#define CIK_INTSRC_GFX_PAGE_INV_FAULT 0x92
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@ -38,7 +38,6 @@
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#include "kfd_dbgmgr.h"
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#include "kfd_dbgmgr.h"
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#include "kfd_dbgdev.h"
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#include "kfd_dbgdev.h"
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#include "kfd_device_queue_manager.h"
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#include "kfd_device_queue_manager.h"
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#include "../../radeon/cik_reg.h"
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static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev)
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static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev)
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{
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{
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@ -60,6 +60,9 @@ enum {
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SH_REG_SIZE = SH_REG_END - SH_REG_BASE
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SH_REG_SIZE = SH_REG_END - SH_REG_BASE
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};
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};
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/* SQ_CMD definitions */
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#define SQ_CMD 0x8DEC
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enum SQ_IND_CMD_CMD {
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enum SQ_IND_CMD_CMD {
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SQ_IND_CMD_CMD_NULL = 0x00000000,
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SQ_IND_CMD_CMD_NULL = 0x00000000,
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SQ_IND_CMD_CMD_HALT = 0x00000001,
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SQ_IND_CMD_CMD_HALT = 0x00000001,
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@ -190,4 +193,38 @@ union ULARGE_INTEGER {
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void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
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void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
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enum DBGDEV_TYPE type);
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enum DBGDEV_TYPE type);
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union TCP_WATCH_CNTL_BITS {
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struct {
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uint32_t mask:24;
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uint32_t vmid:4;
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uint32_t atc:1;
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uint32_t mode:2;
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uint32_t valid:1;
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} bitfields, bits;
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uint32_t u32All;
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signed int i32All;
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float f32All;
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};
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enum {
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ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
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ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
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ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
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/* extend the mask to 26 bits in order to match the low address field */
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ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
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ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
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};
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enum {
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MAX_TRAPID = 8, /* 3 bits in the bitfield. */
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MAX_WATCH_ADDRESSES = 4
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};
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enum {
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ADDRESS_WATCH_REG_ADDR_HI = 0,
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ADDRESS_WATCH_REG_ADDR_LO,
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ADDRESS_WATCH_REG_CNTL,
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ADDRESS_WATCH_REG_MAX
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};
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#endif /* KFD_DBGDEV_H_ */
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#endif /* KFD_DBGDEV_H_ */
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@ -73,7 +73,7 @@
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/*
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/*
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* When working with cp scheduler we should assign the HIQ manually or via
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* When working with cp scheduler we should assign the HIQ manually or via
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* the radeon driver to a fixed hqd slot, here are the fixed HIQ hqd slot
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* the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot
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* definitions for Kaveri. In Kaveri only the first ME queues participates
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* definitions for Kaveri. In Kaveri only the first ME queues participates
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* in the cp scheduling taking that in mind we set the HIQ slot in the
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* in the cp scheduling taking that in mind we set the HIQ slot in the
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* second ME.
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* second ME.
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@ -209,7 +209,7 @@ int pqm_create_queue(struct process_queue_manager *pqm,
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KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
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KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
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((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) ||
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((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) ||
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(dev->dqm->queue_count >= get_queues_num(dev->dqm)))) {
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(dev->dqm->queue_count >= get_queues_num(dev->dqm)))) {
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pr_err("Over-subscription is not allowed in radeon_kfd.sched_policy == 1\n");
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pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n");
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retval = -EPERM;
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retval = -EPERM;
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goto err_create_queue;
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goto err_create_queue;
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}
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}
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