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arm64: dts: imx8mp-evk: correct eqos pad settings
According to RM bit layout, BIT3 and BIT0 are reserved.
8 7 6 5 4 3 2 1 0
PE HYS PUE ODE FSEL X DSE X
Although function is not broken, we should not set reserved bit.
Fixes: dc6d5dc89b
("arm64: dts: imx8mp-evk: enable EQOS ethernet")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
parent
e2c00820a9
commit
e6e1bc0ec9
@ -395,21 +395,21 @@
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
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MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
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MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
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>;
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};
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