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iommu/io-pgtable-arm: Add support to use system cache
Add a quirk IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to override the outer-cacheability attributes set in the TCR for a non-coherent page table walker when using system cache. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/f818676b4a2a9ad1edb92721947d47db41ed6a7c.1606287059.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Will Deacon <will@kernel.org>
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@ -761,7 +761,8 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
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if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
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IO_PGTABLE_QUIRK_NON_STRICT |
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IO_PGTABLE_QUIRK_ARM_TTBR1))
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IO_PGTABLE_QUIRK_ARM_TTBR1 |
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IO_PGTABLE_QUIRK_ARM_OUTER_WBWA))
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return NULL;
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data = arm_lpae_alloc_pgtable(cfg);
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@ -773,10 +774,15 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
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tcr->sh = ARM_LPAE_TCR_SH_IS;
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tcr->irgn = ARM_LPAE_TCR_RGN_WBWA;
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tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
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if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA)
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goto out_free_data;
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} else {
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tcr->sh = ARM_LPAE_TCR_SH_OS;
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tcr->irgn = ARM_LPAE_TCR_RGN_NC;
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tcr->orgn = ARM_LPAE_TCR_RGN_NC;
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if (!(cfg->quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA))
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tcr->orgn = ARM_LPAE_TCR_RGN_NC;
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else
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tcr->orgn = ARM_LPAE_TCR_RGN_WBWA;
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}
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tg1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1;
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@ -86,6 +86,9 @@ struct io_pgtable_cfg {
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*
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* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
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* for use in the upper half of a split address space.
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*
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* IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
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* attributes set in the TCR for a non-coherent page-table walker.
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*/
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#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
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#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
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@ -93,6 +96,7 @@ struct io_pgtable_cfg {
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#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
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#define IO_PGTABLE_QUIRK_NON_STRICT BIT(4)
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#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
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#define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
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unsigned long quirks;
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unsigned long pgsize_bitmap;
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unsigned int ias;
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