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drm/i915/guc: Connect UAPI to GuC multi-lrc interface
Introduce 'set parallel submit' extension to connect UAPI to GuC multi-lrc interface. Kernel doc in new uAPI should explain it all. IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1 media UMD: https://github.com/intel/media-driver/pull/1252 v2: (Daniel Vetter) - Add IGT link and placeholder for media UMD link v3: (Kernel test robot) - Fix warning in unpin engines call (John Harrison) - Reword a bunch of the kernel doc v4: (John Harrison) - Add comment why perma-pin is done after setting gem context - Update some comments / docs for proto contexts v5: (John Harrison) - Rework perma-pin comment - Add BUG_IN if context is pinned when setting gem context Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211014172005.27155-17-matthew.brost@intel.com
This commit is contained in:
Matthew Brost
John Harrison
parent
d38a929449
commit
e5e32171a2
@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension __user *base, void *data)
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return 0;
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}
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static int
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set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
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void *data)
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{
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struct i915_context_engines_parallel_submit __user *ext =
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container_of_user(base, typeof(*ext), base);
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const struct set_proto_ctx_engines *set = data;
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struct drm_i915_private *i915 = set->i915;
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u64 flags;
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int err = 0, n, i, j;
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u16 slot, width, num_siblings;
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struct intel_engine_cs **siblings = NULL;
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intel_engine_mask_t prev_mask;
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/* Disabling for now */
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return -ENODEV;
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/* FIXME: This is NIY for execlists */
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if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
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return -ENODEV;
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if (get_user(slot, &ext->engine_index))
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return -EFAULT;
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if (get_user(width, &ext->width))
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return -EFAULT;
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if (get_user(num_siblings, &ext->num_siblings))
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return -EFAULT;
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if (slot >= set->num_engines) {
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drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
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slot, set->num_engines);
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return -EINVAL;
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}
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if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
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drm_dbg(&i915->drm,
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"Invalid placement[%d], already occupied\n", slot);
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return -EINVAL;
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}
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if (get_user(flags, &ext->flags))
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return -EFAULT;
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if (flags) {
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drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
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return -EINVAL;
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}
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for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
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err = check_user_mbz(&ext->mbz64[n]);
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if (err)
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return err;
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}
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if (width < 2) {
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drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
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return -EINVAL;
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}
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if (num_siblings < 1) {
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drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
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num_siblings);
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return -EINVAL;
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}
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siblings = kmalloc_array(num_siblings * width,
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sizeof(*siblings),
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GFP_KERNEL);
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if (!siblings)
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return -ENOMEM;
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/* Create contexts / engines */
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for (i = 0; i < width; ++i) {
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intel_engine_mask_t current_mask = 0;
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struct i915_engine_class_instance prev_engine;
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for (j = 0; j < num_siblings; ++j) {
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struct i915_engine_class_instance ci;
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n = i * num_siblings + j;
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if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
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err = -EFAULT;
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goto out_err;
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}
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siblings[n] =
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intel_engine_lookup_user(i915, ci.engine_class,
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ci.engine_instance);
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if (!siblings[n]) {
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drm_dbg(&i915->drm,
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"Invalid sibling[%d]: { class:%d, inst:%d }\n",
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n, ci.engine_class, ci.engine_instance);
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err = -EINVAL;
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goto out_err;
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}
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if (n) {
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if (prev_engine.engine_class !=
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ci.engine_class) {
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drm_dbg(&i915->drm,
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"Mismatched class %d, %d\n",
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prev_engine.engine_class,
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ci.engine_class);
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err = -EINVAL;
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goto out_err;
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}
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}
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prev_engine = ci;
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current_mask |= siblings[n]->logical_mask;
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}
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if (i > 0) {
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if (current_mask != prev_mask << 1) {
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drm_dbg(&i915->drm,
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"Non contiguous logical mask 0x%x, 0x%x\n",
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prev_mask, current_mask);
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err = -EINVAL;
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goto out_err;
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}
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}
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prev_mask = current_mask;
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}
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set->engines[slot].type = I915_GEM_ENGINE_TYPE_PARALLEL;
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set->engines[slot].num_siblings = num_siblings;
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set->engines[slot].width = width;
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set->engines[slot].siblings = siblings;
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return 0;
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out_err:
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kfree(siblings);
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return err;
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}
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static const i915_user_extension_fn set_proto_ctx_engines_extensions[] = {
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[I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_proto_ctx_engines_balance,
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[I915_CONTEXT_ENGINES_EXT_BOND] = set_proto_ctx_engines_bond,
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[I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT] =
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set_proto_ctx_engines_parallel_submit,
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};
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static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
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@ -794,6 +935,7 @@ static int intel_context_set_gem(struct intel_context *ce,
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GEM_BUG_ON(rcu_access_pointer(ce->gem_context));
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RCU_INIT_POINTER(ce->gem_context, ctx);
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GEM_BUG_ON(intel_context_is_pinned(ce));
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ce->ring_size = SZ_16K;
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i915_vm_put(ce->vm);
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@ -818,6 +960,25 @@ static int intel_context_set_gem(struct intel_context *ce,
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return ret;
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}
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static void __unpin_engines(struct i915_gem_engines *e, unsigned int count)
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{
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while (count--) {
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struct intel_context *ce = e->engines[count], *child;
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if (!ce || !test_bit(CONTEXT_PERMA_PIN, &ce->flags))
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continue;
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for_each_child(ce, child)
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intel_context_unpin(child);
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intel_context_unpin(ce);
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}
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}
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static void unpin_engines(struct i915_gem_engines *e)
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{
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__unpin_engines(e, e->num_engines);
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}
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static void __free_engines(struct i915_gem_engines *e, unsigned int count)
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{
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while (count--) {
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@ -933,6 +1094,40 @@ free_engines:
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return err;
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}
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static int perma_pin_contexts(struct intel_context *ce)
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{
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struct intel_context *child;
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int i = 0, j = 0, ret;
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GEM_BUG_ON(!intel_context_is_parent(ce));
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ret = intel_context_pin(ce);
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if (unlikely(ret))
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return ret;
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for_each_child(ce, child) {
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ret = intel_context_pin(child);
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if (unlikely(ret))
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goto unwind;
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++i;
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}
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set_bit(CONTEXT_PERMA_PIN, &ce->flags);
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return 0;
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unwind:
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intel_context_unpin(ce);
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for_each_child(ce, child) {
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if (j++ < i)
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intel_context_unpin(child);
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else
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break;
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}
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return ret;
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}
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static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
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unsigned int num_engines,
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struct i915_gem_proto_engine *pe)
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@ -946,7 +1141,7 @@ static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
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e->num_engines = num_engines;
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for (n = 0; n < num_engines; n++) {
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struct intel_context *ce;
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struct intel_context *ce, *child;
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int ret;
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switch (pe[n].type) {
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@ -956,7 +1151,13 @@ static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
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case I915_GEM_ENGINE_TYPE_BALANCED:
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ce = intel_engine_create_virtual(pe[n].siblings,
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pe[n].num_siblings);
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pe[n].num_siblings, 0);
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break;
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case I915_GEM_ENGINE_TYPE_PARALLEL:
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ce = intel_engine_create_parallel(pe[n].siblings,
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pe[n].num_siblings,
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pe[n].width);
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break;
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case I915_GEM_ENGINE_TYPE_INVALID:
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@ -977,6 +1178,30 @@ static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
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err = ERR_PTR(ret);
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goto free_engines;
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}
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for_each_child(ce, child) {
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ret = intel_context_set_gem(child, ctx, pe->sseu);
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if (ret) {
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err = ERR_PTR(ret);
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goto free_engines;
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}
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}
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/*
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* XXX: Must be done after calling intel_context_set_gem as that
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* function changes the ring size. The ring is allocated when
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* the context is pinned. If the ring size is changed after
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* allocation we have a mismatch of the ring size and will cause
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* the context to hang. Presumably with a bit of reordering we
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* could move the perma-pin step to the backend function
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* intel_engine_create_parallel.
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*/
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if (pe[n].type == I915_GEM_ENGINE_TYPE_PARALLEL) {
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ret = perma_pin_contexts(ce);
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if (ret) {
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err = ERR_PTR(ret);
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goto free_engines;
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}
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}
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}
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return e;
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@ -1219,6 +1444,7 @@ static void context_close(struct i915_gem_context *ctx)
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/* Flush any concurrent set_engines() */
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mutex_lock(&ctx->engines_mutex);
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unpin_engines(__context_engines_static(ctx));
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engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
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i915_gem_context_set_closed(ctx);
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mutex_unlock(&ctx->engines_mutex);
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@ -78,13 +78,16 @@ enum i915_gem_engine_type {
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/** @I915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set */
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I915_GEM_ENGINE_TYPE_BALANCED,
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/** @I915_GEM_ENGINE_TYPE_PARALLEL: A parallel engine set */
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I915_GEM_ENGINE_TYPE_PARALLEL,
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};
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/**
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* struct i915_gem_proto_engine - prototype engine
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*
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* This struct describes an engine that a context may contain. Engines
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* have three types:
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* have four types:
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*
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* - I915_GEM_ENGINE_TYPE_INVALID: Invalid engines can be created but they
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* show up as a NULL in i915_gem_engines::engines[i] and any attempt to
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@ -97,6 +100,10 @@ enum i915_gem_engine_type {
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*
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* - I915_GEM_ENGINE_TYPE_BALANCED: A load-balanced engine set, described
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* i915_gem_proto_engine::num_siblings and i915_gem_proto_engine::siblings.
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*
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* - I915_GEM_ENGINE_TYPE_PARALLEL: A parallel submission engine set, described
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* i915_gem_proto_engine::width, i915_gem_proto_engine::num_siblings, and
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* i915_gem_proto_engine::siblings.
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*/
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struct i915_gem_proto_engine {
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/** @type: Type of this engine */
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@ -105,10 +112,13 @@ struct i915_gem_proto_engine {
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/** @engine: Engine, for physical */
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struct intel_engine_cs *engine;
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/** @num_siblings: Number of balanced siblings */
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/** @num_siblings: Number of balanced or parallel siblings */
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unsigned int num_siblings;
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/** @siblings: Balanced siblings */
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/** @width: Width of each sibling */
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unsigned int width;
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/** @siblings: Balanced siblings or num_siblings * width for parallel */
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struct intel_engine_cs **siblings;
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/** @sseu: Client-set SSEU parameters */
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@ -55,9 +55,13 @@ struct intel_context_ops {
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void (*reset)(struct intel_context *ce);
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void (*destroy)(struct kref *kref);
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/* virtual engine/context interface */
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/* virtual/parallel engine/context interface */
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struct intel_context *(*create_virtual)(struct intel_engine_cs **engine,
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unsigned int count);
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unsigned int count,
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unsigned long flags);
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struct intel_context *(*create_parallel)(struct intel_engine_cs **engines,
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unsigned int num_siblings,
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unsigned int width);
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struct intel_engine_cs *(*get_sibling)(struct intel_engine_cs *engine,
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unsigned int sibling);
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};
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@ -113,6 +117,7 @@ struct intel_context {
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#define CONTEXT_NOPREEMPT 8
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#define CONTEXT_LRCA_DIRTY 9
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#define CONTEXT_GUC_INIT 10
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#define CONTEXT_PERMA_PIN 11
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struct {
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u64 timeout_us;
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@ -282,9 +282,19 @@ intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
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return intel_engine_has_preemption(engine);
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}
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#define FORCE_VIRTUAL BIT(0)
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struct intel_context *
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intel_engine_create_virtual(struct intel_engine_cs **siblings,
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unsigned int count);
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unsigned int count, unsigned long flags);
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static inline struct intel_context *
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intel_engine_create_parallel(struct intel_engine_cs **engines,
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unsigned int num_engines,
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unsigned int width)
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{
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GEM_BUG_ON(!engines[0]->cops->create_parallel);
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return engines[0]->cops->create_parallel(engines, num_engines, width);
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}
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static inline bool
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intel_virtual_engine_has_heartbeat(const struct intel_engine_cs *engine)
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@ -1953,16 +1953,16 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
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struct intel_context *
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intel_engine_create_virtual(struct intel_engine_cs **siblings,
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unsigned int count)
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unsigned int count, unsigned long flags)
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{
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if (count == 0)
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return ERR_PTR(-EINVAL);
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if (count == 1)
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if (count == 1 && !(flags & FORCE_VIRTUAL))
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return intel_context_create(siblings[0]);
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GEM_BUG_ON(!siblings[0]->cops->create_virtual);
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return siblings[0]->cops->create_virtual(siblings, count);
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return siblings[0]->cops->create_virtual(siblings, count, flags);
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}
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struct i915_request *
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@ -201,7 +201,8 @@ static struct virtual_engine *to_virtual_engine(struct intel_engine_cs *engine)
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}
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static struct intel_context *
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execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count);
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execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
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unsigned long flags);
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static struct i915_request *
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__active_request(const struct intel_timeline * const tl,
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@ -3784,7 +3785,8 @@ unlock:
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}
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static struct intel_context *
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execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
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execlists_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
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unsigned long flags)
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{
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struct virtual_engine *ve;
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unsigned int n;
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@ -3733,7 +3733,7 @@ static int nop_virtual_engine(struct intel_gt *gt,
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GEM_BUG_ON(!nctx || nctx > ARRAY_SIZE(ve));
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for (n = 0; n < nctx; n++) {
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ve[n] = intel_engine_create_virtual(siblings, nsibling);
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ve[n] = intel_engine_create_virtual(siblings, nsibling, 0);
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if (IS_ERR(ve[n])) {
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err = PTR_ERR(ve[n]);
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nctx = n;
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@ -3929,7 +3929,7 @@ static int mask_virtual_engine(struct intel_gt *gt,
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* restrict it to our desired engine within the virtual engine.
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*/
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ve = intel_engine_create_virtual(siblings, nsibling);
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ve = intel_engine_create_virtual(siblings, nsibling, 0);
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if (IS_ERR(ve)) {
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err = PTR_ERR(ve);
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goto out_close;
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@ -4060,7 +4060,7 @@ static int slicein_virtual_engine(struct intel_gt *gt,
|
||||
i915_request_add(rq);
|
||||
}
|
||||
|
||||
ce = intel_engine_create_virtual(siblings, nsibling);
|
||||
ce = intel_engine_create_virtual(siblings, nsibling, 0);
|
||||
if (IS_ERR(ce)) {
|
||||
err = PTR_ERR(ce);
|
||||
goto out;
|
||||
@ -4112,7 +4112,7 @@ static int sliceout_virtual_engine(struct intel_gt *gt,
|
||||
|
||||
/* XXX We do not handle oversubscription and fairness with normal rq */
|
||||
for (n = 0; n < nsibling; n++) {
|
||||
ce = intel_engine_create_virtual(siblings, nsibling);
|
||||
ce = intel_engine_create_virtual(siblings, nsibling, 0);
|
||||
if (IS_ERR(ce)) {
|
||||
err = PTR_ERR(ce);
|
||||
goto out;
|
||||
@ -4214,7 +4214,7 @@ static int preserved_virtual_engine(struct intel_gt *gt,
|
||||
if (err)
|
||||
goto out_scratch;
|
||||
|
||||
ve = intel_engine_create_virtual(siblings, nsibling);
|
||||
ve = intel_engine_create_virtual(siblings, nsibling, 0);
|
||||
if (IS_ERR(ve)) {
|
||||
err = PTR_ERR(ve);
|
||||
goto out_scratch;
|
||||
@ -4354,7 +4354,7 @@ static int reset_virtual_engine(struct intel_gt *gt,
|
||||
if (igt_spinner_init(&spin, gt))
|
||||
return -ENOMEM;
|
||||
|
||||
ve = intel_engine_create_virtual(siblings, nsibling);
|
||||
ve = intel_engine_create_virtual(siblings, nsibling, 0);
|
||||
if (IS_ERR(ve)) {
|
||||
err = PTR_ERR(ve);
|
||||
goto out_spin;
|
||||
|
||||
@ -124,7 +124,13 @@ struct guc_virtual_engine {
|
||||
};
|
||||
|
||||
static struct intel_context *
|
||||
guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count);
|
||||
guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
|
||||
unsigned long flags);
|
||||
|
||||
static struct intel_context *
|
||||
guc_create_parallel(struct intel_engine_cs **engines,
|
||||
unsigned int num_siblings,
|
||||
unsigned int width);
|
||||
|
||||
#define GUC_REQUEST_SIZE 64 /* bytes */
|
||||
|
||||
@ -2609,6 +2615,7 @@ static const struct intel_context_ops guc_context_ops = {
|
||||
.destroy = guc_context_destroy,
|
||||
|
||||
.create_virtual = guc_create_virtual,
|
||||
.create_parallel = guc_create_parallel,
|
||||
};
|
||||
|
||||
static void submit_work_cb(struct irq_work *wrk)
|
||||
@ -2858,8 +2865,6 @@ static const struct intel_context_ops virtual_guc_context_ops = {
|
||||
.get_sibling = guc_virtual_get_sibling,
|
||||
};
|
||||
|
||||
/* Future patches will use this function */
|
||||
__maybe_unused
|
||||
static int guc_parent_context_pin(struct intel_context *ce, void *vaddr)
|
||||
{
|
||||
struct intel_engine_cs *engine = guc_virtual_get_sibling(ce->engine, 0);
|
||||
@ -2876,8 +2881,6 @@ static int guc_parent_context_pin(struct intel_context *ce, void *vaddr)
|
||||
return __guc_context_pin(ce, engine, vaddr);
|
||||
}
|
||||
|
||||
/* Future patches will use this function */
|
||||
__maybe_unused
|
||||
static int guc_child_context_pin(struct intel_context *ce, void *vaddr)
|
||||
{
|
||||
struct intel_engine_cs *engine = guc_virtual_get_sibling(ce->engine, 0);
|
||||
@ -2889,8 +2892,6 @@ static int guc_child_context_pin(struct intel_context *ce, void *vaddr)
|
||||
return __guc_context_pin(ce, engine, vaddr);
|
||||
}
|
||||
|
||||
/* Future patches will use this function */
|
||||
__maybe_unused
|
||||
static void guc_parent_context_unpin(struct intel_context *ce)
|
||||
{
|
||||
struct intel_guc *guc = ce_to_guc(ce);
|
||||
@ -2906,8 +2907,6 @@ static void guc_parent_context_unpin(struct intel_context *ce)
|
||||
lrc_unpin(ce);
|
||||
}
|
||||
|
||||
/* Future patches will use this function */
|
||||
__maybe_unused
|
||||
static void guc_child_context_unpin(struct intel_context *ce)
|
||||
{
|
||||
GEM_BUG_ON(context_enabled(ce));
|
||||
@ -2918,8 +2917,6 @@ static void guc_child_context_unpin(struct intel_context *ce)
|
||||
lrc_unpin(ce);
|
||||
}
|
||||
|
||||
/* Future patches will use this function */
|
||||
__maybe_unused
|
||||
static void guc_child_context_post_unpin(struct intel_context *ce)
|
||||
{
|
||||
GEM_BUG_ON(!intel_context_is_child(ce));
|
||||
@ -2930,6 +2927,98 @@ static void guc_child_context_post_unpin(struct intel_context *ce)
|
||||
intel_context_unpin(ce->parallel.parent);
|
||||
}
|
||||
|
||||
static void guc_child_context_destroy(struct kref *kref)
|
||||
{
|
||||
struct intel_context *ce = container_of(kref, typeof(*ce), ref);
|
||||
|
||||
__guc_context_destroy(ce);
|
||||
}
|
||||
|
||||
static const struct intel_context_ops virtual_parent_context_ops = {
|
||||
.alloc = guc_virtual_context_alloc,
|
||||
|
||||
.pre_pin = guc_context_pre_pin,
|
||||
.pin = guc_parent_context_pin,
|
||||
.unpin = guc_parent_context_unpin,
|
||||
.post_unpin = guc_context_post_unpin,
|
||||
|
||||
.ban = guc_context_ban,
|
||||
|
||||
.cancel_request = guc_context_cancel_request,
|
||||
|
||||
.enter = guc_virtual_context_enter,
|
||||
.exit = guc_virtual_context_exit,
|
||||
|
||||
.sched_disable = guc_context_sched_disable,
|
||||
|
||||
.destroy = guc_context_destroy,
|
||||
|
||||
.get_sibling = guc_virtual_get_sibling,
|
||||
};
|
||||
|
||||
static const struct intel_context_ops virtual_child_context_ops = {
|
||||
.alloc = guc_virtual_context_alloc,
|
||||
|
||||
.pre_pin = guc_context_pre_pin,
|
||||
.pin = guc_child_context_pin,
|
||||
.unpin = guc_child_context_unpin,
|
||||
.post_unpin = guc_child_context_post_unpin,
|
||||
|
||||
.cancel_request = guc_context_cancel_request,
|
||||
|
||||
.enter = guc_virtual_context_enter,
|
||||
.exit = guc_virtual_context_exit,
|
||||
|
||||
.destroy = guc_child_context_destroy,
|
||||
|
||||
.get_sibling = guc_virtual_get_sibling,
|
||||
};
|
||||
|
||||
static struct intel_context *
|
||||
guc_create_parallel(struct intel_engine_cs **engines,
|
||||
unsigned int num_siblings,
|
||||
unsigned int width)
|
||||
{
|
||||
struct intel_engine_cs **siblings = NULL;
|
||||
struct intel_context *parent = NULL, *ce, *err;
|
||||
int i, j;
|
||||
|
||||
siblings = kmalloc_array(num_siblings,
|
||||
sizeof(*siblings),
|
||||
GFP_KERNEL);
|
||||
if (!siblings)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
for (i = 0; i < width; ++i) {
|
||||
for (j = 0; j < num_siblings; ++j)
|
||||
siblings[j] = engines[i * num_siblings + j];
|
||||
|
||||
ce = intel_engine_create_virtual(siblings, num_siblings,
|
||||
FORCE_VIRTUAL);
|
||||
if (!ce) {
|
||||
err = ERR_PTR(-ENOMEM);
|
||||
goto unwind;
|
||||
}
|
||||
|
||||
if (i == 0) {
|
||||
parent = ce;
|
||||
parent->ops = &virtual_parent_context_ops;
|
||||
} else {
|
||||
ce->ops = &virtual_child_context_ops;
|
||||
intel_context_bind_parent_child(parent, ce);
|
||||
}
|
||||
}
|
||||
|
||||
kfree(siblings);
|
||||
return parent;
|
||||
|
||||
unwind:
|
||||
if (parent)
|
||||
intel_context_put(parent);
|
||||
kfree(siblings);
|
||||
return err;
|
||||
}
|
||||
|
||||
static bool
|
||||
guc_irq_enable_breadcrumbs(struct intel_breadcrumbs *b)
|
||||
{
|
||||
@ -3756,7 +3845,8 @@ void intel_guc_submission_print_context_info(struct intel_guc *guc,
|
||||
}
|
||||
|
||||
static struct intel_context *
|
||||
guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count)
|
||||
guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct guc_virtual_engine *ve;
|
||||
struct intel_guc *guc;
|
||||
|
||||
@ -1824,6 +1824,7 @@ struct drm_i915_gem_context_param {
|
||||
* Extensions:
|
||||
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
|
||||
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
|
||||
* i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_ENGINES 0xa
|
||||
|
||||
@ -2098,6 +2099,135 @@ struct i915_context_engines_bond {
|
||||
struct i915_engine_class_instance engines[N__]; \
|
||||
} __attribute__((packed)) name__
|
||||
|
||||
/**
|
||||
* struct i915_context_engines_parallel_submit - Configure engine for
|
||||
* parallel submission.
|
||||
*
|
||||
* Setup a slot in the context engine map to allow multiple BBs to be submitted
|
||||
* in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU
|
||||
* in parallel. Multiple hardware contexts are created internally in the i915 to
|
||||
* run these BBs. Once a slot is configured for N BBs only N BBs can be
|
||||
* submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
|
||||
* doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
|
||||
* many BBs there are based on the slot's configuration. The N BBs are the last
|
||||
* N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
|
||||
*
|
||||
* The default placement behavior is to create implicit bonds between each
|
||||
* context if each context maps to more than 1 physical engine (e.g. context is
|
||||
* a virtual engine). Also we only allow contexts of same engine class and these
|
||||
* contexts must be in logically contiguous order. Examples of the placement
|
||||
* behavior are described below. Lastly, the default is to not allow BBs to be
|
||||
* preempted mid-batch. Rather insert coordinated preemption points on all
|
||||
* hardware contexts between each set of BBs. Flags could be added in the future
|
||||
* to change both of these default behaviors.
|
||||
*
|
||||
* Returns -EINVAL if hardware context placement configuration is invalid or if
|
||||
* the placement configuration isn't supported on the platform / submission
|
||||
* interface.
|
||||
* Returns -ENODEV if extension isn't supported on the platform / submission
|
||||
* interface.
|
||||
*
|
||||
* .. code-block:: none
|
||||
*
|
||||
* Examples syntax:
|
||||
* CS[X] = generic engine of same class, logical instance X
|
||||
* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
|
||||
*
|
||||
* Example 1 pseudo code:
|
||||
* set_engines(INVALID)
|
||||
* set_parallel(engine_index=0, width=2, num_siblings=1,
|
||||
* engines=CS[0],CS[1])
|
||||
*
|
||||
* Results in the following valid placement:
|
||||
* CS[0], CS[1]
|
||||
*
|
||||
* Example 2 pseudo code:
|
||||
* set_engines(INVALID)
|
||||
* set_parallel(engine_index=0, width=2, num_siblings=2,
|
||||
* engines=CS[0],CS[2],CS[1],CS[3])
|
||||
*
|
||||
* Results in the following valid placements:
|
||||
* CS[0], CS[1]
|
||||
* CS[2], CS[3]
|
||||
*
|
||||
* This can be thought of as two virtual engines, each containing two
|
||||
* engines thereby making a 2D array. However, there are bonds tying the
|
||||
* entries together and placing restrictions on how they can be scheduled.
|
||||
* Specifically, the scheduler can choose only vertical columns from the 2D
|
||||
* array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the
|
||||
* scheduler wants to submit to CS[0], it must also choose CS[1] and vice
|
||||
* versa. Same for CS[2] requires also using CS[3].
|
||||
* VE[0] = CS[0], CS[2]
|
||||
* VE[1] = CS[1], CS[3]
|
||||
*
|
||||
* Example 3 pseudo code:
|
||||
* set_engines(INVALID)
|
||||
* set_parallel(engine_index=0, width=2, num_siblings=2,
|
||||
* engines=CS[0],CS[1],CS[1],CS[3])
|
||||
*
|
||||
* Results in the following valid and invalid placements:
|
||||
* CS[0], CS[1]
|
||||
* CS[1], CS[3] - Not logically contiguous, return -EINVAL
|
||||
*/
|
||||
struct i915_context_engines_parallel_submit {
|
||||
/**
|
||||
* @base: base user extension.
|
||||
*/
|
||||
struct i915_user_extension base;
|
||||
|
||||
/**
|
||||
* @engine_index: slot for parallel engine
|
||||
*/
|
||||
__u16 engine_index;
|
||||
|
||||
/**
|
||||
* @width: number of contexts per parallel engine or in other words the
|
||||
* number of batches in each submission
|
||||
*/
|
||||
__u16 width;
|
||||
|
||||
/**
|
||||
* @num_siblings: number of siblings per context or in other words the
|
||||
* number of possible placements for each submission
|
||||
*/
|
||||
__u16 num_siblings;
|
||||
|
||||
/**
|
||||
* @mbz16: reserved for future use; must be zero
|
||||
*/
|
||||
__u16 mbz16;
|
||||
|
||||
/**
|
||||
* @flags: all undefined flags must be zero, currently not defined flags
|
||||
*/
|
||||
__u64 flags;
|
||||
|
||||
/**
|
||||
* @mbz64: reserved for future use; must be zero
|
||||
*/
|
||||
__u64 mbz64[3];
|
||||
|
||||
/**
|
||||
* @engines: 2-d array of engine instances to configure parallel engine
|
||||
*
|
||||
* length = width (i) * num_siblings (j)
|
||||
* index = j + i * num_siblings
|
||||
*/
|
||||
struct i915_engine_class_instance engines[0];
|
||||
|
||||
} __packed;
|
||||
|
||||
#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
|
||||
struct i915_user_extension base; \
|
||||
__u16 engine_index; \
|
||||
__u16 width; \
|
||||
__u16 num_siblings; \
|
||||
__u16 mbz16; \
|
||||
__u64 flags; \
|
||||
__u64 mbz64[3]; \
|
||||
struct i915_engine_class_instance engines[N__]; \
|
||||
} __attribute__((packed)) name__
|
||||
|
||||
/**
|
||||
* DOC: Context Engine Map uAPI
|
||||
*
|
||||
@ -2157,6 +2287,7 @@ struct i915_context_param_engines {
|
||||
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
|
||||
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
|
||||
#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
|
||||
#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
|
||||
struct i915_engine_class_instance engines[0];
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user