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genirq/msi, treewide: Use a named struct for PCI/MSI attributes
The unnamed struct sucks and is in the way of further cleanups. Stick the PCI related MSI data into a real data structure and cleanup all users. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20211206210224.374863119@linutronix.de
This commit is contained in:
Thomas Gleixner
parent
bec61847cd
commit
e58f2259b9
@ -212,7 +212,7 @@ static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
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entry = first_pci_msi_entry(dev);
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for (; dn; dn = of_get_next_parent(dn)) {
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if (entry->msi_attrib.is_64) {
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if (entry->pci.msi_attrib.is_64) {
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prop = of_get_property(dn, "msi-address-64", &len);
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if (prop)
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break;
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@ -2154,10 +2154,10 @@ static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg)
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int rc;
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rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq,
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entry->msi_attrib.is_64, msg);
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entry->pci.msi_attrib.is_64, msg);
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if (rc)
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dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n",
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entry->msi_attrib.is_64 ? "64" : "32", d->hwirq, rc);
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entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc);
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}
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/*
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@ -332,7 +332,7 @@ static int check_msix_entries(struct pci_dev *pdev)
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expected = 0;
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for_each_pci_msi_entry(entry, pdev) {
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if (entry->msi_attrib.entry_nr != expected) {
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if (entry->pci.msi_attrib.entry_nr != expected) {
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pr_debug("rtas_msi: bad MSI-X entries.\n");
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return -EINVAL;
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}
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@ -449,7 +449,7 @@ static int pseries_msi_ops_prepare(struct irq_domain *domain, struct device *dev
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct msi_desc *desc = first_pci_msi_entry(pdev);
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int type = desc->msi_attrib.is_msix ? PCI_CAP_ID_MSIX : PCI_CAP_ID_MSI;
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int type = desc->pci.msi_attrib.is_msix ? PCI_CAP_ID_MSIX : PCI_CAP_ID_MSI;
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return rtas_prepare_msi_irqs(pdev, nvec, type, arg);
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}
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@ -580,7 +580,7 @@ static int pseries_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
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int hwirq;
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int i, ret;
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hwirq = rtas_query_irq_number(pci_get_pdn(pdev), desc->msi_attrib.entry_nr);
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hwirq = rtas_query_irq_number(pci_get_pdn(pdev), desc->pci.msi_attrib.entry_nr);
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if (hwirq < 0) {
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dev_err(&pdev->dev, "Failed to query HW IRQ: %d\n", hwirq);
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return hwirq;
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@ -146,13 +146,13 @@ static int sparc64_setup_msi_irq(unsigned int *irq_p,
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msiqid = pick_msiq(pbm);
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err = ops->msi_setup(pbm, msiqid, msi,
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(entry->msi_attrib.is_64 ? 1 : 0));
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(entry->pci.msi_attrib.is_64 ? 1 : 0));
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if (err)
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goto out_msi_free;
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pbm->msi_irq_table[msi - pbm->msi_first] = *irq_p;
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if (entry->msi_attrib.is_64) {
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if (entry->pci.msi_attrib.is_64) {
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msg.address_hi = pbm->msi64_start >> 32;
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msg.address_lo = pbm->msi64_start & 0xffffffff;
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} else {
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@ -163,7 +163,7 @@ int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
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struct msi_desc *desc = first_pci_msi_entry(pdev);
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init_irq_alloc_info(arg, NULL);
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if (desc->msi_attrib.is_msix) {
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if (desc->pci.msi_attrib.is_msix) {
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arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSIX;
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} else {
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arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
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@ -306,7 +306,7 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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return -EINVAL;
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map_irq.table_base = pci_resource_start(dev, bir);
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map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
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map_irq.entry_nr = msidesc->pci.msi_attrib.entry_nr;
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}
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ret = -EINVAL;
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@ -398,7 +398,7 @@ static void xen_pv_teardown_msi_irqs(struct pci_dev *dev)
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{
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struct msi_desc *msidesc = first_pci_msi_entry(dev);
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if (msidesc->msi_attrib.is_msix)
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if (msidesc->pci.msi_attrib.is_msix)
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xen_pci_frontend_disable_msix(dev);
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else
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xen_pci_frontend_disable_msi(dev);
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@ -414,7 +414,7 @@ static int xen_msi_domain_alloc_irqs(struct irq_domain *domain,
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if (WARN_ON_ONCE(!dev_is_pci(dev)))
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return -EINVAL;
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if (first_msi_entry(dev)->msi_attrib.is_msix)
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if (first_msi_entry(dev)->pci.msi_attrib.is_msix)
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type = PCI_CAP_ID_MSIX;
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else
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type = PCI_CAP_ID_MSI;
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@ -911,7 +911,7 @@ static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
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}
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ab_pci->msi_ep_base_data = msi_desc->msg.data;
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if (msi_desc->msi_attrib.is_64)
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if (msi_desc->pci.msi_attrib.is_64)
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set_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags);
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ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data);
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@ -138,9 +138,9 @@ void __weak arch_restore_msi_irqs(struct pci_dev *dev)
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static inline __attribute_const__ u32 msi_multi_mask(struct msi_desc *desc)
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{
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/* Don't shift by >= width of type */
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if (desc->msi_attrib.multi_cap >= 5)
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if (desc->pci.msi_attrib.multi_cap >= 5)
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return 0xffffffff;
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return (1 << (1 << desc->msi_attrib.multi_cap)) - 1;
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return (1 << (1 << desc->pci.msi_attrib.multi_cap)) - 1;
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}
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static noinline void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set)
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@ -148,14 +148,14 @@ static noinline void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 s
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raw_spinlock_t *lock = &desc->dev->msi_lock;
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unsigned long flags;
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if (!desc->msi_attrib.can_mask)
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if (!desc->pci.msi_attrib.can_mask)
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return;
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raw_spin_lock_irqsave(lock, flags);
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desc->msi_mask &= ~clear;
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desc->msi_mask |= set;
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pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
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desc->msi_mask);
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desc->pci.msi_mask &= ~clear;
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desc->pci.msi_mask |= set;
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pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->pci.mask_pos,
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desc->pci.msi_mask);
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raw_spin_unlock_irqrestore(lock, flags);
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}
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@ -171,7 +171,7 @@ static inline void pci_msi_unmask(struct msi_desc *desc, u32 mask)
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static inline void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
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{
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return desc->mask_base + desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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return desc->pci.mask_base + desc->pci.msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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}
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/*
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@ -184,27 +184,27 @@ static void pci_msix_write_vector_ctrl(struct msi_desc *desc, u32 ctrl)
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{
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void __iomem *desc_addr = pci_msix_desc_addr(desc);
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if (desc->msi_attrib.can_mask)
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if (desc->pci.msi_attrib.can_mask)
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writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
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}
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static inline void pci_msix_mask(struct msi_desc *desc)
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{
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desc->msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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pci_msix_write_vector_ctrl(desc, desc->msix_ctrl);
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desc->pci.msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl);
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/* Flush write to device */
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readl(desc->mask_base);
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readl(desc->pci.mask_base);
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}
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static inline void pci_msix_unmask(struct msi_desc *desc)
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{
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desc->msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
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pci_msix_write_vector_ctrl(desc, desc->msix_ctrl);
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desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
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pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl);
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}
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static void __pci_msi_mask_desc(struct msi_desc *desc, u32 mask)
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{
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if (desc->msi_attrib.is_msix)
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if (desc->pci.msi_attrib.is_msix)
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pci_msix_mask(desc);
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else
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pci_msi_mask(desc, mask);
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@ -212,7 +212,7 @@ static void __pci_msi_mask_desc(struct msi_desc *desc, u32 mask)
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static void __pci_msi_unmask_desc(struct msi_desc *desc, u32 mask)
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{
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if (desc->msi_attrib.is_msix)
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if (desc->pci.msi_attrib.is_msix)
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pci_msix_unmask(desc);
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else
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pci_msi_unmask(desc, mask);
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@ -256,10 +256,10 @@ void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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BUG_ON(dev->current_state != PCI_D0);
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if (entry->msi_attrib.is_msix) {
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if (entry->pci.msi_attrib.is_msix) {
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void __iomem *base = pci_msix_desc_addr(entry);
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if (WARN_ON_ONCE(entry->msi_attrib.is_virtual))
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if (WARN_ON_ONCE(entry->pci.msi_attrib.is_virtual))
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return;
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msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
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@ -271,7 +271,7 @@ void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
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&msg->address_lo);
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if (entry->msi_attrib.is_64) {
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if (entry->pci.msi_attrib.is_64) {
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
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&msg->address_hi);
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pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
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@ -289,12 +289,12 @@ void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
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/* Don't touch the hardware now */
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} else if (entry->msi_attrib.is_msix) {
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} else if (entry->pci.msi_attrib.is_msix) {
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void __iomem *base = pci_msix_desc_addr(entry);
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u32 ctrl = entry->msix_ctrl;
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u32 ctrl = entry->pci.msix_ctrl;
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bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT);
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if (entry->msi_attrib.is_virtual)
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if (entry->pci.msi_attrib.is_virtual)
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goto skip;
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/*
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@ -323,12 +323,12 @@ void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
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msgctl &= ~PCI_MSI_FLAGS_QSIZE;
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msgctl |= entry->msi_attrib.multiple << 4;
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msgctl |= entry->pci.msi_attrib.multiple << 4;
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
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msg->address_lo);
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if (entry->msi_attrib.is_64) {
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if (entry->pci.msi_attrib.is_64) {
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
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msg->address_hi);
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pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
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@ -376,9 +376,9 @@ static void free_msi_irqs(struct pci_dev *dev)
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pci_msi_teardown_msi_irqs(dev);
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list_for_each_entry_safe(entry, tmp, msi_list, list) {
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if (entry->msi_attrib.is_msix) {
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if (entry->pci.msi_attrib.is_msix) {
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if (list_is_last(&entry->list, msi_list))
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iounmap(entry->mask_base);
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iounmap(entry->pci.mask_base);
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}
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list_del(&entry->list);
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@ -420,7 +420,7 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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pci_msi_update_mask(entry, 0, 0);
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control &= ~PCI_MSI_FLAGS_QSIZE;
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control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
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control |= (entry->pci.msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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@ -449,7 +449,7 @@ static void __pci_restore_msix_state(struct pci_dev *dev)
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arch_restore_msi_irqs(dev);
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for_each_pci_msi_entry(entry, dev)
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pci_msix_write_vector_ctrl(entry, entry->msix_ctrl);
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pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl);
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pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
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}
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@ -481,24 +481,24 @@ msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
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if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
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control |= PCI_MSI_FLAGS_MASKBIT;
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entry->msi_attrib.is_msix = 0;
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entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
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entry->msi_attrib.is_virtual = 0;
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entry->msi_attrib.entry_nr = 0;
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entry->msi_attrib.can_mask = !pci_msi_ignore_mask &&
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entry->pci.msi_attrib.is_msix = 0;
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entry->pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
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entry->pci.msi_attrib.is_virtual = 0;
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entry->pci.msi_attrib.entry_nr = 0;
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entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
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!!(control & PCI_MSI_FLAGS_MASKBIT);
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entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
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entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
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entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
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entry->pci.msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
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entry->pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
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entry->pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
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if (control & PCI_MSI_FLAGS_64BIT)
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entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
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entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
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else
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entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
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entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
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/* Save the initial mask status */
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if (entry->msi_attrib.can_mask)
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pci_read_config_dword(dev, entry->mask_pos, &entry->msi_mask);
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if (entry->pci.msi_attrib.can_mask)
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pci_read_config_dword(dev, entry->pci.mask_pos, &entry->pci.msi_mask);
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out:
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kfree(masks);
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@ -630,26 +630,26 @@ static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
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goto out;
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}
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entry->msi_attrib.is_msix = 1;
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entry->msi_attrib.is_64 = 1;
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entry->pci.msi_attrib.is_msix = 1;
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entry->pci.msi_attrib.is_64 = 1;
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if (entries)
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entry->msi_attrib.entry_nr = entries[i].entry;
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entry->pci.msi_attrib.entry_nr = entries[i].entry;
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else
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entry->msi_attrib.entry_nr = i;
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entry->pci.msi_attrib.entry_nr = i;
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entry->msi_attrib.is_virtual =
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entry->msi_attrib.entry_nr >= vec_count;
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entry->pci.msi_attrib.is_virtual =
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entry->pci.msi_attrib.entry_nr >= vec_count;
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entry->msi_attrib.can_mask = !pci_msi_ignore_mask &&
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!entry->msi_attrib.is_virtual;
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entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
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!entry->pci.msi_attrib.is_virtual;
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entry->msi_attrib.default_irq = dev->irq;
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entry->mask_base = base;
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entry->pci.msi_attrib.default_irq = dev->irq;
|
||||
entry->pci.mask_base = base;
|
||||
|
||||
if (entry->msi_attrib.can_mask) {
|
||||
if (entry->pci.msi_attrib.can_mask) {
|
||||
addr = pci_msix_desc_addr(entry);
|
||||
entry->msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
|
||||
entry->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
|
||||
}
|
||||
|
||||
list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
|
||||
@ -874,7 +874,7 @@ static void pci_msi_shutdown(struct pci_dev *dev)
|
||||
pci_msi_unmask(desc, msi_multi_mask(desc));
|
||||
|
||||
/* Restore dev->irq to its default pin-assertion IRQ */
|
||||
dev->irq = desc->msi_attrib.default_irq;
|
||||
dev->irq = desc->pci.msi_attrib.default_irq;
|
||||
pcibios_alloc_irq(dev);
|
||||
}
|
||||
|
||||
@ -1203,7 +1203,7 @@ int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
|
||||
struct msi_desc *entry;
|
||||
|
||||
for_each_pci_msi_entry(entry, dev) {
|
||||
if (entry->msi_attrib.entry_nr == nr)
|
||||
if (entry->pci.msi_attrib.entry_nr == nr)
|
||||
return entry->irq;
|
||||
}
|
||||
WARN_ON_ONCE(1);
|
||||
@ -1242,7 +1242,7 @@ const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
|
||||
struct msi_desc *entry;
|
||||
|
||||
for_each_pci_msi_entry(entry, dev) {
|
||||
if (entry->msi_attrib.entry_nr == nr)
|
||||
if (entry->pci.msi_attrib.entry_nr == nr)
|
||||
return &entry->affinity->mask;
|
||||
}
|
||||
WARN_ON_ONCE(1);
|
||||
@ -1295,14 +1295,14 @@ static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc)
|
||||
{
|
||||
struct pci_dev *dev = msi_desc_to_pci_dev(desc);
|
||||
|
||||
return (irq_hw_number_t)desc->msi_attrib.entry_nr |
|
||||
return (irq_hw_number_t)desc->pci.msi_attrib.entry_nr |
|
||||
pci_dev_id(dev) << 11 |
|
||||
(pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
|
||||
}
|
||||
|
||||
static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
|
||||
{
|
||||
return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
|
||||
return !desc->pci.msi_attrib.is_msix && desc->nvec_used > 1;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1326,7 +1326,7 @@ int pci_msi_domain_check_cap(struct irq_domain *domain,
|
||||
if (pci_msi_desc_is_multi_msi(desc) &&
|
||||
!(info->flags & MSI_FLAG_MULTI_PCI_MSI))
|
||||
return 1;
|
||||
else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
|
||||
else if (desc->pci.msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
|
||||
return -ENOTSUPP;
|
||||
|
||||
return 0;
|
||||
|
||||
@ -263,7 +263,7 @@ static int pci_frontend_enable_msix(struct pci_dev *dev,
|
||||
|
||||
i = 0;
|
||||
for_each_pci_msi_entry(entry, dev) {
|
||||
op.msix_entries[i].entry = entry->msi_attrib.entry_nr;
|
||||
op.msix_entries[i].entry = entry->pci.msi_attrib.entry_nr;
|
||||
/* Vector is useless at this point. */
|
||||
op.msix_entries[i].vector = -1;
|
||||
i++;
|
||||
|
||||
@ -68,6 +68,42 @@ static inline void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
|
||||
typedef void (*irq_write_msi_msg_t)(struct msi_desc *desc,
|
||||
struct msi_msg *msg);
|
||||
|
||||
/**
|
||||
* pci_msi_desc - PCI/MSI specific MSI descriptor data
|
||||
*
|
||||
* @msi_mask: [PCI MSI] MSI cached mask bits
|
||||
* @msix_ctrl: [PCI MSI-X] MSI-X cached per vector control bits
|
||||
* @is_msix: [PCI MSI/X] True if MSI-X
|
||||
* @multiple: [PCI MSI/X] log2 num of messages allocated
|
||||
* @multi_cap: [PCI MSI/X] log2 num of messages supported
|
||||
* @can_mask: [PCI MSI/X] Masking supported?
|
||||
* @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit
|
||||
* @entry_nr: [PCI MSI/X] Entry which is described by this descriptor
|
||||
* @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
|
||||
* @mask_pos: [PCI MSI] Mask register position
|
||||
* @mask_base: [PCI MSI-X] Mask register base address
|
||||
*/
|
||||
struct pci_msi_desc {
|
||||
union {
|
||||
u32 msi_mask;
|
||||
u32 msix_ctrl;
|
||||
};
|
||||
struct {
|
||||
u8 is_msix : 1;
|
||||
u8 multiple : 3;
|
||||
u8 multi_cap : 3;
|
||||
u8 can_mask : 1;
|
||||
u8 is_64 : 1;
|
||||
u8 is_virtual : 1;
|
||||
u16 entry_nr;
|
||||
unsigned default_irq;
|
||||
} msi_attrib;
|
||||
union {
|
||||
u8 mask_pos;
|
||||
void __iomem *mask_base;
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* platform_msi_desc - Platform device specific msi descriptor data
|
||||
* @msi_priv_data: Pointer to platform private data
|
||||
@ -107,17 +143,7 @@ struct ti_sci_inta_msi_desc {
|
||||
* address or data changes
|
||||
* @write_msi_msg_data: Data parameter for the callback.
|
||||
*
|
||||
* @msi_mask: [PCI MSI] MSI cached mask bits
|
||||
* @msix_ctrl: [PCI MSI-X] MSI-X cached per vector control bits
|
||||
* @is_msix: [PCI MSI/X] True if MSI-X
|
||||
* @multiple: [PCI MSI/X] log2 num of messages allocated
|
||||
* @multi_cap: [PCI MSI/X] log2 num of messages supported
|
||||
* @maskbit: [PCI MSI/X] Mask-Pending bit supported?
|
||||
* @is_64: [PCI MSI/X] Address size: 0=32bit 1=64bit
|
||||
* @entry_nr: [PCI MSI/X] Entry which is described by this descriptor
|
||||
* @default_irq:[PCI MSI/X] The default pre-assigned non-MSI irq
|
||||
* @mask_pos: [PCI MSI] Mask register position
|
||||
* @mask_base: [PCI MSI-X] Mask register base address
|
||||
* @pci: [PCI] PCI speficic msi descriptor data
|
||||
* @platform: [platform] Platform device specific msi descriptor data
|
||||
* @fsl_mc: [fsl-mc] FSL MC device specific msi descriptor data
|
||||
* @inta: [INTA] TISCI based INTA specific msi descriptor data
|
||||
@ -138,38 +164,10 @@ struct msi_desc {
|
||||
void *write_msi_msg_data;
|
||||
|
||||
union {
|
||||
/* PCI MSI/X specific data */
|
||||
struct {
|
||||
union {
|
||||
u32 msi_mask;
|
||||
u32 msix_ctrl;
|
||||
};
|
||||
struct {
|
||||
u8 is_msix : 1;
|
||||
u8 multiple : 3;
|
||||
u8 multi_cap : 3;
|
||||
u8 can_mask : 1;
|
||||
u8 is_64 : 1;
|
||||
u8 is_virtual : 1;
|
||||
u16 entry_nr;
|
||||
unsigned default_irq;
|
||||
} msi_attrib;
|
||||
union {
|
||||
u8 mask_pos;
|
||||
void __iomem *mask_base;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Non PCI variants add their data structure here. New
|
||||
* entries need to use a named structure. We want
|
||||
* proper name spaces for this. The PCI part is
|
||||
* anonymous for now as it would require an immediate
|
||||
* tree wide cleanup.
|
||||
*/
|
||||
struct platform_msi_desc platform;
|
||||
struct fsl_mc_msi_desc fsl_mc;
|
||||
struct ti_sci_inta_msi_desc inta;
|
||||
struct pci_msi_desc pci;
|
||||
struct platform_msi_desc platform;
|
||||
struct fsl_mc_msi_desc fsl_mc;
|
||||
struct ti_sci_inta_msi_desc inta;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -91,7 +91,7 @@ static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
|
||||
return -ENODEV;
|
||||
|
||||
if (dev_is_pci(dev))
|
||||
is_msix = entry->msi_attrib.is_msix;
|
||||
is_msix = entry->pci.msi_attrib.is_msix;
|
||||
|
||||
return sysfs_emit(buf, "%s\n", is_msix ? "msix" : "msi");
|
||||
}
|
||||
@ -535,7 +535,7 @@ static bool msi_check_reservation_mode(struct irq_domain *domain,
|
||||
* masking and MSI does so when the can_mask attribute is set.
|
||||
*/
|
||||
desc = first_msi_entry(dev);
|
||||
return desc->msi_attrib.is_msix || desc->msi_attrib.can_mask;
|
||||
return desc->pci.msi_attrib.is_msix || desc->pci.msi_attrib.can_mask;
|
||||
}
|
||||
|
||||
int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user