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pwm: stm32: Implement .get_state()
Implement the &pwm_ops->get_state callback so drivers can inherit PWM state set by the bootloader. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [ukl: split off from a patch that also fixes clk enable count in .probe()] Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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@ -471,8 +471,50 @@ static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
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return ret;
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}
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static int stm32_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm, struct pwm_state *state)
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{
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
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int ch = pwm->hwpwm;
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unsigned long rate;
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u32 ccer, psc, arr, ccr;
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u64 dty, prd;
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int ret;
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mutex_lock(&priv->lock);
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ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
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if (ret)
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goto out;
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state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4));
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state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ?
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PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
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ret = regmap_read(priv->regmap, TIM_PSC, &psc);
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if (ret)
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goto out;
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ret = regmap_read(priv->regmap, TIM_ARR, &arr);
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if (ret)
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goto out;
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ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr);
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if (ret)
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goto out;
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rate = clk_get_rate(priv->clk);
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prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1);
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state->period = DIV_ROUND_UP_ULL(prd, rate);
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dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr;
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state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
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out:
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mutex_unlock(&priv->lock);
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return ret;
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}
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static const struct pwm_ops stm32pwm_ops = {
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.apply = stm32_pwm_apply_locked,
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.get_state = stm32_pwm_get_state,
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.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
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};
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