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gpio: ich: Add blink capability option
This patch allows gpio_ich driver to be aware of non blink capable chipsets. Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -62,6 +62,9 @@ struct ichx_desc {
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/* Max GPIO pins the chipset can have */
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/* Max GPIO pins the chipset can have */
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uint ngpio;
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uint ngpio;
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/* GPO_BLINK is available on this chipset */
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bool have_blink;
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/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
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/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
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bool uses_gpe0;
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bool uses_gpe0;
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@ -151,7 +154,7 @@ static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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int val)
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int val)
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{
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{
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/* Disable blink hardware which is available for GPIOs from 0 to 31. */
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/* Disable blink hardware which is available for GPIOs from 0 to 31. */
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if (nr < 32)
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if (nr < 32 && ichx_priv.desc->have_blink)
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ichx_write_bit(GPO_BLINK, nr, 0, 0);
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ichx_write_bit(GPO_BLINK, nr, 0, 0);
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/* Set GPIO output value. */
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/* Set GPIO output value. */
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@ -266,6 +269,7 @@ static struct ichx_desc ich6_desc = {
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.uses_gpe0 = true,
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.uses_gpe0 = true,
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.ngpio = 50,
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.ngpio = 50,
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.have_blink = true,
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};
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};
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/* Intel 3100 */
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/* Intel 3100 */
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@ -290,19 +294,23 @@ static struct ichx_desc i3100_desc = {
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/* ICH7 and ICH8-based */
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/* ICH7 and ICH8-based */
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static struct ichx_desc ich7_desc = {
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static struct ichx_desc ich7_desc = {
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.ngpio = 50,
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.ngpio = 50,
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.have_blink = true,
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};
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};
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/* ICH9-based */
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/* ICH9-based */
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static struct ichx_desc ich9_desc = {
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static struct ichx_desc ich9_desc = {
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.ngpio = 61,
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.ngpio = 61,
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.have_blink = true,
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};
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};
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/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
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/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
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static struct ichx_desc ich10_cons_desc = {
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static struct ichx_desc ich10_cons_desc = {
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.ngpio = 61,
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.ngpio = 61,
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.have_blink = true,
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};
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};
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static struct ichx_desc ich10_corp_desc = {
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static struct ichx_desc ich10_corp_desc = {
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.ngpio = 72,
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.ngpio = 72,
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.have_blink = true,
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};
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};
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/* Intel 5 series, 6 series, 3400 series, and C200 series */
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/* Intel 5 series, 6 series, 3400 series, and C200 series */
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