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octeontx2-af: cn10k: Mailbox changes for CN10K CPT

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Adds changes to existing CPT mailbox messages to support
CN10K CPT block. This patch also adds new register defines
for CN10K CPT.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Srujana Challa 2021-04-21 14:53:00 +05:30 committed by David S. Miller
parent a926c025d5
commit e4bbc5c53a
2 changed files with 31 additions and 1 deletions
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11
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
View File

@ -9,6 +9,10 @@
/* CPT PF device id */
#define PCI_DEVID_OTX2_CPT_PF 0xA0FD
#define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2
/* Length of initial context fetch in 128 byte words */
#define CPT_CTX_ILEN 2
static int get_cpt_pf_num(struct rvu *rvu)
{
@ -21,7 +25,8 @@ static int get_cpt_pf_num(struct rvu *rvu)
if (!pdev)
continue;
if (pdev->device == PCI_DEVID_OTX2_CPT_PF) {
if (pdev->device == PCI_DEVID_OTX2_CPT_PF ||
pdev->device == PCI_DEVID_OTX2_CPT10K_PF) {
cpt_pf_num = i;
put_device(&pdev->dev);
break;
@ -103,6 +108,9 @@ int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu,
/* Set CPT LF group and priority */
val = (u64)req->eng_grpmsk << 48 | 1;
if (!is_rvu_otx2(rvu))
val |= (CPT_CTX_ILEN << 17);
rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
/* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC */
@ -192,6 +200,7 @@ static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
case CPT_AF_PF_FUNC:
case CPT_AF_BLK_RST:
case CPT_AF_CONSTANTS1:
case CPT_AF_CTX_FLUSH_TIMER:
return true;
}

21
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
View File

@ -494,6 +494,27 @@
#define CPT_AF_RAS_INT_W1S (0x47028)
#define CPT_AF_RAS_INT_ENA_W1S (0x47030)
#define CPT_AF_RAS_INT_ENA_W1C (0x47038)
#define CPT_AF_CTX_FLUSH_TIMER (0x48000ull)
#define CPT_AF_CTX_ERR (0x48008ull)
#define CPT_AF_CTX_ENC_ID (0x48010ull)
#define CPT_AF_CTX_MIS_PC (0x49400ull)
#define CPT_AF_CTX_HIT_PC (0x49408ull)
#define CPT_AF_CTX_AOP_PC (0x49410ull)
#define CPT_AF_CTX_AOP_LATENCY_PC (0x49418ull)
#define CPT_AF_CTX_IFETCH_PC (0x49420ull)
#define CPT_AF_CTX_IFETCH_LATENCY_PC (0x49428ull)
#define CPT_AF_CTX_FFETCH_PC (0x49430ull)
#define CPT_AF_CTX_FFETCH_LATENCY_PC (0x49438ull)
#define CPT_AF_CTX_WBACK_PC (0x49440ull)
#define CPT_AF_CTX_WBACK_LATENCY_PC (0x49448ull)
#define CPT_AF_CTX_PSH_PC (0x49450ull)
#define CPT_AF_CTX_PSH_LATENCY_PC (0x49458ull)
#define CPT_AF_RXC_TIME (0x50010ull)
#define CPT_AF_RXC_TIME_CFG (0x50018ull)
#define CPT_AF_RXC_DFRG (0x50020ull)
#define CPT_AF_RXC_ACTIVE_STS (0x50028ull)
#define CPT_AF_RXC_ZOMBIE_STS (0x50030ull)
#define CPT_AF_X2PX_LINK_CFG(a) (0x51000ull | (u64)(a) << 3)
#define AF_BAR2_ALIASX(a, b) (0x9100000ull | (a) << 12 | (b))
#define CPT_AF_BAR2_SEL 0x9000000