From e4a7e67a08ac409f1485c82a2190636d5c81b932 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 4 Oct 2022 15:24:14 -0500 Subject: [PATCH] irqchip/imx-mu-msi: Fix wrong register offset for 8ulp Offset 0x124 should be for IMX_MU_TSR, not IMX_MU_GSR. Fixes: 70afdab904d2 ("irqchip: Add IMX MU MSI controller driver") Reported-by: Colin King Signed-off-by: Frank Li [maz: updated commit message, tags] Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20221004202414.216577-1-Frank.Li@nxp.com --- drivers/irqchip/irq-imx-mu-msi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-msi.c index b62139dc36e8..229039eda1b1 100644 --- a/drivers/irqchip/irq-imx-mu-msi.c +++ b/drivers/irqchip/irq-imx-mu-msi.c @@ -292,7 +292,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { .xSR = { [IMX_MU_SR] = 0xC, [IMX_MU_GSR] = 0x118, - [IMX_MU_GSR] = 0x124, + [IMX_MU_TSR] = 0x124, [IMX_MU_RSR] = 0x12C, }, .xCR = {