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irqchip/imx-mu-msi: Fix wrong register offset for 8ulp
Offset 0x124 should be for IMX_MU_TSR, not IMX_MU_GSR.
Fixes: 70afdab904
("irqchip: Add IMX MU MSI controller driver")
Reported-by: Colin King <colin.i.king@gmail.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[maz: updated commit message, tags]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221004202414.216577-1-Frank.Li@nxp.com
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@ -292,7 +292,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
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.xSR = {
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[IMX_MU_SR] = 0xC,
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[IMX_MU_GSR] = 0x118,
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[IMX_MU_GSR] = 0x124,
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[IMX_MU_TSR] = 0x124,
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[IMX_MU_RSR] = 0x12C,
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},
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.xCR = {
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