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MIPS: Lantiq: Add PCI controller support.
The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds the driver that allows us to use the EBU as a PCI controller. In order for PCI to work the EBU is set to endianess swap all the data. In addition we need to make use of SWAP_IO_SPACE for device->host DMA to work. The clock of the PCI works in several modes (internal/external). If this is not configured correctly the SoC will hang. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2250/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin
Ralf Baechle
parent
8ec6d93508
commit
e47d488935
46
arch/mips/include/asm/mach-lantiq/lantiq_platform.h
Normal file
46
arch/mips/include/asm/mach-lantiq/lantiq_platform.h
Normal file
@ -0,0 +1,46 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _LANTIQ_PLATFORM_H__
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#define _LANTIQ_PLATFORM_H__
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#include <linux/mtd/partitions.h>
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/* struct used to pass info to the pci core */
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enum {
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PCI_CLOCK_INT = 0,
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PCI_CLOCK_EXT
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};
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#define PCI_EXIN0 0x0001
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#define PCI_EXIN1 0x0002
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#define PCI_EXIN2 0x0004
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#define PCI_EXIN3 0x0008
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#define PCI_EXIN4 0x0010
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#define PCI_EXIN5 0x0020
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#define PCI_EXIN_MAX 6
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#define PCI_GNT1 0x0040
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#define PCI_GNT2 0x0080
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#define PCI_GNT3 0x0100
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#define PCI_GNT4 0x0200
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#define PCI_REQ1 0x0400
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#define PCI_REQ2 0x0800
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#define PCI_REQ3 0x1000
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#define PCI_REQ4 0x2000
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#define PCI_REQ_SHIFT 10
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#define PCI_REQ_MASK 0xf
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struct ltq_pci_data {
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int clock;
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int gpio;
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int irq[16];
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};
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#endif
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@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
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obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
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obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
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obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
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obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o
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obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
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obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
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obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
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116
arch/mips/pci/ops-lantiq.c
Normal file
116
arch/mips/pci/ops-lantiq.c
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@ -0,0 +1,116 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <asm/addrspace.h>
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#include <linux/vmalloc.h>
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#include <lantiq_soc.h>
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#include "pci-lantiq.h"
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#define LTQ_PCI_CFG_BUSNUM_SHF 16
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#define LTQ_PCI_CFG_DEVNUM_SHF 11
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#define LTQ_PCI_CFG_FUNNUM_SHF 8
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
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unsigned int devfn, unsigned int where, u32 *data)
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{
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unsigned long cfg_base;
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unsigned long flags;
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u32 temp;
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/* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
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SoC itself */
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if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
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|| ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
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return 1;
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spin_lock_irqsave(&ebu_lock, flags);
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cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
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LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
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/* Perform access */
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if (access_type == PCI_ACCESS_WRITE) {
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ltq_w32(swab32(*data), ((u32 *)cfg_base));
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} else {
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*data = ltq_r32(((u32 *)(cfg_base)));
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*data = swab32(*data);
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}
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wmb();
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/* clean possible Master abort */
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cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
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temp = ltq_r32(((u32 *)(cfg_base)));
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temp = swab32(temp);
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cfg_base = (unsigned long) ltq_pci_mapped_cfg;
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cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
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ltq_w32(temp, ((u32 *)cfg_base));
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spin_unlock_irqrestore(&ebu_lock, flags);
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if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
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return 1;
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return 0;
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}
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int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 data = 0;
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if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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if (size == 4) {
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data = val;
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} else {
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if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
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devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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297
arch/mips/pci/pci-lantiq.c
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297
arch/mips/pci/pci-lantiq.c
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@ -0,0 +1,297 @@
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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#include <linux/platform_device.h>
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#include <asm/pci.h>
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#include <asm/gpio.h>
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#include <asm/addrspace.h>
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#include <lantiq_soc.h>
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#include <lantiq_irq.h>
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#include <lantiq_platform.h>
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#include "pci-lantiq.h"
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#define LTQ_PCI_CFG_BASE 0x17000000
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#define LTQ_PCI_CFG_SIZE 0x00008000
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#define LTQ_PCI_MEM_BASE 0x18000000
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#define LTQ_PCI_MEM_SIZE 0x02000000
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#define LTQ_PCI_IO_BASE 0x1AE00000
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#define LTQ_PCI_IO_SIZE 0x00200000
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#define PCI_CR_FCI_ADDR_MAP0 0x00C0
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#define PCI_CR_FCI_ADDR_MAP1 0x00C4
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#define PCI_CR_FCI_ADDR_MAP2 0x00C8
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#define PCI_CR_FCI_ADDR_MAP3 0x00CC
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#define PCI_CR_FCI_ADDR_MAP4 0x00D0
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#define PCI_CR_FCI_ADDR_MAP5 0x00D4
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#define PCI_CR_FCI_ADDR_MAP6 0x00D8
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#define PCI_CR_FCI_ADDR_MAP7 0x00DC
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#define PCI_CR_CLK_CTRL 0x0000
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#define PCI_CR_PCI_MOD 0x0030
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#define PCI_CR_PC_ARB 0x0080
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#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
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#define PCI_CR_BAR11MASK 0x0044
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#define PCI_CR_BAR12MASK 0x0048
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#define PCI_CR_BAR13MASK 0x004C
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#define PCI_CS_BASE_ADDR1 0x0010
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#define PCI_CR_PCI_ADDR_MAP11 0x0064
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#define PCI_CR_FCI_BURST_LENGTH 0x00E8
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#define PCI_CR_PCI_EOI 0x002C
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#define PCI_CS_STS_CMD 0x0004
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#define PCI_MASTER0_REQ_MASK_2BITS 8
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#define PCI_MASTER1_REQ_MASK_2BITS 10
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#define PCI_MASTER2_REQ_MASK_2BITS 12
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#define INTERNAL_ARB_ENABLE_BIT 0
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#define LTQ_CGU_IFCCR 0x0018
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#define LTQ_CGU_PCICR 0x0034
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#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
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#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
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#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
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#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
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struct ltq_pci_gpio_map {
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int pin;
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int alt0;
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int alt1;
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int dir;
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char *name;
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};
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/* the pci core can make use of the following gpios */
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static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
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{ 0, 1, 0, 0, "pci-exin0" },
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{ 1, 1, 0, 0, "pci-exin1" },
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{ 2, 1, 0, 0, "pci-exin2" },
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{ 39, 1, 0, 0, "pci-exin3" },
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{ 10, 1, 0, 0, "pci-exin4" },
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{ 9, 1, 0, 0, "pci-exin5" },
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{ 30, 1, 0, 1, "pci-gnt1" },
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{ 23, 1, 0, 1, "pci-gnt2" },
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{ 19, 1, 0, 1, "pci-gnt3" },
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{ 38, 1, 0, 1, "pci-gnt4" },
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{ 29, 1, 0, 0, "pci-req1" },
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{ 31, 1, 0, 0, "pci-req2" },
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{ 3, 1, 0, 0, "pci-req3" },
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{ 37, 1, 0, 0, "pci-req4" },
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};
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__iomem void *ltq_pci_mapped_cfg;
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static __iomem void *ltq_pci_membase;
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int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
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/* Since the PCI REQ pins can be reused for other functionality, make it
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possible to exclude those from interpretation by the PCI controller */
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static int ltq_pci_req_mask = 0xf;
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static int *ltq_pci_irq_map;
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struct pci_ops ltq_pci_ops = {
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.read = ltq_pci_read_config_dword,
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.write = ltq_pci_write_config_dword
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};
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static struct resource pci_io_resource = {
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.name = "pci io space",
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.start = LTQ_PCI_IO_BASE,
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.end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource pci_mem_resource = {
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.name = "pci memory space",
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.start = LTQ_PCI_MEM_BASE,
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.end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller ltq_pci_controller = {
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.pci_ops = <q_pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &pci_io_resource,
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.io_offset = 0x00000000UL,
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};
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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if (ltqpci_plat_dev_init)
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return ltqpci_plat_dev_init(dev);
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return 0;
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}
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static u32 ltq_calc_bar11mask(void)
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{
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u32 mem, bar11mask;
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/* BAR11MASK value depends on available memory on system. */
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mem = num_physpages * PAGE_SIZE;
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bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
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return bar11mask;
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}
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static void ltq_pci_setup_gpio(int gpio)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
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if (gpio & (1 << i)) {
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ltq_gpio_request(ltq_pci_gpio_map[i].pin,
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ltq_pci_gpio_map[i].alt0,
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ltq_pci_gpio_map[i].alt1,
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ltq_pci_gpio_map[i].dir,
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ltq_pci_gpio_map[i].name);
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}
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}
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ltq_gpio_request(21, 0, 0, 1, "pci-reset");
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ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
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}
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static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
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{
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u32 temp_buffer;
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/* set clock to 33Mhz */
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
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/* external or internal clock ? */
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if (conf->clock) {
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16),
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LTQ_CGU_IFCCR);
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ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR);
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} else {
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ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16),
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LTQ_CGU_IFCCR);
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ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR);
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}
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/* setup pci clock and gpis used by pci */
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ltq_pci_setup_gpio(conf->gpio);
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/* enable auto-switching between PCI and EBU */
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ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
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/* busy, i.e. configuration is not done, PCI access has to be retried */
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ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
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wmb();
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/* BUS Master/IO/MEM access */
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ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
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/* enable external 2 PCI masters */
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temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
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temp_buffer &= (~(ltq_pci_req_mask << 16));
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/* enable internal arbiter */
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temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
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/* enable internal PCI master reqest */
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temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
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/* enable EBU request */
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temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
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/* enable all external masters request */
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temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
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ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
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wmb();
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/* setup BAR memory regions */
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ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
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ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
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ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
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ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
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ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
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ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
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ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
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ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
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ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
|
||||
ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
|
||||
ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
|
||||
ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
|
||||
/* both TX and RX endian swap are enabled */
|
||||
ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
|
||||
wmb();
|
||||
ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
|
||||
PCI_CR_BAR12MASK);
|
||||
ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
|
||||
PCI_CR_BAR13MASK);
|
||||
/*use 8 dw burst length */
|
||||
ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
|
||||
ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
|
||||
wmb();
|
||||
|
||||
/* setup irq line */
|
||||
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
|
||||
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
|
||||
|
||||
/* toggle reset pin */
|
||||
__gpio_set_value(21, 0);
|
||||
wmb();
|
||||
mdelay(1);
|
||||
__gpio_set_value(21, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
if (ltq_pci_irq_map[slot])
|
||||
return ltq_pci_irq_map[slot];
|
||||
printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
|
||||
slot);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit ltq_pci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ltq_pci_data *ltq_pci_data =
|
||||
(struct ltq_pci_data *) pdev->dev.platform_data;
|
||||
pci_probe_only = 0;
|
||||
ltq_pci_irq_map = ltq_pci_data->irq;
|
||||
ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
|
||||
ltq_pci_mapped_cfg =
|
||||
ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
|
||||
ltq_pci_controller.io_map_base =
|
||||
(unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
|
||||
ltq_pci_startup(ltq_pci_data);
|
||||
register_pci_controller(<q_pci_controller);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver
|
||||
ltq_pci_driver = {
|
||||
.probe = ltq_pci_probe,
|
||||
.driver = {
|
||||
.name = "ltq_pci",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
int __init pcibios_init(void)
|
||||
{
|
||||
int ret = platform_driver_register(<q_pci_driver);
|
||||
if (ret)
|
||||
printk(KERN_INFO "ltq_pci: Error registering platfom driver!");
|
||||
return ret;
|
||||
}
|
||||
|
||||
arch_initcall(pcibios_init);
|
||||
18
arch/mips/pci/pci-lantiq.h
Normal file
18
arch/mips/pci/pci-lantiq.h
Normal file
@ -0,0 +1,18 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*
|
||||
* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
|
||||
*/
|
||||
|
||||
#ifndef _LTQ_PCI_H__
|
||||
#define _LTQ_PCI_H__
|
||||
|
||||
extern __iomem void *ltq_pci_mapped_cfg;
|
||||
extern int ltq_pci_read_config_dword(struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 *val);
|
||||
extern int ltq_pci_write_config_dword(struct pci_bus *bus,
|
||||
unsigned int devfn, int where, int size, u32 val);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user