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scsi: ufs: ufs-exynos: Change pclk available max value

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To support 167MHz PCLK, we need to adjust the maximum value.

Link: https://lore.kernel.org/r/20211018124216.153072-4-chanho61.park@samsung.com
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Chanho Park 2021-10-18 21:42:04 +09:00 committed by Martin K. Petersen
parent 10fb4f8743
commit e387d448e4
1 changed files with 1 additions and 1 deletions
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drivers/scsi/ufs/ufs-exynos.h
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@ -99,7 +99,7 @@ struct exynos_ufs;
#define PA_HIBERN8TIME_VAL 0x20
#define PCLK_AVAIL_MIN 70000000
#define PCLK_AVAIL_MAX 133000000
#define PCLK_AVAIL_MAX 167000000
struct exynos_ufs_uic_attr {
/* TX Attributes */