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Merge branch 'net-mtk_eth_soc-improve-pcs-implementation'
Russell King says:
====================
net: mtk_eth_soc: improve PCS implementation
As a result of invesigations from Frank Wunderlich, we know a lot more
about the Mediatek "SGMII" PCS block, and can implement the PCS support
correctly. This series achieves that, and Frank has tested the final
result and reports that it works for him. The series could do with
further testing by others, but I suspect that is unlikely to happen
until it is merged based on past performances with this driver.
Briefly, the patches in order:
1. Add a new helper to get the link timer duration in nanoseconds
2. Add definitions for the newly discovered registers and updates to
bit definitions, including bitmasks for the BMCR, BMSR and two
advertisement registers.
3. Remove unnecessary/unused error handling (functions always returning
zero.)
4. Adding the missing pcs_get_state() implementation.
5. Converting the code to use regmap_update_bits() rather than
open-coding read-modify-write sequences.
6. Adding out-of-band speed and duplex forcing for all non-inband modes
not just the 802.3z link modes the code currently does.
7. Moving the release of the PHY power down to the main pcs_config()
function.
8. Moving the interface speed selection to the main pcs_config()
function.
9. Adding advertisement programming.
10. Adding correct link timer programming using the new helper in the
first patch.
11. Adding support for 802.3z negotiation.
There is one remaining issue - when configuring the PCS for in-band,
for some reason the AN restart bit is always set. This should not be
necessary, but requires further investigation with the hardware to
find out whether it is really necessary. I suspect this was a work
around for a previous poor implementation.
====================
Link: https://lore.kernel.org/r/Y1qDMw+DJLAJHT40@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
e385592066
@ -466,8 +466,10 @@
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#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
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/* SGMII subsystem config registers */
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/* Register to auto-negotiation restart */
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/* BMCR (low 16) BMSR (high 16) */
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#define SGMSYS_PCS_CONTROL_1 0x0
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#define SGMII_BMCR GENMASK(15, 0)
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#define SGMII_BMSR GENMASK(31, 16)
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#define SGMII_AN_RESTART BIT(9)
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#define SGMII_ISOLATE BIT(10)
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#define SGMII_AN_ENABLE BIT(12)
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@ -477,13 +479,18 @@
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#define SGMII_PCS_FAULT BIT(23)
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#define SGMII_AN_EXPANSION_CLR BIT(30)
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#define SGMSYS_PCS_ADVERTISE 0x8
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#define SGMII_ADVERTISE GENMASK(15, 0)
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#define SGMII_LPA GENMASK(31, 16)
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/* Register to programmable link timer, the unit in 2 * 8ns */
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#define SGMSYS_PCS_LINK_TIMER 0x18
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#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
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#define SGMII_LINK_TIMER_MASK GENMASK(19, 0)
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#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK)
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/* Register to control remote fault */
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#define SGMSYS_SGMII_MODE 0x20
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#define SGMII_IF_MODE_BIT0 BIT(0)
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#define SGMII_IF_MODE_SGMII BIT(0)
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#define SGMII_SPEED_DUPLEX_AN BIT(1)
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#define SGMII_SPEED_MASK GENMASK(3, 2)
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#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
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@ -19,62 +19,18 @@ static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs)
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return container_of(pcs, struct mtk_pcs, pcs);
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}
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/* For SGMII interface mode */
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static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
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static void mtk_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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unsigned int val;
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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unsigned int bm, adv;
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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/* Read the BMSR and LPA */
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm);
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regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
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regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val |= SGMII_REMOTE_FAULT_DIS;
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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val |= SGMII_AN_RESTART;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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}
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/* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
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* fixed speed.
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*/
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static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
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phy_interface_t interface)
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{
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unsigned int val;
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regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
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val &= ~RG_PHY_SPEED_MASK;
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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val |= RG_PHY_SPEED_3_125G;
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regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
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/* Disable SGMII AN */
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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val &= ~SGMII_AN_ENABLE;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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/* Set the speed etc but leave the duplex unchanged */
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regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
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val |= SGMII_SPEED_1000;
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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/* Release PHYA power down state */
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regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm),
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FIELD_GET(SGMII_LPA, adv));
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}
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static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
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@ -83,46 +39,116 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
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bool permit_pause_to_mac)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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int err = 0;
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unsigned int rgc3, sgm_mode, bmcr;
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int advertise, link_timer;
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bool changed, use_an;
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/* Setup SGMIISYS with the determined property */
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if (interface != PHY_INTERFACE_MODE_SGMII)
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err = mtk_pcs_setup_mode_force(mpcs, interface);
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else if (phylink_autoneg_inband(mode))
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err = mtk_pcs_setup_mode_an(mpcs);
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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rgc3 = RG_PHY_SPEED_3_125G;
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else
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rgc3 = 0;
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return err;
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advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
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advertising);
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if (advertise < 0)
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return advertise;
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link_timer = phylink_get_link_timer_ns(interface);
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if (link_timer < 0)
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return link_timer;
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/* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
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* we assume that fixes it's speed at bitrate = line rate (in
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* other words, 1000Mbps or 2500Mbps).
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*/
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if (interface == PHY_INTERFACE_MODE_SGMII) {
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sgm_mode = SGMII_IF_MODE_SGMII;
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if (phylink_autoneg_inband(mode)) {
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sgm_mode |= SGMII_REMOTE_FAULT_DIS |
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SGMII_SPEED_DUPLEX_AN;
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use_an = true;
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} else {
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use_an = false;
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}
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} else if (phylink_autoneg_inband(mode)) {
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/* 1000base-X or 2500base-X autoneg */
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sgm_mode = SGMII_REMOTE_FAULT_DIS;
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use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
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advertising);
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} else {
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/* 1000base-X or 2500base-X without autoneg */
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sgm_mode = 0;
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use_an = false;
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}
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if (use_an) {
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/* FIXME: Do we need to set AN_RESTART here? */
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bmcr = SGMII_AN_RESTART | SGMII_AN_ENABLE;
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} else {
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bmcr = 0;
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}
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/* Configure the underlying interface speed */
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regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
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RG_PHY_SPEED_3_125G, rgc3);
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/* Update the advertisement, noting whether it has changed */
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regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
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SGMII_ADVERTISE, advertise, &changed);
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER, link_timer / 2 / 8);
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/* Update the sgmsys mode register */
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regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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SGMII_REMOTE_FAULT_DIS | SGMII_SPEED_DUPLEX_AN |
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SGMII_IF_MODE_SGMII, sgm_mode);
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/* Update the BMCR */
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regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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SGMII_AN_RESTART | SGMII_AN_ENABLE, bmcr);
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/* Release PHYA power down state */
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regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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SGMII_PHYA_PWD, 0);
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return changed;
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}
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static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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unsigned int val;
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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val |= SGMII_AN_RESTART;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
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SGMII_AN_RESTART, SGMII_AN_RESTART);
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}
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static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface, int speed, int duplex)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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unsigned int val;
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unsigned int sgm_mode;
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if (!phy_interface_mode_is_8023z(interface))
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return;
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if (!phylink_autoneg_inband(mode)) {
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/* Force the speed and duplex setting */
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if (speed == SPEED_10)
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sgm_mode = SGMII_SPEED_10;
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else if (speed == SPEED_100)
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sgm_mode = SGMII_SPEED_100;
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else
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sgm_mode = SGMII_SPEED_1000;
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/* SGMII force duplex setting */
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regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val &= ~SGMII_DUPLEX_FULL;
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if (duplex == DUPLEX_FULL)
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val |= SGMII_DUPLEX_FULL;
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if (duplex == DUPLEX_FULL)
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sgm_mode |= SGMII_DUPLEX_FULL;
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
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SGMII_DUPLEX_FULL | SGMII_SPEED_MASK,
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sgm_mode);
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}
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}
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static const struct phylink_pcs_ops mtk_pcs_ops = {
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.pcs_get_state = mtk_pcs_get_state,
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.pcs_config = mtk_pcs_config,
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.pcs_an_restart = mtk_pcs_restart_an,
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.pcs_link_up = mtk_pcs_link_up,
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@ -616,6 +616,30 @@ int phylink_speed_up(struct phylink *pl);
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void phylink_set_port_modes(unsigned long *bits);
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/**
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* phylink_get_link_timer_ns - return the PCS link timer value
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* @interface: link &typedef phy_interface_t mode
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*
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* Return the PCS link timer setting in nanoseconds for the PHY @interface
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* mode, or -EINVAL if not appropriate.
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*/
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static inline int phylink_get_link_timer_ns(phy_interface_t interface)
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{
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switch (interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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return 1600000;
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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return 10000000;
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default:
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return -EINVAL;
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}
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}
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void phylink_mii_c22_pcs_decode_state(struct phylink_link_state *state,
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u16 bmsr, u16 lpa);
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void phylink_mii_c22_pcs_get_state(struct mdio_device *pcs,
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