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ARM: 6336/1: U8500 PRCMU driver
Add an initial driver for communicating with the Power, Reset and Clock Management Unit (PRCMU) firmware in U8500. This initial version supports AB8500 communication only. Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Linus Walleij
Russell King
parent
008f8a2f7f
commit
e3726fcf26
@ -4,7 +4,7 @@
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obj-y := clock.o cpu.o devices.o
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obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o
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obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
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obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o
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obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o
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obj-$(CONFIG_MACH_U5500) += board-u5500.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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@ -41,6 +41,7 @@
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#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
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#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
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#define IRQ_AB4500 (IRQ_SHPI_START + 40)
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#define IRQ_PRCMU (IRQ_SHPI_START + 47)
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#define IRQ_DISP (IRQ_SHPI_START + 48)
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#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
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#define IRQ_I2C4 (IRQ_SHPI_START + 51)
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91
arch/arm/mach-ux500/include/mach/prcmu-regs.h
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91
arch/arm/mach-ux500/include/mach/prcmu-regs.h
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@ -0,0 +1,91 @@
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/*
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* Copyright (c) 2009 ST-Ericsson SA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*/
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#ifndef __MACH_PRCMU_REGS_H
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#define __MACH_PRCMU_REGS_H
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#include <mach/hardware.h>
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#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
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#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
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#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
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#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
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#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
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#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
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#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
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#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
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#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
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/* ARM WFI Standby signal register */
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#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
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#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
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/* CPU mailbox registers */
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#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
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#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
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#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
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/* Dual A9 core interrupt management unit registers */
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#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
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#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
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#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
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#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
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#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
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#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
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#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
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#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
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#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
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#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
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#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
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#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
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#define ARM_WAKEUP_MODEM 0x1
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#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
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#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
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#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
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#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
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#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
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#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
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#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
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#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
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#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
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#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
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#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
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/* System reset register */
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#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
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/* Level shifter and clamp control registers */
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#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
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#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
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/* PRCMU clock/PLL/reset registers */
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#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
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#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
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#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
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#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
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#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
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#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
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#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
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#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
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#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
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#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
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/* ePOD and memory power signal control registers */
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#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
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#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
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/* Debug power control unit registers */
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#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
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/* Miscellaneous unit registers */
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#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
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#endif /* __MACH_PRCMU__REGS_H */
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15
arch/arm/mach-ux500/include/mach/prcmu.h
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15
arch/arm/mach-ux500/include/mach/prcmu.h
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@ -0,0 +1,15 @@
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/*
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* Copyright (C) STMicroelectronics 2009
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License v2
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*
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* PRCMU f/w APIs
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*/
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#ifndef __MACH_PRCMU_H
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#define __MACH_PRCMU_H
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int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
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int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
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#endif /* __MACH_PRCMU_H */
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231
arch/arm/mach-ux500/prcmu.c
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231
arch/arm/mach-ux500/prcmu.c
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@ -0,0 +1,231 @@
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/*
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* Copyright (C) ST Ericsson SA 2010
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*
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* License Terms: GNU General Public License v2
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* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
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*
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* U8500 PRCMU driver.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/mutex.h>
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#include <linux/completion.h>
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#include <linux/jiffies.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <mach/hardware.h>
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#include <mach/prcmu-regs.h>
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#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE)
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#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44)
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#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4)
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#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
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#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
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#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
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#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
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#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
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#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
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#define I2C_WRITE(slave) ((slave) << 1)
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#define I2C_READ(slave) (((slave) << 1) | BIT(0))
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#define I2C_STOP_EN BIT(3)
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enum ack_mb5_status {
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I2C_WR_OK = 0x01,
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I2C_RD_OK = 0x02,
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};
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#define MBOX_BIT BIT
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#define NUM_MBOX 8
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static struct {
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struct mutex lock;
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struct completion work;
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bool failed;
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struct {
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u8 status;
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u8 value;
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} ack;
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} mb5_transfer;
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/**
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* prcmu_abb_read() - Read register value(s) from the ABB.
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* @slave: The I2C slave address.
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* @reg: The (start) register address.
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* @value: The read out value(s).
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* @size: The number of registers to read.
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*
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* Reads register value(s) from the ABB.
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* @size has to be 1 for the current firmware version.
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*/
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int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
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{
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int r;
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if (size != 1)
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return -EINVAL;
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r = mutex_lock_interruptible(&mb5_transfer.lock);
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if (r)
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return r;
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
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cpu_relax();
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writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
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writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
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writeb(reg, REQ_MB5_I2C_REG);
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writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
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if (!wait_for_completion_timeout(&mb5_transfer.work,
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msecs_to_jiffies(500))) {
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pr_err("prcmu: prcmu_abb_read timed out.\n");
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r = -EIO;
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goto unlock_and_return;
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}
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r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
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if (!r)
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*value = mb5_transfer.ack.value;
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unlock_and_return:
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mutex_unlock(&mb5_transfer.lock);
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return r;
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}
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EXPORT_SYMBOL(prcmu_abb_read);
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/**
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* prcmu_abb_write() - Write register value(s) to the ABB.
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* @slave: The I2C slave address.
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* @reg: The (start) register address.
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* @value: The value(s) to write.
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* @size: The number of registers to write.
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*
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* Reads register value(s) from the ABB.
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* @size has to be 1 for the current firmware version.
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*/
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int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
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{
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int r;
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if (size != 1)
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return -EINVAL;
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r = mutex_lock_interruptible(&mb5_transfer.lock);
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if (r)
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return r;
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
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cpu_relax();
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writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
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writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
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writeb(reg, REQ_MB5_I2C_REG);
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writeb(*value, REQ_MB5_I2C_VAL);
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writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
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if (!wait_for_completion_timeout(&mb5_transfer.work,
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msecs_to_jiffies(500))) {
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pr_err("prcmu: prcmu_abb_write timed out.\n");
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r = -EIO;
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goto unlock_and_return;
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}
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r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
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unlock_and_return:
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mutex_unlock(&mb5_transfer.lock);
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return r;
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}
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EXPORT_SYMBOL(prcmu_abb_write);
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static void read_mailbox_0(void)
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{
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writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_1(void)
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{
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writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_2(void)
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{
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writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_3(void)
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{
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writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_4(void)
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{
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writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_5(void)
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{
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mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
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mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
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complete(&mb5_transfer.work);
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writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_6(void)
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{
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writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
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}
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static void read_mailbox_7(void)
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{
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writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
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}
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static void (* const read_mailbox[NUM_MBOX])(void) = {
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read_mailbox_0,
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read_mailbox_1,
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read_mailbox_2,
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read_mailbox_3,
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read_mailbox_4,
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read_mailbox_5,
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read_mailbox_6,
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read_mailbox_7
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};
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static irqreturn_t prcmu_irq_handler(int irq, void *data)
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{
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u32 bits;
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u8 n;
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bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
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if (unlikely(!bits))
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return IRQ_NONE;
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for (n = 0; bits; n++) {
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if (bits & MBOX_BIT(n)) {
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bits -= MBOX_BIT(n);
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read_mailbox[n]();
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}
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}
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return IRQ_HANDLED;
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}
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static int __init prcmu_init(void)
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{
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mutex_init(&mb5_transfer.lock);
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init_completion(&mb5_transfer.work);
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/* Clean up the mailbox interrupts after pre-kernel code. */
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writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
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return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL);
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}
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arch_initcall(prcmu_init);
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