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drm fixes for 6.1-rc2
core: - fix connector DDC pointer - fix buffer overflow in format_helper_test amdgpu: - Mode2 reset fixes for Sienna Cichlid - Revert broken fan speed sensor fix - SMU 13.x fixes - GC 11.x fixes - RAS fixes - SR-IOV fixes - Fix BO move breakage on SI - Misc compiler fixes - Fix gfx9 APU regression caused by PCI AER fix vc4: - HDMI fixes panfrost: - compiler fixes -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmNR6GUACgkQDHTzWXnE hr5wRhAAhnD6ZlzhQlGQJVWNHfRTOG7n2RBnUKeDHOZ9ndlyasUbf/2Y/On9n7XO QiTWCFbKfMxaPV+5QdECxZbm4s+KjQihh6l1eqLBMsocbZq5eopkpgJ7j9N16jDH NlLrquUb/F++67Xr7OvqcdDfZlPDiKr4p6slvcdtRiFUG4C6a8ZiFV0U0kBsJXHn Qa7hunK31T3qPnUp3IDvR8bpRTdn1wproSd1S/+6LqtFZoQuayx1t53w/yhJhc7g XiwJJ+swFH0LHMO8SvkH6msY36T6vDZoUJMInBw/32Dk8MrMwtJvCic1hAHLIt9i ZHhCEoCxDSScjhqoO1Hc8emDo56I4gkwwxuEDw0m3EipJbDakYKDloULAu960ndE guJgqLfPd1Yf1M+I/Z9B4+WGDKmpfWLYktw5Q7Mzmz/GIL8K5ArgtdNz/RqGdSaI U3LvHG4cXVQnnd+k9PJxoD2wCL1tgrTugPks66KQwQ1fHWi21BNGIc9Og88taSAj HtPRcCxZQjnnxijxnPNXboYrFpnVgfvRvwMwZdhwmM3ieWgcSTghnKXoiTCvwv85 +lBdEP5OlRwc6phwZMJ/VPM9dLkekG9ltShYN8rx5AY1TXdzY7U2TzoysWxqSu6o bdsRY77+SUreqR29VM01R9Ta+uDtMfkRsgWRgGPCVJcm0ltlG1o= =cF5c -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2022-10-21' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "Usual fixes for the week. The amdgpu contains fixes for two regressions, one reported in response to rc1 which broke on SI GPUs, and one gfx9 APU regression. Otherwise it's mostly fixes for new IP, and some GPU reset fixes. vc4 is just HDMI fixes, and panfrost has some mnor types fixes. Core: - fix connector DDC pointer - fix buffer overflow in format_helper_test amdgpu: - Mode2 reset fixes for Sienna Cichlid - Revert broken fan speed sensor fix - SMU 13.x fixes - GC 11.x fixes - RAS fixes - SR-IOV fixes - Fix BO move breakage on SI - Misc compiler fixes - Fix gfx9 APU regression caused by PCI AER fix vc4: - HDMI fixes panfrost: - compiler fixes" * tag 'drm-fixes-2022-10-21' of git://anongit.freedesktop.org/drm/drm: (35 commits) drm/amdgpu: fix sdma doorbell init ordering on APUs drm/panfrost: replace endian-specific types with native ones drm/panfrost: Remove type name from internal structs drm/connector: Set DDC pointer in drmm_connector_init drm: tests: Fix a buffer overflow in format_helper_test drm/amdgpu: use DRM_SCHED_FENCE_DONT_PIPELINE for VM updates drm/sched: add DRM_SCHED_FENCE_DONT_PIPELINE flag drm/amdgpu: Fix for BO move issue drm/amdgpu: dequeue mes scheduler during fini drm/amd/pm: enable thermal alert on smu_v13_0_10 drm/amdgpu: Program GC registers through RLCG interface in gfx_v11/gmc_v11 drm/amdkfd: Fix type of reset_type parameter in hqd_destroy() callback drm/amd/display: Increase frame size limit for display_mode_vba_util_32.o drm/amd/pm: add SMU IP v13.0.4 IF version define to V7 drm/amd/pm: update SMU IP v13.0.4 driver interface version drm/amd/pm: Init pm_attr_list when dpm is disabled drm/amd/pm: disable cstate feature for gpu reset scenario drm/amd/pm: fulfill SMU13.0.7 cstate control interface drm/amd/pm: fulfill SMU13.0.0 cstate control interface drm/amdgpu: Add sriov vf ras support in amdgpu_ras_asic_supported ...
This commit is contained in:
Linus Torvalds
commit
e35184f321
@ -274,9 +274,6 @@ extern int amdgpu_vcnfw_log;
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#define AMDGPU_RESET_VCE (1 << 13)
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#define AMDGPU_RESET_VCE1 (1 << 14)
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#define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0)
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#define AMDGPU_RESET_LEVEL_MODE2 (1 << 1)
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/* max cursor sizes (in pixels) */
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#define CIK_CURSOR_WIDTH 128
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#define CIK_CURSOR_HEIGHT 128
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@ -1065,7 +1062,6 @@ struct amdgpu_device {
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struct work_struct reset_work;
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uint32_t amdgpu_reset_level_mask;
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bool job_hang;
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};
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@ -134,7 +134,6 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work)
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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amdgpu_device_gpu_recover(adev, NULL, &reset_context);
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}
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@ -111,7 +111,7 @@ static int init_interrupts_v11(struct amdgpu_device *adev, uint32_t pipe_id)
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lock_srbm(adev, mec, pipe, 0, 0);
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WREG32(SOC15_REG_OFFSET(GC, 0, regCPC_INT_CNTL),
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WREG32_SOC15(GC, 0, regCPC_INT_CNTL,
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CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
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CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
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@ -1954,8 +1954,6 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
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return PTR_ERR(ent);
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}
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debugfs_create_u32("amdgpu_reset_level", 0600, root, &adev->amdgpu_reset_level_mask);
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/* Register debugfs entries for amdgpu_ttm */
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amdgpu_ttm_debugfs_init(adev);
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amdgpu_debugfs_pm_init(adev);
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@ -2928,6 +2928,14 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
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amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
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amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
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/*
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* Per PMFW team's suggestion, driver needs to handle gfxoff
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* and df cstate features disablement for gpu reset(e.g. Mode1Reset)
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* scenario. Add the missing df cstate disablement here.
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*/
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if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
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dev_warn(adev->dev, "Failed to disallow df cstate");
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for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
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if (!adev->ip_blocks[i].status.valid)
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continue;
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@ -5210,7 +5218,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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reset_context->job = job;
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reset_context->hive = hive;
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/*
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* Build list of devices to reset.
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* In case we are in XGMI hive mode, resort the device list
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@ -5337,11 +5344,8 @@ retry: /* Rest of adevs pre asic reset from XGMI hive. */
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amdgpu_ras_resume(adev);
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} else {
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r = amdgpu_do_asic_reset(device_list_handle, reset_context);
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if (r && r == -EAGAIN) {
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set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags);
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adev->asic_reset_res = 0;
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if (r && r == -EAGAIN)
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goto retry;
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}
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if (!r && gpu_reset_for_dev_remove)
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goto recover_end;
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@ -5777,7 +5781,6 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
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reset_context.reset_req_dev = adev;
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set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
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set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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adev->no_hw_access = true;
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r = amdgpu_device_pre_asic_reset(adev, &reset_context);
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@ -72,7 +72,6 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
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if (r)
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@ -1950,7 +1950,6 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
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reset_context.method = AMD_RESET_METHOD_NONE;
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reset_context.reset_req_dev = adev;
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clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
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clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
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amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
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}
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@ -2268,6 +2267,25 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
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static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
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{
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if (amdgpu_sriov_vf(adev)) {
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switch (adev->ip_versions[MP0_HWIP][0]) {
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case IP_VERSION(13, 0, 2):
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return true;
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default:
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return false;
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}
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}
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if (adev->asic_type == CHIP_IP_DISCOVERY) {
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switch (adev->ip_versions[MP0_HWIP][0]) {
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case IP_VERSION(13, 0, 0):
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case IP_VERSION(13, 0, 10):
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return true;
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default:
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return false;
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}
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}
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return adev->asic_type == CHIP_VEGA10 ||
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adev->asic_type == CHIP_VEGA20 ||
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adev->asic_type == CHIP_ARCTURUS ||
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@ -2311,11 +2329,6 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
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!amdgpu_ras_asic_supported(adev))
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return;
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/* If driver run on sriov guest side, only enable ras for aldebaran */
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if (amdgpu_sriov_vf(adev) &&
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adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2))
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return;
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if (!adev->gmc.xgmi.connected_to_cpu) {
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if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
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dev_info(adev->dev, "MEM ECC is active.\n");
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@ -37,8 +37,6 @@ int amdgpu_reset_init(struct amdgpu_device *adev)
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{
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int ret = 0;
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adev->amdgpu_reset_level_mask = 0x1;
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switch (adev->ip_versions[MP1_HWIP][0]) {
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case IP_VERSION(13, 0, 2):
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ret = aldebaran_reset_init(adev);
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@ -76,12 +74,6 @@ int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
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{
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struct amdgpu_reset_handler *reset_handler = NULL;
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if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
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return -ENOSYS;
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if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags))
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return -ENOSYS;
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if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
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reset_handler = adev->reset_cntl->get_reset_handler(
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adev->reset_cntl, reset_context);
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@ -98,12 +90,6 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
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int ret;
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struct amdgpu_reset_handler *reset_handler = NULL;
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if (!(adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_MODE2))
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return -ENOSYS;
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if (test_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags))
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return -ENOSYS;
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if (adev->reset_cntl)
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reset_handler = adev->reset_cntl->get_reset_handler(
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adev->reset_cntl, reset_context);
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@ -30,8 +30,7 @@ enum AMDGPU_RESET_FLAGS {
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AMDGPU_NEED_FULL_RESET = 0,
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AMDGPU_SKIP_HW_RESET = 1,
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AMDGPU_SKIP_MODE2_RESET = 2,
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AMDGPU_RESET_FOR_DEVICE_REMOVE = 3,
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AMDGPU_RESET_FOR_DEVICE_REMOVE = 2,
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};
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struct amdgpu_reset_context {
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@ -405,9 +405,6 @@ bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
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{
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ktime_t deadline = ktime_add_us(ktime_get(), 10000);
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if (!(ring->adev->amdgpu_reset_level_mask & AMDGPU_RESET_LEVEL_SOFT_RECOVERY))
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return false;
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if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
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return false;
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@ -439,6 +439,9 @@ static bool amdgpu_mem_visible(struct amdgpu_device *adev,
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while (cursor.remaining) {
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amdgpu_res_next(&cursor, cursor.size);
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if (!cursor.remaining)
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break;
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/* ttm_resource_ioremap only supports contiguous memory */
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if (end != cursor.start)
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return false;
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@ -726,6 +726,12 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
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adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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}
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if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
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/* VF MMIO access (except mailbox range) from CPU
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* will be blocked during sriov runtime
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*/
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adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;
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/* we have the ability to check now */
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if (amdgpu_sriov_vf(adev)) {
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switch (adev->asic_type) {
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@ -31,6 +31,7 @@
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#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
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#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
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#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
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#define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
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/* flags for indirect register access path supported by rlcg for sriov */
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#define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
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@ -297,6 +298,9 @@ struct amdgpu_video_codec_info;
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#define amdgpu_passthrough(adev) \
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((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
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#define amdgpu_sriov_vf_mmio_access_protection(adev) \
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((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
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static inline bool is_virtual_machine(void)
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{
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#if defined(CONFIG_X86)
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@ -2338,7 +2338,11 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
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*/
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#ifdef CONFIG_X86_64
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if (amdgpu_vm_update_mode == -1) {
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if (amdgpu_gmc_vram_full_visible(&adev->gmc))
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/* For asic with VF MMIO access protection
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* avoid using CPU for VM table updates
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*/
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if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
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!amdgpu_sriov_vf_mmio_access_protection(adev))
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adev->vm_manager.vm_update_mode =
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AMDGPU_VM_USE_CPU_FOR_COMPUTE;
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else
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@ -116,8 +116,15 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p,
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DMA_RESV_USAGE_BOOKKEEP);
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}
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if (fence && !p->immediate)
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if (fence && !p->immediate) {
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/*
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* Most hw generations now have a separate queue for page table
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* updates, but when the queue is shared with userspace we need
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* the extra CPU round trip to correctly flush the TLB.
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*/
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set_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &f->flags);
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swap(*fence, f);
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}
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dma_fence_put(f);
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return 0;
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@ -1571,7 +1571,7 @@ static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
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WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
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/* Enable trap for each kfd vmid. */
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data = RREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL));
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data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
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data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
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}
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soc21_grbm_select(adev, 0, 0, 0, 0);
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@ -5076,6 +5076,7 @@ static int gfx_v11_0_set_clockgating_state(void *handle,
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case IP_VERSION(11, 0, 0):
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case IP_VERSION(11, 0, 1):
|
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case IP_VERSION(11, 0, 2):
|
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case IP_VERSION(11, 0, 3):
|
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gfx_v11_0_update_gfx_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
|
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break;
|
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|
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@ -186,6 +186,10 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
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/* Use register 17 for GART */
|
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const unsigned eng = 17;
|
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unsigned int i;
|
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unsigned char hub_ip = 0;
|
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|
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hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
|
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GC_HWIP : MMHUB_HWIP;
|
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|
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spin_lock(&adev->gmc.invalidate_lock);
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/*
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@ -199,8 +203,8 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
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if (use_semaphore) {
|
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for (i = 0; i < adev->usec_timeout; i++) {
|
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/* a read return value of 1 means semaphore acuqire */
|
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tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
|
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hub->eng_distance * eng);
|
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tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
|
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hub->eng_distance * eng, hub_ip);
|
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if (tmp & 0x1)
|
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break;
|
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udelay(1);
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@ -210,12 +214,12 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
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DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
|
||||
}
|
||||
|
||||
WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
|
||||
WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip);
|
||||
|
||||
/* Wait for ACK with a delay.*/
|
||||
for (i = 0; i < adev->usec_timeout; i++) {
|
||||
tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
|
||||
hub->eng_distance * eng);
|
||||
tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
|
||||
hub->eng_distance * eng, hub_ip);
|
||||
tmp &= 1 << vmid;
|
||||
if (tmp)
|
||||
break;
|
||||
@ -229,8 +233,8 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
|
||||
* add semaphore release after invalidation,
|
||||
* write with 0 means semaphore release
|
||||
*/
|
||||
WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
|
||||
hub->eng_distance * eng, 0);
|
||||
WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
|
||||
hub->eng_distance * eng, 0, hub_ip);
|
||||
|
||||
/* Issue additional private vm invalidation to MMHUB */
|
||||
if ((vmhub != AMDGPU_GFXHUB_0) &&
|
||||
|
||||
@ -1156,6 +1156,42 @@ static int mes_v11_0_sw_fini(void *handle)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t data;
|
||||
int i;
|
||||
|
||||
mutex_lock(&adev->srbm_mutex);
|
||||
soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
|
||||
|
||||
/* disable the queue if it's active */
|
||||
if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
|
||||
WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
|
||||
for (i = 0; i < adev->usec_timeout; i++) {
|
||||
if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
}
|
||||
data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
|
||||
data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
|
||||
DOORBELL_EN, 0);
|
||||
data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
|
||||
DOORBELL_HIT, 1);
|
||||
WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
|
||||
|
||||
WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
|
||||
|
||||
WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
|
||||
WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
|
||||
WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
|
||||
|
||||
soc21_grbm_select(adev, 0, 0, 0, 0);
|
||||
mutex_unlock(&adev->srbm_mutex);
|
||||
|
||||
adev->mes.ring.sched.ready = false;
|
||||
}
|
||||
|
||||
static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
|
||||
{
|
||||
uint32_t tmp;
|
||||
@ -1207,6 +1243,9 @@ failure:
|
||||
|
||||
static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
|
||||
{
|
||||
if (adev->mes.ring.sched.ready)
|
||||
mes_v11_0_kiq_dequeue_sched(adev);
|
||||
|
||||
mes_v11_0_enable(adev, false);
|
||||
return 0;
|
||||
}
|
||||
@ -1262,9 +1301,6 @@ failure:
|
||||
|
||||
static int mes_v11_0_hw_fini(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
adev->mes.ring.sched.ready = false;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1296,7 +1332,8 @@ static int mes_v11_0_late_init(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
if (!amdgpu_in_reset(adev))
|
||||
if (!amdgpu_in_reset(adev) &&
|
||||
(adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
|
||||
amdgpu_mes_self_test(adev);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -290,7 +290,6 @@ flr_done:
|
||||
reset_context.method = AMD_RESET_METHOD_NONE;
|
||||
reset_context.reset_req_dev = adev;
|
||||
clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
|
||||
clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
|
||||
|
||||
amdgpu_device_gpu_recover(adev, NULL, &reset_context);
|
||||
}
|
||||
|
||||
@ -317,7 +317,6 @@ flr_done:
|
||||
reset_context.method = AMD_RESET_METHOD_NONE;
|
||||
reset_context.reset_req_dev = adev;
|
||||
clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
|
||||
clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
|
||||
|
||||
amdgpu_device_gpu_recover(adev, NULL, &reset_context);
|
||||
}
|
||||
|
||||
@ -529,7 +529,6 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work)
|
||||
reset_context.method = AMD_RESET_METHOD_NONE;
|
||||
reset_context.reset_req_dev = adev;
|
||||
clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
|
||||
clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);
|
||||
|
||||
amdgpu_device_gpu_recover(adev, NULL, &reset_context);
|
||||
}
|
||||
|
||||
@ -1417,11 +1417,6 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
|
||||
WREG32_SDMA(i, mmSDMA0_CNTL, temp);
|
||||
|
||||
if (!amdgpu_sriov_vf(adev)) {
|
||||
ring = &adev->sdma.instance[i].ring;
|
||||
adev->nbio.funcs->sdma_doorbell_range(adev, i,
|
||||
ring->use_doorbell, ring->doorbell_index,
|
||||
adev->doorbell_index.sdma_doorbell_range);
|
||||
|
||||
/* unhalt engine */
|
||||
temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
|
||||
temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
|
||||
|
||||
@ -31,12 +31,23 @@
|
||||
#include "amdgpu_psp.h"
|
||||
#include "amdgpu_xgmi.h"
|
||||
|
||||
static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
|
||||
{
|
||||
#if 0
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
|
||||
|
||||
if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7) &&
|
||||
adev->pm.fw_version >= 0x3a5500 && !amdgpu_sriov_vf(adev))
|
||||
return true;
|
||||
#endif
|
||||
return false;
|
||||
}
|
||||
|
||||
static struct amdgpu_reset_handler *
|
||||
sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
|
||||
struct amdgpu_reset_context *reset_context)
|
||||
{
|
||||
struct amdgpu_reset_handler *handler;
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
|
||||
|
||||
if (reset_context->method != AMD_RESET_METHOD_NONE) {
|
||||
list_for_each_entry(handler, &reset_ctl->reset_handlers,
|
||||
@ -44,15 +55,13 @@ sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
|
||||
if (handler->reset_method == reset_context->method)
|
||||
return handler;
|
||||
}
|
||||
} else {
|
||||
list_for_each_entry(handler, &reset_ctl->reset_handlers,
|
||||
}
|
||||
|
||||
if (sienna_cichlid_is_mode2_default(reset_ctl)) {
|
||||
list_for_each_entry (handler, &reset_ctl->reset_handlers,
|
||||
handler_list) {
|
||||
if (handler->reset_method == AMD_RESET_METHOD_MODE2 &&
|
||||
adev->pm.fw_version >= 0x3a5500 &&
|
||||
!amdgpu_sriov_vf(adev)) {
|
||||
reset_context->method = AMD_RESET_METHOD_MODE2;
|
||||
if (handler->reset_method == AMD_RESET_METHOD_MODE2)
|
||||
return handler;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1211,6 +1211,20 @@ static int soc15_common_sw_fini(void *handle)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* sdma doorbell range is programed by hypervisor */
|
||||
if (!amdgpu_sriov_vf(adev)) {
|
||||
for (i = 0; i < adev->sdma.num_instances; i++) {
|
||||
adev->nbio.funcs->sdma_doorbell_range(adev, i,
|
||||
true, adev->doorbell_index.sdma_engine[i] << 1,
|
||||
adev->doorbell_index.sdma_doorbell_range);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int soc15_common_hw_init(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
@ -1230,6 +1244,13 @@ static int soc15_common_hw_init(void *handle)
|
||||
|
||||
/* enable the doorbell aperture */
|
||||
soc15_enable_doorbell_aperture(adev, true);
|
||||
/* HW doorbell routing policy: doorbell writing not
|
||||
* in SDMA/IH/MM/ACV range will be routed to CP. So
|
||||
* we need to init SDMA doorbell range prior
|
||||
* to CP ip block init and ring test. IH already
|
||||
* happens before CP.
|
||||
*/
|
||||
soc15_sdma_doorbell_range_init(adev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -423,6 +423,7 @@ static bool soc21_need_full_reset(struct amdgpu_device *adev)
|
||||
case IP_VERSION(11, 0, 0):
|
||||
return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
|
||||
case IP_VERSION(11, 0, 2):
|
||||
case IP_VERSION(11, 0, 3):
|
||||
return false;
|
||||
default:
|
||||
return true;
|
||||
@ -636,7 +637,11 @@ static int soc21_common_early_init(void *handle)
|
||||
break;
|
||||
case IP_VERSION(11, 0, 3):
|
||||
adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
|
||||
AMD_CG_SUPPORT_JPEG_MGCG;
|
||||
AMD_CG_SUPPORT_JPEG_MGCG |
|
||||
AMD_CG_SUPPORT_GFX_CGCG |
|
||||
AMD_CG_SUPPORT_GFX_CGLS |
|
||||
AMD_CG_SUPPORT_REPEATER_FGCG |
|
||||
AMD_CG_SUPPORT_GFX_MGCG;
|
||||
adev->pg_flags = AMD_PG_SUPPORT_VCN |
|
||||
AMD_PG_SUPPORT_VCN_DPG |
|
||||
AMD_PG_SUPPORT_JPEG;
|
||||
|
||||
@ -77,7 +77,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/dcn32_fpu.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_ccflags) $(frame_warn_flag)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_ccflags) $(frame_warn_flag)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn321/dcn321_fpu.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags)
|
||||
CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags)
|
||||
|
||||
@ -262,8 +262,9 @@ struct kfd2kgd_calls {
|
||||
uint32_t queue_id);
|
||||
|
||||
int (*hqd_destroy)(struct amdgpu_device *adev, void *mqd,
|
||||
uint32_t reset_type, unsigned int timeout,
|
||||
uint32_t pipe_id, uint32_t queue_id);
|
||||
enum kfd_preempt_type reset_type,
|
||||
unsigned int timeout, uint32_t pipe_id,
|
||||
uint32_t queue_id);
|
||||
|
||||
bool (*hqd_sdma_is_occupied)(struct amdgpu_device *adev, void *mqd);
|
||||
|
||||
|
||||
@ -3362,11 +3362,11 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
|
||||
if (adev->pm.sysfs_initialized)
|
||||
return 0;
|
||||
|
||||
INIT_LIST_HEAD(&adev->pm.pm_attr_list);
|
||||
|
||||
if (adev->pm.dpm_enabled == 0)
|
||||
return 0;
|
||||
|
||||
INIT_LIST_HEAD(&adev->pm.pm_attr_list);
|
||||
|
||||
adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
|
||||
DRIVER_NAME, adev,
|
||||
hwmon_groups);
|
||||
|
||||
@ -67,21 +67,22 @@ int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
|
||||
int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
|
||||
uint32_t *speed)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
uint32_t duty100, duty;
|
||||
uint64_t tmp64;
|
||||
uint32_t current_rpm;
|
||||
uint32_t percent = 0;
|
||||
|
||||
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
|
||||
CG_FDO_CTRL1, FMAX_DUTY100);
|
||||
duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
|
||||
CG_THERMAL_STATUS, FDO_PWM_DUTY);
|
||||
if (hwmgr->thermal_controller.fanInfo.bNoFan)
|
||||
return 0;
|
||||
|
||||
if (!duty100)
|
||||
return -EINVAL;
|
||||
if (vega10_get_current_rpm(hwmgr, ¤t_rpm))
|
||||
return -1;
|
||||
|
||||
tmp64 = (uint64_t)duty * 255;
|
||||
do_div(tmp64, duty100);
|
||||
*speed = MIN((uint32_t)tmp64, 255);
|
||||
if (hwmgr->thermal_controller.
|
||||
advanceFanControlParameters.usMaxFanRPM != 0)
|
||||
percent = current_rpm * 255 /
|
||||
hwmgr->thermal_controller.
|
||||
advanceFanControlParameters.usMaxFanRPM;
|
||||
|
||||
*speed = MIN(percent, 255);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1314,8 +1314,8 @@ static int smu_smc_hw_setup(struct smu_context *smu)
|
||||
|
||||
ret = smu_enable_thermal_alert(smu);
|
||||
if (ret) {
|
||||
dev_err(adev->dev, "Failed to enable thermal alert!\n");
|
||||
return ret;
|
||||
dev_err(adev->dev, "Failed to enable thermal alert!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = smu_notify_display_change(smu);
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
// *** IMPORTANT ***
|
||||
// SMU TEAM: Always increment the interface version if
|
||||
// any structure is changed in this file
|
||||
#define PMFW_DRIVER_IF_VERSION 5
|
||||
#define PMFW_DRIVER_IF_VERSION 7
|
||||
|
||||
typedef struct {
|
||||
int32_t value;
|
||||
@ -163,8 +163,8 @@ typedef struct {
|
||||
uint16_t DclkFrequency; //[MHz]
|
||||
uint16_t MemclkFrequency; //[MHz]
|
||||
uint16_t spare; //[centi]
|
||||
uint16_t UvdActivity; //[centi]
|
||||
uint16_t GfxActivity; //[centi]
|
||||
uint16_t UvdActivity; //[centi]
|
||||
|
||||
uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
|
||||
uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC
|
||||
@ -199,6 +199,19 @@ typedef struct {
|
||||
uint16_t DeviceState;
|
||||
uint16_t CurTemp; //[centi-Celsius]
|
||||
uint16_t spare2;
|
||||
|
||||
uint16_t AverageGfxclkFrequency;
|
||||
uint16_t AverageFclkFrequency;
|
||||
uint16_t AverageGfxActivity;
|
||||
uint16_t AverageSocclkFrequency;
|
||||
uint16_t AverageVclkFrequency;
|
||||
uint16_t AverageVcnActivity;
|
||||
uint16_t AverageDRAMReads; //Filtered DF Bandwidth::DRAM Reads
|
||||
uint16_t AverageDRAMWrites; //Filtered DF Bandwidth::DRAM Writes
|
||||
uint16_t AverageSocketPower; //Filtered value of CurrentSocketPower
|
||||
uint16_t AverageCorePower; //Filtered of [sum of CorePower[8]])
|
||||
uint16_t AverageCoreC0Residency[8]; //Filtered of [average C0 residency % per core]
|
||||
uint32_t MetricsCounter; //Counts the # of metrics table parameter reads per update to the metrics table, i.e. if the metrics table update happens every 1 second, this value could be up to 1000 if the smu collected metrics data every cycle, or as low as 0 if the smu was asleep the whole time. Reset to 0 after writing.
|
||||
} SmuMetrics_t;
|
||||
|
||||
typedef struct {
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
#define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
|
||||
#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04
|
||||
#define SMU13_DRIVER_IF_VERSION_ALDE 0x08
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x05
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x07
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x30
|
||||
#define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
|
||||
|
||||
@ -2242,9 +2242,17 @@ static void arcturus_get_unique_id(struct smu_context *smu)
|
||||
static int arcturus_set_df_cstate(struct smu_context *smu,
|
||||
enum pp_df_cstate state)
|
||||
{
|
||||
struct amdgpu_device *adev = smu->adev;
|
||||
uint32_t smu_version;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Arcturus does not need the cstate disablement
|
||||
* prerequisite for gpu reset.
|
||||
*/
|
||||
if (amdgpu_in_reset(adev) || adev->in_suspend)
|
||||
return 0;
|
||||
|
||||
ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
|
||||
if (ret) {
|
||||
dev_err(smu->adev->dev, "Failed to get smu version!\n");
|
||||
|
||||
@ -1640,6 +1640,15 @@ static bool aldebaran_is_baco_supported(struct smu_context *smu)
|
||||
static int aldebaran_set_df_cstate(struct smu_context *smu,
|
||||
enum pp_df_cstate state)
|
||||
{
|
||||
struct amdgpu_device *adev = smu->adev;
|
||||
|
||||
/*
|
||||
* Aldebaran does not need the cstate disablement
|
||||
* prerequisite for gpu reset.
|
||||
*/
|
||||
if (amdgpu_in_reset(adev) || adev->in_suspend)
|
||||
return 0;
|
||||
|
||||
return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
|
||||
}
|
||||
|
||||
|
||||
@ -211,7 +211,8 @@ int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
|
||||
return 0;
|
||||
|
||||
if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) ||
|
||||
(adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)))
|
||||
(adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) ||
|
||||
(adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)))
|
||||
return 0;
|
||||
|
||||
/* override pptable_id from driver parameter */
|
||||
@ -454,9 +455,6 @@ int smu_v13_0_setup_pptable(struct smu_context *smu)
|
||||
dev_info(adev->dev, "override pptable id %d\n", pptable_id);
|
||||
} else {
|
||||
pptable_id = smu->smu_table.boot_values.pp_table_id;
|
||||
|
||||
if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))
|
||||
pptable_id = 6666;
|
||||
}
|
||||
|
||||
/* force using vbios pptable in sriov mode */
|
||||
|
||||
@ -119,6 +119,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
|
||||
MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
|
||||
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
|
||||
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
|
||||
MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
|
||||
};
|
||||
|
||||
static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
|
||||
@ -1753,6 +1754,15 @@ static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
|
||||
enum pp_df_cstate state)
|
||||
{
|
||||
return smu_cmn_send_smc_msg_with_param(smu,
|
||||
SMU_MSG_DFCstateControl,
|
||||
state,
|
||||
NULL);
|
||||
}
|
||||
|
||||
static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
|
||||
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
|
||||
.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
|
||||
@ -1822,6 +1832,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
|
||||
.mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
|
||||
.mode1_reset = smu_v13_0_mode1_reset,
|
||||
.set_mp1_state = smu_v13_0_0_set_mp1_state,
|
||||
.set_df_cstate = smu_v13_0_0_set_df_cstate,
|
||||
};
|
||||
|
||||
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
|
||||
|
||||
@ -121,6 +121,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
|
||||
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
|
||||
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
|
||||
MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
|
||||
MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
|
||||
};
|
||||
|
||||
static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
|
||||
@ -1587,6 +1588,16 @@ static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
|
||||
enum pp_df_cstate state)
|
||||
{
|
||||
return smu_cmn_send_smc_msg_with_param(smu,
|
||||
SMU_MSG_DFCstateControl,
|
||||
state,
|
||||
NULL);
|
||||
}
|
||||
|
||||
static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
|
||||
.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
|
||||
.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
|
||||
@ -1649,6 +1660,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
|
||||
.mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
|
||||
.mode1_reset = smu_v13_0_mode1_reset,
|
||||
.set_mp1_state = smu_v13_0_7_set_mp1_state,
|
||||
.set_df_cstate = smu_v13_0_7_set_df_cstate,
|
||||
};
|
||||
|
||||
void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
|
||||
|
||||
@ -435,7 +435,7 @@ int drmm_connector_init(struct drm_device *dev,
|
||||
if (drm_WARN_ON(dev, funcs && funcs->destroy))
|
||||
return -EINVAL;
|
||||
|
||||
ret = __drm_connector_init(dev, connector, funcs, connector_type, NULL);
|
||||
ret = __drm_connector_init(dev, connector, funcs, connector_type, ddc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
@ -63,13 +63,13 @@ static void panfrost_core_dump_header(struct panfrost_dump_iterator *iter,
|
||||
{
|
||||
struct panfrost_dump_object_header *hdr = iter->hdr;
|
||||
|
||||
hdr->magic = cpu_to_le32(PANFROSTDUMP_MAGIC);
|
||||
hdr->type = cpu_to_le32(type);
|
||||
hdr->file_offset = cpu_to_le32(iter->data - iter->start);
|
||||
hdr->file_size = cpu_to_le32(data_end - iter->data);
|
||||
hdr->magic = PANFROSTDUMP_MAGIC;
|
||||
hdr->type = type;
|
||||
hdr->file_offset = iter->data - iter->start;
|
||||
hdr->file_size = data_end - iter->data;
|
||||
|
||||
iter->hdr++;
|
||||
iter->data += le32_to_cpu(hdr->file_size);
|
||||
iter->data += hdr->file_size;
|
||||
}
|
||||
|
||||
static void
|
||||
@ -93,8 +93,8 @@ panfrost_core_dump_registers(struct panfrost_dump_iterator *iter,
|
||||
|
||||
reg = panfrost_dump_registers[i] + js_as_offset;
|
||||
|
||||
dumpreg->reg = cpu_to_le32(reg);
|
||||
dumpreg->value = cpu_to_le32(gpu_read(pfdev, reg));
|
||||
dumpreg->reg = reg;
|
||||
dumpreg->value = gpu_read(pfdev, reg);
|
||||
}
|
||||
|
||||
panfrost_core_dump_header(iter, PANFROSTDUMP_BUF_REG, dumpreg);
|
||||
@ -106,7 +106,7 @@ void panfrost_core_dump(struct panfrost_job *job)
|
||||
struct panfrost_dump_iterator iter;
|
||||
struct drm_gem_object *dbo;
|
||||
unsigned int n_obj, n_bomap_pages;
|
||||
__le64 *bomap, *bomap_start;
|
||||
u64 *bomap, *bomap_start;
|
||||
size_t file_size;
|
||||
u32 as_nr;
|
||||
int slot;
|
||||
@ -177,11 +177,11 @@ void panfrost_core_dump(struct panfrost_job *job)
|
||||
* For now, we write the job identifier in the register dump header,
|
||||
* so that we can decode the entire dump later with pandecode
|
||||
*/
|
||||
iter.hdr->reghdr.jc = cpu_to_le64(job->jc);
|
||||
iter.hdr->reghdr.major = cpu_to_le32(PANFROSTDUMP_MAJOR);
|
||||
iter.hdr->reghdr.minor = cpu_to_le32(PANFROSTDUMP_MINOR);
|
||||
iter.hdr->reghdr.gpu_id = cpu_to_le32(pfdev->features.id);
|
||||
iter.hdr->reghdr.nbos = cpu_to_le64(job->bo_count);
|
||||
iter.hdr->reghdr.jc = job->jc;
|
||||
iter.hdr->reghdr.major = PANFROSTDUMP_MAJOR;
|
||||
iter.hdr->reghdr.minor = PANFROSTDUMP_MINOR;
|
||||
iter.hdr->reghdr.gpu_id = pfdev->features.id;
|
||||
iter.hdr->reghdr.nbos = job->bo_count;
|
||||
|
||||
panfrost_core_dump_registers(&iter, pfdev, as_nr, slot);
|
||||
|
||||
@ -218,27 +218,27 @@ void panfrost_core_dump(struct panfrost_job *job)
|
||||
|
||||
WARN_ON(!mapping->active);
|
||||
|
||||
iter.hdr->bomap.data[0] = cpu_to_le32((bomap - bomap_start));
|
||||
iter.hdr->bomap.data[0] = bomap - bomap_start;
|
||||
|
||||
for_each_sgtable_page(bo->base.sgt, &page_iter, 0) {
|
||||
struct page *page = sg_page_iter_page(&page_iter);
|
||||
|
||||
if (!IS_ERR(page)) {
|
||||
*bomap++ = cpu_to_le64(page_to_phys(page));
|
||||
*bomap++ = page_to_phys(page);
|
||||
} else {
|
||||
dev_err(pfdev->dev, "Panfrost Dump: wrong page\n");
|
||||
*bomap++ = ~cpu_to_le64(0);
|
||||
*bomap++ = 0;
|
||||
}
|
||||
}
|
||||
|
||||
iter.hdr->bomap.iova = cpu_to_le64(mapping->mmnode.start << PAGE_SHIFT);
|
||||
iter.hdr->bomap.iova = mapping->mmnode.start << PAGE_SHIFT;
|
||||
|
||||
vaddr = map.vaddr;
|
||||
memcpy(iter.data, vaddr, bo->base.base.size);
|
||||
|
||||
drm_gem_shmem_vunmap(&bo->base, &map);
|
||||
|
||||
iter.hdr->bomap.valid = cpu_to_le32(1);
|
||||
iter.hdr->bomap.valid = 1;
|
||||
|
||||
dump_header: panfrost_core_dump_header(&iter, PANFROSTDUMP_BUF_BO, iter.data +
|
||||
bo->base.base.size);
|
||||
|
||||
@ -385,7 +385,8 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity)
|
||||
}
|
||||
|
||||
s_fence = to_drm_sched_fence(fence);
|
||||
if (s_fence && s_fence->sched == sched) {
|
||||
if (s_fence && s_fence->sched == sched &&
|
||||
!test_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &fence->flags)) {
|
||||
|
||||
/*
|
||||
* Fence is from the same scheduler, only need to wait for
|
||||
|
||||
@ -438,7 +438,7 @@ static void drm_test_fb_xrgb8888_to_xrgb2101010(struct kunit *test)
|
||||
iosys_map_set_vaddr(&src, xrgb8888);
|
||||
|
||||
drm_fb_xrgb8888_to_xrgb2101010(&dst, &result->dst_pitch, &src, &fb, ¶ms->clip);
|
||||
buf = le32buf_to_cpu(test, buf, TEST_BUF_SIZE);
|
||||
buf = le32buf_to_cpu(test, buf, dst_size / sizeof(u32));
|
||||
KUNIT_EXPECT_EQ(test, memcmp(buf, result->expected, dst_size), 0);
|
||||
}
|
||||
|
||||
|
||||
@ -490,6 +490,7 @@ module_init(vc4_drm_register);
|
||||
module_exit(vc4_drm_unregister);
|
||||
|
||||
MODULE_ALIAS("platform:vc4-drm");
|
||||
MODULE_SOFTDEP("pre: snd-soc-hdmi-codec");
|
||||
MODULE_DESCRIPTION("Broadcom VC4 DRM Driver");
|
||||
MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
@ -3318,12 +3318,37 @@ static int vc4_hdmi_runtime_resume(struct device *dev)
|
||||
struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
|
||||
unsigned long __maybe_unused flags;
|
||||
u32 __maybe_unused value;
|
||||
unsigned long rate;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* The HSM clock is in the HDMI power domain, so we need to set
|
||||
* its frequency while the power domain is active so that it
|
||||
* keeps its rate.
|
||||
*/
|
||||
ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Whenever the RaspberryPi boots without an HDMI monitor
|
||||
* plugged in, the firmware won't have initialized the HSM clock
|
||||
* rate and it will be reported as 0.
|
||||
*
|
||||
* If we try to access a register of the controller in such a
|
||||
* case, it will lead to a silent CPU stall. Let's make sure we
|
||||
* prevent such a case.
|
||||
*/
|
||||
rate = clk_get_rate(vc4_hdmi->hsm_clock);
|
||||
if (!rate) {
|
||||
ret = -EINVAL;
|
||||
goto err_disable_clk;
|
||||
}
|
||||
|
||||
if (vc4_hdmi->variant->reset)
|
||||
vc4_hdmi->variant->reset(vc4_hdmi);
|
||||
|
||||
@ -3345,6 +3370,10 @@ static int vc4_hdmi_runtime_resume(struct device *dev)
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
||||
err_disable_clk:
|
||||
clk_disable_unprepare(vc4_hdmi->hsm_clock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void vc4_hdmi_put_ddc_device(void *ptr)
|
||||
|
||||
@ -32,6 +32,15 @@
|
||||
|
||||
#define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
|
||||
|
||||
/**
|
||||
* DRM_SCHED_FENCE_DONT_PIPELINE - Prefent dependency pipelining
|
||||
*
|
||||
* Setting this flag on a scheduler fence prevents pipelining of jobs depending
|
||||
* on this fence. In other words we always insert a full CPU round trip before
|
||||
* dependen jobs are pushed to the hw queue.
|
||||
*/
|
||||
#define DRM_SCHED_FENCE_DONT_PIPELINE DMA_FENCE_FLAG_USER_BITS
|
||||
|
||||
struct drm_gem_object;
|
||||
|
||||
struct drm_gpu_scheduler;
|
||||
|
||||
@ -235,25 +235,29 @@ struct drm_panfrost_madvise {
|
||||
#define PANFROSTDUMP_BUF_BO (PANFROSTDUMP_BUF_BOMAP + 1)
|
||||
#define PANFROSTDUMP_BUF_TRAILER (PANFROSTDUMP_BUF_BO + 1)
|
||||
|
||||
/*
|
||||
* This structure is the native endianness of the dumping machine, tools can
|
||||
* detect the endianness by looking at the value in 'magic'.
|
||||
*/
|
||||
struct panfrost_dump_object_header {
|
||||
__le32 magic;
|
||||
__le32 type;
|
||||
__le32 file_size;
|
||||
__le32 file_offset;
|
||||
__u32 magic;
|
||||
__u32 type;
|
||||
__u32 file_size;
|
||||
__u32 file_offset;
|
||||
|
||||
union {
|
||||
struct pan_reg_hdr {
|
||||
__le64 jc;
|
||||
__le32 gpu_id;
|
||||
__le32 major;
|
||||
__le32 minor;
|
||||
__le64 nbos;
|
||||
struct {
|
||||
__u64 jc;
|
||||
__u32 gpu_id;
|
||||
__u32 major;
|
||||
__u32 minor;
|
||||
__u64 nbos;
|
||||
} reghdr;
|
||||
|
||||
struct pan_bomap_hdr {
|
||||
__le32 valid;
|
||||
__le64 iova;
|
||||
__le32 data[2];
|
||||
__u32 valid;
|
||||
__u64 iova;
|
||||
__u32 data[2];
|
||||
} bomap;
|
||||
|
||||
/*
|
||||
@ -261,14 +265,14 @@ struct panfrost_dump_object_header {
|
||||
* with new fields and also keep it 512-byte aligned
|
||||
*/
|
||||
|
||||
__le32 sizer[496];
|
||||
__u32 sizer[496];
|
||||
};
|
||||
};
|
||||
|
||||
/* Registers object, an array of these */
|
||||
struct panfrost_dump_registers {
|
||||
__le32 reg;
|
||||
__le32 value;
|
||||
__u32 reg;
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user