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Char/Misc driver fixes for 5.18-rc5

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Here are a small number of char/misc/other driver fixes for 5.18-rc5
 
 Nothing major in here, this is mostly IIO driver fixes along with some
 other small things:
 	- at25 driver fix for systems without a dma-able stack
 	- phy driver fixes for reported issues
 	- binder driver fixes for reported issues
 
 All of these have been in linux-next without any reported problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'char-misc-5.18-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver fixes from Greg KH:
 "Here are a small number of char/misc/other driver fixes for 5.18-rc5

  Nothing major in here, this is mostly IIO driver fixes along with some
  other small things:

   - at25 driver fix for systems without a dma-able stack

   - phy driver fixes for reported issues

   - binder driver fixes for reported issues

  All of these have been in linux-next without any reported problems"

* tag 'char-misc-5.18-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (31 commits)
  eeprom: at25: Use DMA safe buffers
  binder: Gracefully handle BINDER_TYPE_FDA objects with num_fds=0
  binder: Address corner cases in deferred copy and fixup
  phy: amlogic: fix error path in phy_g12a_usb3_pcie_probe()
  iio: imu: inv_icm42600: Fix I2C init possible nack
  iio: dac: ltc2688: fix voltage scale read
  interconnect: qcom: sdx55: Drop IP0 interconnects
  interconnect: qcom: sc7180: Drop IP0 interconnects
  phy: ti: Add missing pm_runtime_disable() in serdes_am654_probe
  phy: mapphone-mdm6600: Fix PM error handling in phy_mdm6600_probe
  phy: ti: omap-usb2: Fix error handling in omap_usb2_enable_clocks
  bus: mhi: host: pci_generic: Flush recovery worker during freeze
  bus: mhi: host: pci_generic: Add missing poweroff() PM callback
  phy: ti: tusb1210: Fix an error handling path in tusb1210_probe()
  phy: samsung: exynos5250-sata: fix missing device put in probe error paths
  phy: samsung: Fix missing of_node_put() in exynos_sata_phy_probe
  phy: ti: Fix missing of_node_put in ti_pipe3_get_sysctrl()
  phy: ti: tusb1210: Make tusb1210_chg_det_states static
  iio:dac:ad3552r: Fix an IS_ERR() vs NULL check
  iio: sx9324: Fix default precharge internal resistance register
  ...
This commit is contained in:
Linus Torvalds 2022-04-30 10:15:57 -07:00
commit e2e5ebecca
25 changed files with 148 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/android/binder.c
View File

@ -2295,6 +2295,7 @@ static int binder_do_deferred_txn_copies(struct binder_alloc *alloc,
{ {
int ret = 0; int ret = 0;
struct binder_sg_copy *sgc, *tmpsgc; struct binder_sg_copy *sgc, *tmpsgc;
struct binder_ptr_fixup *tmppf;
struct binder_ptr_fixup *pf = struct binder_ptr_fixup *pf =
list_first_entry_or_null(pf_head, struct binder_ptr_fixup, list_first_entry_or_null(pf_head, struct binder_ptr_fixup,
node); node);
@ -2349,7 +2350,11 @@ static int binder_do_deferred_txn_copies(struct binder_alloc *alloc,
list_del(&sgc->node); list_del(&sgc->node);
kfree(sgc); kfree(sgc);
} }
BUG_ON(!list_empty(pf_head)); list_for_each_entry_safe(pf, tmppf, pf_head, node) {
BUG_ON(pf->skip_size == 0);
list_del(&pf->node);
kfree(pf);
}
BUG_ON(!list_empty(sgc_head)); BUG_ON(!list_empty(sgc_head));
return ret > 0 ? -EINVAL : ret; return ret > 0 ? -EINVAL : ret;
@ -2486,6 +2491,9 @@ static int binder_translate_fd_array(struct list_head *pf_head,
struct binder_proc *proc = thread->proc; struct binder_proc *proc = thread->proc;
int ret; int ret;
if (fda->num_fds == 0)
return 0;
fd_buf_size = sizeof(u32) * fda->num_fds; fd_buf_size = sizeof(u32) * fda->num_fds;
if (fda->num_fds >= SIZE_MAX / sizeof(u32)) { if (fda->num_fds >= SIZE_MAX / sizeof(u32)) {
binder_user_error("%d:%d got transaction with invalid number of fds (%lld)\n", binder_user_error("%d:%d got transaction with invalid number of fds (%lld)\n",

2
drivers/bus/mhi/host/pci_generic.c
View File

@ -1060,6 +1060,7 @@ static int __maybe_unused mhi_pci_freeze(struct device *dev)
* the intermediate restore kernel reinitializes MHI device with new * the intermediate restore kernel reinitializes MHI device with new
* context. * context.
*/ */
flush_work(&mhi_pdev->recovery_work);
if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
mhi_power_down(mhi_cntrl, true); mhi_power_down(mhi_cntrl, true);
mhi_unprepare_after_power_down(mhi_cntrl); mhi_unprepare_after_power_down(mhi_cntrl);
@ -1085,6 +1086,7 @@ static const struct dev_pm_ops mhi_pci_pm_ops = {
.resume = mhi_pci_resume, .resume = mhi_pci_resume,
.freeze = mhi_pci_freeze, .freeze = mhi_pci_freeze,
.thaw = mhi_pci_restore, .thaw = mhi_pci_restore,
.poweroff = mhi_pci_freeze,
.restore = mhi_pci_restore, .restore = mhi_pci_restore,
#endif #endif
}; };

12
drivers/iio/adc/ad7280a.c
View File

@ -745,7 +745,7 @@ static int ad7280a_write_thresh(struct iio_dev *indio_dev,
case IIO_EV_DIR_RISING: case IIO_EV_DIR_RISING:
addr = AD7280A_CELL_OVERVOLTAGE_REG; addr = AD7280A_CELL_OVERVOLTAGE_REG;
ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr, ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
1, val); 1, value);
if (ret) if (ret)
break; break;
st->cell_threshhigh = value; st->cell_threshhigh = value;
@ -753,7 +753,7 @@ static int ad7280a_write_thresh(struct iio_dev *indio_dev,
case IIO_EV_DIR_FALLING: case IIO_EV_DIR_FALLING:
addr = AD7280A_CELL_UNDERVOLTAGE_REG; addr = AD7280A_CELL_UNDERVOLTAGE_REG;
ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr, ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
1, val); 1, value);
if (ret) if (ret)
break; break;
st->cell_threshlow = value; st->cell_threshlow = value;
@ -770,18 +770,18 @@ static int ad7280a_write_thresh(struct iio_dev *indio_dev,
case IIO_EV_DIR_RISING: case IIO_EV_DIR_RISING:
addr = AD7280A_AUX_ADC_OVERVOLTAGE_REG; addr = AD7280A_AUX_ADC_OVERVOLTAGE_REG;
ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr, ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
1, val); 1, value);
if (ret) if (ret)
break; break;
st->aux_threshhigh = val; st->aux_threshhigh = value;
break; break;
case IIO_EV_DIR_FALLING: case IIO_EV_DIR_FALLING:
addr = AD7280A_AUX_ADC_UNDERVOLTAGE_REG; addr = AD7280A_AUX_ADC_UNDERVOLTAGE_REG;
ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr, ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, addr,
1, val); 1, value);
if (ret) if (ret)
break; break;
st->aux_threshlow = val; st->aux_threshlow = value;
break; break;
default: default:
ret = -EINVAL; ret = -EINVAL;

5
drivers/iio/chemical/scd4x.c
View File

@ -471,12 +471,15 @@ static ssize_t calibration_forced_value_store(struct device *dev,
ret = scd4x_write_and_fetch(state, CMD_FRC, arg, &val, sizeof(val)); ret = scd4x_write_and_fetch(state, CMD_FRC, arg, &val, sizeof(val));
mutex_unlock(&state->lock); mutex_unlock(&state->lock);
if (ret)
return ret;
if (val == 0xff) { if (val == 0xff) {
dev_err(dev, "forced calibration has failed"); dev_err(dev, "forced calibration has failed");
return -EINVAL; return -EINVAL;
} }
return ret ?: len; return len;
} }
static IIO_DEVICE_ATTR_RW(calibration_auto_enable, 0); static IIO_DEVICE_ATTR_RW(calibration_auto_enable, 0);

6
drivers/iio/dac/ad3552r.c
View File

@ -656,7 +656,7 @@ static int ad3552r_reset(struct ad3552r_desc *dac)
{ {
struct reg_addr_pool addr; struct reg_addr_pool addr;
int ret; int ret;
u16 val; int val;
dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset", dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",
GPIOD_OUT_LOW); GPIOD_OUT_LOW);
@ -809,10 +809,10 @@ static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac,
gain_child = fwnode_get_named_child_node(child, gain_child = fwnode_get_named_child_node(child,
"custom-output-range-config"); "custom-output-range-config");
if (IS_ERR(gain_child)) { if (!gain_child) {
dev_err(dev, dev_err(dev,
"mandatory custom-output-range-config property missing\n"); "mandatory custom-output-range-config property missing\n");
return PTR_ERR(gain_child); return -EINVAL;
} }
dac->ch_data[ch].range_override = 1; dac->ch_data[ch].range_override = 1;

2
drivers/iio/dac/ad5446.c
View File

@ -178,7 +178,7 @@ static int ad5446_read_raw(struct iio_dev *indio_dev,
switch (m) { switch (m) {
case IIO_CHAN_INFO_RAW: case IIO_CHAN_INFO_RAW:
*val = st->cached_val; *val = st->cached_val >> chan->scan_type.shift;
return IIO_VAL_INT; return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE: case IIO_CHAN_INFO_SCALE:
*val = st->vref_mv; *val = st->vref_mv;

2
drivers/iio/dac/ad5592r-base.c
View File

@ -522,7 +522,7 @@ static int ad5592r_alloc_channels(struct iio_dev *iio_dev)
if (!ret) if (!ret)
st->channel_modes[reg] = tmp; st->channel_modes[reg] = tmp;
fwnode_property_read_u32(child, "adi,off-state", &tmp); ret = fwnode_property_read_u32(child, "adi,off-state", &tmp);
if (!ret) if (!ret)
st->channel_offstate[reg] = tmp; st->channel_offstate[reg] = tmp;
} }

2
drivers/iio/dac/ltc2688.c
View File

@ -298,7 +298,7 @@ static int ltc2688_read_raw(struct iio_dev *indio_dev,
if (ret) if (ret)
return ret; return ret;
*val = 16; *val2 = 16;
return IIO_VAL_FRACTIONAL_LOG2; return IIO_VAL_FRACTIONAL_LOG2;
case IIO_CHAN_INFO_CALIBBIAS: case IIO_CHAN_INFO_CALIBBIAS:
ret = regmap_read(st->regmap, ret = regmap_read(st->regmap,

28
drivers/iio/dac/ti-dac5571.c
View File

@ -19,6 +19,7 @@
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/mod_devicetable.h> #include <linux/mod_devicetable.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h> #include <linux/regulator/consumer.h>
enum chip_id { enum chip_id {
@ -311,6 +312,7 @@ static int dac5571_probe(struct i2c_client *client,
const struct dac5571_spec *spec; const struct dac5571_spec *spec;
struct dac5571_data *data; struct dac5571_data *data;
struct iio_dev *indio_dev; struct iio_dev *indio_dev;
enum chip_id chip_id;
int ret, i; int ret, i;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
@ -326,7 +328,13 @@ static int dac5571_probe(struct i2c_client *client,
indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = dac5571_channels; indio_dev->channels = dac5571_channels;
spec = &dac5571_spec[id->driver_data]; if (dev_fwnode(dev))
chip_id = (uintptr_t)device_get_match_data(dev);
else
chip_id = id->driver_data;
spec = &dac5571_spec[chip_id];
indio_dev->num_channels = spec->num_channels; indio_dev->num_channels = spec->num_channels;
data->spec = spec; data->spec = spec;
@ -385,15 +393,15 @@ static int dac5571_remove(struct i2c_client *i2c)
} }
static const struct of_device_id dac5571_of_id[] = { static const struct of_device_id dac5571_of_id[] = {
{.compatible = "ti,dac5571"}, {.compatible = "ti,dac5571", .data = (void *)single_8bit},
{.compatible = "ti,dac6571"}, {.compatible = "ti,dac6571", .data = (void *)single_10bit},
{.compatible = "ti,dac7571"}, {.compatible = "ti,dac7571", .data = (void *)single_12bit},
{.compatible = "ti,dac5574"}, {.compatible = "ti,dac5574", .data = (void *)quad_8bit},
{.compatible = "ti,dac6574"}, {.compatible = "ti,dac6574", .data = (void *)quad_10bit},
{.compatible = "ti,dac7574"}, {.compatible = "ti,dac7574", .data = (void *)quad_12bit},
{.compatible = "ti,dac5573"}, {.compatible = "ti,dac5573", .data = (void *)quad_8bit},
{.compatible = "ti,dac6573"}, {.compatible = "ti,dac6573", .data = (void *)quad_10bit},
{.compatible = "ti,dac7573"}, {.compatible = "ti,dac7573", .data = (void *)quad_12bit},
{} {}
}; };
MODULE_DEVICE_TABLE(of, dac5571_of_id); MODULE_DEVICE_TABLE(of, dac5571_of_id);

1
drivers/iio/filter/Kconfig
View File

@ -8,6 +8,7 @@ menu "Filters"
config ADMV8818 config ADMV8818
tristate "Analog Devices ADMV8818 High-Pass and Low-Pass Filter" tristate "Analog Devices ADMV8818 High-Pass and Low-Pass Filter"
depends on SPI && COMMON_CLK && 64BIT depends on SPI && COMMON_CLK && 64BIT
select REGMAP_SPI
help help
Say yes here to build support for Analog Devices ADMV8818 Say yes here to build support for Analog Devices ADMV8818
2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter. 2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter.

20
drivers/iio/imu/bmi160/bmi160_core.c
View File

@ -730,7 +730,7 @@ static int bmi160_chip_init(struct bmi160_data *data, bool use_spi)
ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET); ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET);
if (ret) if (ret)
return ret; goto disable_regulator;
usleep_range(BMI160_SOFTRESET_USLEEP, BMI160_SOFTRESET_USLEEP + 1); usleep_range(BMI160_SOFTRESET_USLEEP, BMI160_SOFTRESET_USLEEP + 1);
@ -741,29 +741,37 @@ static int bmi160_chip_init(struct bmi160_data *data, bool use_spi)
if (use_spi) { if (use_spi) {
ret = regmap_read(data->regmap, BMI160_REG_DUMMY, &val); ret = regmap_read(data->regmap, BMI160_REG_DUMMY, &val);
if (ret) if (ret)
return ret; goto disable_regulator;
} }
ret = regmap_read(data->regmap, BMI160_REG_CHIP_ID, &val); ret = regmap_read(data->regmap, BMI160_REG_CHIP_ID, &val);
if (ret) { if (ret) {
dev_err(dev, "Error reading chip id\n"); dev_err(dev, "Error reading chip id\n");
return ret; goto disable_regulator;
} }
if (val != BMI160_CHIP_ID_VAL) { if (val != BMI160_CHIP_ID_VAL) {
dev_err(dev, "Wrong chip id, got %x expected %x\n", dev_err(dev, "Wrong chip id, got %x expected %x\n",
val, BMI160_CHIP_ID_VAL); val, BMI160_CHIP_ID_VAL);
return -ENODEV; ret = -ENODEV;
goto disable_regulator;
} }
ret = bmi160_set_mode(data, BMI160_ACCEL, true); ret = bmi160_set_mode(data, BMI160_ACCEL, true);
if (ret) if (ret)
return ret; goto disable_regulator;
ret = bmi160_set_mode(data, BMI160_GYRO, true); ret = bmi160_set_mode(data, BMI160_GYRO, true);
if (ret) if (ret)
return ret; goto disable_accel;
return 0; return 0;
disable_accel:
bmi160_set_mode(data, BMI160_ACCEL, false);
disable_regulator:
regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies);
return ret;
} }
static int bmi160_data_rdy_trigger_set_state(struct iio_trigger *trig, static int bmi160_data_rdy_trigger_set_state(struct iio_trigger *trig,

15
drivers/iio/imu/inv_icm42600/inv_icm42600_i2c.c
View File

@ -18,12 +18,15 @@ static int inv_icm42600_i2c_bus_setup(struct inv_icm42600_state *st)
unsigned int mask, val; unsigned int mask, val;
int ret; int ret;
/* setup interface registers */ /*
ret = regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG6, * setup interface registers
INV_ICM42600_INTF_CONFIG6_MASK, * This register write to REG_INTF_CONFIG6 enables a spike filter that
INV_ICM42600_INTF_CONFIG6_I3C_EN); * is impacting the line and can prevent the I2C ACK to be seen by the
if (ret) * controller. So we don't test the return value.
return ret; */
regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG6,
INV_ICM42600_INTF_CONFIG6_MASK,
INV_ICM42600_INTF_CONFIG6_I3C_EN);
ret = regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG4, ret = regmap_update_bits(st->map, INV_ICM42600_REG_INTF_CONFIG4,
INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY, 0); INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY, 0);

1
drivers/iio/magnetometer/ak8975.c
View File

@ -416,6 +416,7 @@ static int ak8975_power_on(const struct ak8975_data *data)
if (ret) { if (ret) {
dev_warn(&data->client->dev, dev_warn(&data->client->dev,
"Failed to enable specified Vid supply\n"); "Failed to enable specified Vid supply\n");
regulator_disable(data->vdd);
return ret; return ret;
} }

32
drivers/iio/proximity/sx9324.c
View File

@ -70,13 +70,17 @@
#define SX9324_REG_AFE_PH2 0x2a #define SX9324_REG_AFE_PH2 0x2a
#define SX9324_REG_AFE_PH3 0x2b #define SX9324_REG_AFE_PH3 0x2b
#define SX9324_REG_AFE_CTRL8 0x2c #define SX9324_REG_AFE_CTRL8 0x2c
#define SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM 0x02 #define SX9324_REG_AFE_CTRL8_RESERVED 0x10
#define SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM 0x02
#define SX9324_REG_AFE_CTRL9 0x2d #define SX9324_REG_AFE_CTRL9 0x2d
#define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08 #define SX9324_REG_AFE_CTRL9_AGAIN_1 0x08
#define SX9324_REG_PROX_CTRL0 0x30 #define SX9324_REG_PROX_CTRL0 0x30
#define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3) #define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3)
#define SX9324_REG_PROX_CTRL0_GAIN_1 0x80 #define SX9324_REG_PROX_CTRL0_GAIN_SHIFT 3
#define SX9324_REG_PROX_CTRL0_GAIN_RSVD 0x0
#define SX9324_REG_PROX_CTRL0_GAIN_1 0x1
#define SX9324_REG_PROX_CTRL0_GAIN_8 0x4
#define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0) #define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0)
#define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01 #define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01
#define SX9324_REG_PROX_CTRL1 0x31 #define SX9324_REG_PROX_CTRL1 0x31
@ -379,7 +383,14 @@ static int sx9324_read_gain(struct sx_common_data *data,
if (ret) if (ret)
return ret; return ret;
*val = 1 << FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval); regval = FIELD_GET(SX9324_REG_PROX_CTRL0_GAIN_MASK, regval);
if (regval)
regval--;
else if (regval == SX9324_REG_PROX_CTRL0_GAIN_RSVD ||
regval > SX9324_REG_PROX_CTRL0_GAIN_8)
return -EINVAL;
*val = 1 << regval;
return IIO_VAL_INT; return IIO_VAL_INT;
} }
@ -725,8 +736,12 @@ static int sx9324_write_gain(struct sx_common_data *data,
unsigned int gain, reg; unsigned int gain, reg;
int ret; int ret;
gain = ilog2(val);
reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2; reg = SX9324_REG_PROX_CTRL0 + chan->channel / 2;
gain = ilog2(val) + 1;
if (val <= 0 || gain > SX9324_REG_PROX_CTRL0_GAIN_8)
return -EINVAL;
gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain); gain = FIELD_PREP(SX9324_REG_PROX_CTRL0_GAIN_MASK, gain);
mutex_lock(&data->mutex); mutex_lock(&data->mutex);
@ -781,12 +796,15 @@ static const struct sx_common_reg_default sx9324_default_regs[] = {
{ SX9324_REG_AFE_PH2, 0x1a }, { SX9324_REG_AFE_PH2, 0x1a },
{ SX9324_REG_AFE_PH3, 0x16 }, { SX9324_REG_AFE_PH3, 0x16 },
{ SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM }, { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESERVED |
SX9324_REG_AFE_CTRL8_RESFILTIN_4KOHM },
{ SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 }, { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 },
{ SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL0_GAIN_1 | { SX9324_REG_PROX_CTRL0,
SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
SX9324_REG_PROX_CTRL0_RAWFILT_1P50 }, SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
{ SX9324_REG_PROX_CTRL1, SX9324_REG_PROX_CTRL0_GAIN_1 | { SX9324_REG_PROX_CTRL1,
SX9324_REG_PROX_CTRL0_GAIN_1 << SX9324_REG_PROX_CTRL0_GAIN_SHIFT |
SX9324_REG_PROX_CTRL0_RAWFILT_1P50 }, SX9324_REG_PROX_CTRL0_RAWFILT_1P50 },
{ SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K }, { SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K },
{ SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES | { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES |

1
drivers/iio/proximity/sx_common.c
View File

@ -521,6 +521,7 @@ int sx_common_probe(struct i2c_client *client,
return dev_err_probe(dev, ret, "error reading WHOAMI\n"); return dev_err_probe(dev, ret, "error reading WHOAMI\n");
ACPI_COMPANION_SET(&indio_dev->dev, ACPI_COMPANION(dev)); ACPI_COMPANION_SET(&indio_dev->dev, ACPI_COMPANION(dev));
indio_dev->dev.of_node = client->dev.of_node;
indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->channels = data->chip_info->iio_channels; indio_dev->channels = data->chip_info->iio_channels;

21
drivers/interconnect/qcom/sc7180.c
View File

@ -47,7 +47,6 @@ DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM
DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC); DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC);
DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC); DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC);
DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC);
DEFINE_QNODE(ipa_core_master, SC7180_MASTER_IPA_CORE, 1, 8, SC7180_SLAVE_IPA_CORE);
DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1); DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1);
DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC); DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC);
DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC); DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC);
@ -129,7 +128,6 @@ DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC); DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC);
DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC); DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC);
DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4); DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4);
DEFINE_QNODE(ipa_core_slave, SC7180_SLAVE_IPA_CORE, 1, 8);
DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4); DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4);
DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC); DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC);
DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC); DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC);
@ -160,7 +158,6 @@ DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9); DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
@ -372,22 +369,6 @@ static struct qcom_icc_desc sc7180_gem_noc = {
.num_bcms = ARRAY_SIZE(gem_noc_bcms), .num_bcms = ARRAY_SIZE(gem_noc_bcms),
}; };
static struct qcom_icc_bcm *ipa_virt_bcms[] = {
&bcm_ip0,
};
static struct qcom_icc_node *ipa_virt_nodes[] = {
[MASTER_IPA_CORE] = &ipa_core_master,
[SLAVE_IPA_CORE] = &ipa_core_slave,
};
static struct qcom_icc_desc sc7180_ipa_virt = {
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
};
static struct qcom_icc_bcm *mc_virt_bcms[] = { static struct qcom_icc_bcm *mc_virt_bcms[] = {
&bcm_acv, &bcm_acv,
&bcm_mc0, &bcm_mc0,
@ -519,8 +500,6 @@ static const struct of_device_id qnoc_of_match[] = {
.data = &sc7180_dc_noc}, .data = &sc7180_dc_noc},
{ .compatible = "qcom,sc7180-gem-noc", { .compatible = "qcom,sc7180-gem-noc",
.data = &sc7180_gem_noc}, .data = &sc7180_gem_noc},
{ .compatible = "qcom,sc7180-ipa-virt",
.data = &sc7180_ipa_virt},
{ .compatible = "qcom,sc7180-mc-virt", { .compatible = "qcom,sc7180-mc-virt",
.data = &sc7180_mc_virt}, .data = &sc7180_mc_virt},
{ .compatible = "qcom,sc7180-mmss-noc", { .compatible = "qcom,sc7180-mmss-noc",

21
drivers/interconnect/qcom/sdx55.c
View File

@ -18,7 +18,6 @@
#include "icc-rpmh.h" #include "icc-rpmh.h"
#include "sdx55.h" #include "sdx55.h"
DEFINE_QNODE(ipa_core_master, SDX55_MASTER_IPA_CORE, 1, 8, SDX55_SLAVE_IPA_CORE);
DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0); DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0);
DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC);
DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC); DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC);
@ -40,7 +39,6 @@ DEFINE_QNODE(xm_pcie, SDX55_MASTER_PCIE, 1, 8, SDX55_SLAVE_ANOC_SNOC);
DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO);
DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC); DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC);
DEFINE_QNODE(ipa_core_slave, SDX55_SLAVE_IPA_CORE, 1, 8);
DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4); DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4);
DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0); DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0);
DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC); DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC);
@ -82,7 +80,6 @@ DEFINE_QNODE(xs_sys_tcu_cfg, SDX55_SLAVE_TCU, 1, 8);
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg); DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg);
DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);
DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie); DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie);
@ -219,22 +216,6 @@ static const struct qcom_icc_desc sdx55_system_noc = {
.num_bcms = ARRAY_SIZE(system_noc_bcms), .num_bcms = ARRAY_SIZE(system_noc_bcms),
}; };
static struct qcom_icc_bcm *ipa_virt_bcms[] = {
&bcm_ip0,
};
static struct qcom_icc_node *ipa_virt_nodes[] = {
[MASTER_IPA_CORE] = &ipa_core_master,
[SLAVE_IPA_CORE] = &ipa_core_slave,
};
static const struct qcom_icc_desc sdx55_ipa_virt = {
.nodes = ipa_virt_nodes,
.num_nodes = ARRAY_SIZE(ipa_virt_nodes),
.bcms = ipa_virt_bcms,
.num_bcms = ARRAY_SIZE(ipa_virt_bcms),
};
static const struct of_device_id qnoc_of_match[] = { static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,sdx55-mc-virt", { .compatible = "qcom,sdx55-mc-virt",
.data = &sdx55_mc_virt}, .data = &sdx55_mc_virt},
@ -242,8 +223,6 @@ static const struct of_device_id qnoc_of_match[] = {
.data = &sdx55_mem_noc}, .data = &sdx55_mem_noc},
{ .compatible = "qcom,sdx55-system-noc", { .compatible = "qcom,sdx55-system-noc",
.data = &sdx55_system_noc}, .data = &sdx55_system_noc},
{ .compatible = "qcom,sdx55-ipa-virt",
.data = &sdx55_ipa_virt},
{ } { }
}; };
MODULE_DEVICE_TABLE(of, qnoc_of_match); MODULE_DEVICE_TABLE(of, qnoc_of_match);

19
drivers/misc/eeprom/at25.c
View File

@ -31,6 +31,8 @@
*/ */
#define FM25_SN_LEN 8 /* serial number length */ #define FM25_SN_LEN 8 /* serial number length */
#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
struct at25_data { struct at25_data {
struct spi_eeprom chip; struct spi_eeprom chip;
struct spi_device *spi; struct spi_device *spi;
@ -39,6 +41,7 @@ struct at25_data {
struct nvmem_config nvmem_config; struct nvmem_config nvmem_config;
struct nvmem_device *nvmem; struct nvmem_device *nvmem;
u8 sernum[FM25_SN_LEN]; u8 sernum[FM25_SN_LEN];
u8 command[EE_MAXADDRLEN + 1];
}; };
#define AT25_WREN 0x06 /* latch the write enable */ #define AT25_WREN 0x06 /* latch the write enable */
@ -61,8 +64,6 @@ struct at25_data {
#define FM25_ID_LEN 9 /* ID length */ #define FM25_ID_LEN 9 /* ID length */
#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
/* /*
* Specs often allow 5ms for a page write, sometimes 20ms; * Specs often allow 5ms for a page write, sometimes 20ms;
* it's important to recover from write timeouts. * it's important to recover from write timeouts.
@ -78,7 +79,6 @@ static int at25_ee_read(void *priv, unsigned int offset,
{ {
struct at25_data *at25 = priv; struct at25_data *at25 = priv;
char *buf = val; char *buf = val;
u8 command[EE_MAXADDRLEN + 1];
u8 *cp; u8 *cp;
ssize_t status; ssize_t status;
struct spi_transfer t[2]; struct spi_transfer t[2];
@ -92,12 +92,15 @@ static int at25_ee_read(void *priv, unsigned int offset,
if (unlikely(!count)) if (unlikely(!count))
return -EINVAL; return -EINVAL;
cp = command; cp = at25->command;
instr = AT25_READ; instr = AT25_READ;
if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR) if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
if (offset >= BIT(at25->addrlen * 8)) if (offset >= BIT(at25->addrlen * 8))
instr |= AT25_INSTR_BIT3; instr |= AT25_INSTR_BIT3;
mutex_lock(&at25->lock);
*cp++ = instr; *cp++ = instr;
/* 8/16/24-bit address is written MSB first */ /* 8/16/24-bit address is written MSB first */
@ -116,7 +119,7 @@ static int at25_ee_read(void *priv, unsigned int offset,
spi_message_init(&m); spi_message_init(&m);
memset(t, 0, sizeof(t)); memset(t, 0, sizeof(t));
t[0].tx_buf = command; t[0].tx_buf = at25->command;
t[0].len = at25->addrlen + 1; t[0].len = at25->addrlen + 1;
spi_message_add_tail(&t[0], &m); spi_message_add_tail(&t[0], &m);
@ -124,8 +127,6 @@ static int at25_ee_read(void *priv, unsigned int offset,
t[1].len = count; t[1].len = count;
spi_message_add_tail(&t[1], &m); spi_message_add_tail(&t[1], &m);
mutex_lock(&at25->lock);
/* /*
* Read it all at once. * Read it all at once.
* *
@ -152,7 +153,7 @@ static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,
spi_message_init(&m); spi_message_init(&m);
memset(t, 0, sizeof(t)); memset(t, 0, sizeof(t));
t[0].tx_buf = &command; t[0].tx_buf = at25->command;
t[0].len = 1; t[0].len = 1;
spi_message_add_tail(&t[0], &m); spi_message_add_tail(&t[0], &m);
@ -162,6 +163,8 @@ static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,
mutex_lock(&at25->lock); mutex_lock(&at25->lock);
at25->command[0] = command;
status = spi_sync(at25->spi, &m); status = spi_sync(at25->spi, &m);
dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status); dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status);

20
drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
View File

@ -414,19 +414,19 @@ static int phy_g12a_usb3_pcie_probe(struct platform_device *pdev)
ret = clk_prepare_enable(priv->clk_ref); ret = clk_prepare_enable(priv->clk_ref);
if (ret) if (ret)
goto err_disable_clk_ref; return ret;
priv->reset = devm_reset_control_array_get_exclusive(dev); priv->reset = devm_reset_control_array_get_exclusive(dev);
if (IS_ERR(priv->reset)) if (IS_ERR(priv->reset)) {
return PTR_ERR(priv->reset); ret = PTR_ERR(priv->reset);
goto err_disable_clk_ref;
}
priv->phy = devm_phy_create(dev, np, &phy_g12a_usb3_pcie_ops); priv->phy = devm_phy_create(dev, np, &phy_g12a_usb3_pcie_ops);
if (IS_ERR(priv->phy)) { if (IS_ERR(priv->phy)) {
ret = PTR_ERR(priv->phy); ret = PTR_ERR(priv->phy);
if (ret != -EPROBE_DEFER) dev_err_probe(dev, ret, "failed to create PHY\n");
dev_err(dev, "failed to create PHY\n"); goto err_disable_clk_ref;
return ret;
} }
phy_set_drvdata(priv->phy, priv); phy_set_drvdata(priv->phy, priv);
@ -434,8 +434,12 @@ static int phy_g12a_usb3_pcie_probe(struct platform_device *pdev)
phy_provider = devm_of_phy_provider_register(dev, phy_provider = devm_of_phy_provider_register(dev,
phy_g12a_usb3_pcie_xlate); phy_g12a_usb3_pcie_xlate);
if (IS_ERR(phy_provider)) {
ret = PTR_ERR(phy_provider);
goto err_disable_clk_ref;
}
return PTR_ERR_OR_ZERO(phy_provider); return 0;
err_disable_clk_ref: err_disable_clk_ref:
clk_disable_unprepare(priv->clk_ref); clk_disable_unprepare(priv->clk_ref);

3
drivers/phy/motorola/phy-mapphone-mdm6600.c
View File

@ -629,7 +629,8 @@ idle:
cleanup: cleanup:
if (error < 0) if (error < 0)
phy_mdm6600_device_power_off(ddata); phy_mdm6600_device_power_off(ddata);
pm_runtime_disable(ddata->dev);
pm_runtime_dont_use_autosuspend(ddata->dev);
return error; return error;
} }

21
drivers/phy/samsung/phy-exynos5250-sata.c
View File

@ -187,6 +187,7 @@ static int exynos_sata_phy_probe(struct platform_device *pdev)
return -EINVAL; return -EINVAL;
sata_phy->client = of_find_i2c_device_by_node(node); sata_phy->client = of_find_i2c_device_by_node(node);
of_node_put(node);
if (!sata_phy->client) if (!sata_phy->client)
return -EPROBE_DEFER; return -EPROBE_DEFER;
@ -195,20 +196,21 @@ static int exynos_sata_phy_probe(struct platform_device *pdev)
sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl"); sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl");
if (IS_ERR(sata_phy->phyclk)) { if (IS_ERR(sata_phy->phyclk)) {
dev_err(dev, "failed to get clk for PHY\n"); dev_err(dev, "failed to get clk for PHY\n");
return PTR_ERR(sata_phy->phyclk); ret = PTR_ERR(sata_phy->phyclk);
goto put_dev;
} }
ret = clk_prepare_enable(sata_phy->phyclk); ret = clk_prepare_enable(sata_phy->phyclk);
if (ret < 0) { if (ret < 0) {
dev_err(dev, "failed to enable source clk\n"); dev_err(dev, "failed to enable source clk\n");
return ret; goto put_dev;
} }
sata_phy->phy = devm_phy_create(dev, NULL, &exynos_sata_phy_ops); sata_phy->phy = devm_phy_create(dev, NULL, &exynos_sata_phy_ops);
if (IS_ERR(sata_phy->phy)) { if (IS_ERR(sata_phy->phy)) {
clk_disable_unprepare(sata_phy->phyclk);
dev_err(dev, "failed to create PHY\n"); dev_err(dev, "failed to create PHY\n");
return PTR_ERR(sata_phy->phy); ret = PTR_ERR(sata_phy->phy);
goto clk_disable;
} }
phy_set_drvdata(sata_phy->phy, sata_phy); phy_set_drvdata(sata_phy->phy, sata_phy);
@ -216,11 +218,18 @@ static int exynos_sata_phy_probe(struct platform_device *pdev)
phy_provider = devm_of_phy_provider_register(dev, phy_provider = devm_of_phy_provider_register(dev,
of_phy_simple_xlate); of_phy_simple_xlate);
if (IS_ERR(phy_provider)) { if (IS_ERR(phy_provider)) {
clk_disable_unprepare(sata_phy->phyclk); ret = PTR_ERR(phy_provider);
return PTR_ERR(phy_provider); goto clk_disable;
} }
return 0; return 0;
clk_disable:
clk_disable_unprepare(sata_phy->phyclk);
put_dev:
put_device(&sata_phy->client->dev);
return ret;
} }
static const struct of_device_id exynos_sata_phy_of_match[] = { static const struct of_device_id exynos_sata_phy_of_match[] = {

2
drivers/phy/ti/phy-am654-serdes.c
View File

@ -838,7 +838,7 @@ static int serdes_am654_probe(struct platform_device *pdev)
clk_err: clk_err:
of_clk_del_provider(node); of_clk_del_provider(node);
pm_runtime_disable(dev);
return ret; return ret;
} }

2
drivers/phy/ti/phy-omap-usb2.c
View File

@ -215,7 +215,7 @@ static int omap_usb2_enable_clocks(struct omap_usb *phy)
return 0; return 0;
err1: err1:
clk_disable(phy->wkupclk); clk_disable_unprepare(phy->wkupclk);
err0: err0:
return ret; return ret;

1
drivers/phy/ti/phy-ti-pipe3.c
View File

@ -696,6 +696,7 @@ static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
} }
control_pdev = of_find_device_by_node(control_node); control_pdev = of_find_device_by_node(control_node);
of_node_put(control_node);
if (!control_pdev) { if (!control_pdev) {
dev_err(dev, "Failed to get control device\n"); dev_err(dev, "Failed to get control device\n");
return -EINVAL; return -EINVAL;

12
drivers/phy/ti/phy-tusb1210.c
View File

@ -155,7 +155,7 @@ static int tusb1210_set_mode(struct phy *phy, enum phy_mode mode, int submode)
} }
#ifdef CONFIG_POWER_SUPPLY #ifdef CONFIG_POWER_SUPPLY
const char * const tusb1210_chg_det_states[] = { static const char * const tusb1210_chg_det_states[] = {
"CHG_DET_CONNECTING", "CHG_DET_CONNECTING",
"CHG_DET_START_DET", "CHG_DET_START_DET",
"CHG_DET_READ_DET", "CHG_DET_READ_DET",
@ -537,12 +537,18 @@ static int tusb1210_probe(struct ulpi *ulpi)
tusb1210_probe_charger_detect(tusb); tusb1210_probe_charger_detect(tusb);
tusb->phy = ulpi_phy_create(ulpi, &phy_ops); tusb->phy = ulpi_phy_create(ulpi, &phy_ops);
if (IS_ERR(tusb->phy)) if (IS_ERR(tusb->phy)) {
return PTR_ERR(tusb->phy); ret = PTR_ERR(tusb->phy);
goto err_remove_charger;
}
phy_set_drvdata(tusb->phy, tusb); phy_set_drvdata(tusb->phy, tusb);
ulpi_set_drvdata(ulpi, tusb); ulpi_set_drvdata(ulpi, tusb);
return 0; return 0;
err_remove_charger:
tusb1210_remove_charger_detect(tusb);
return ret;
} }
static void tusb1210_remove(struct ulpi *ulpi) static void tusb1210_remove(struct ulpi *ulpi)