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drm/nouveau/pmu: convert to new-style nvkm_subdev

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:21 +10:00
parent a4f7bd3608
commit e2ca4e7d6e
21 changed files with 228 additions and 260 deletions
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27
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h
View File

@ -3,6 +3,7 @@
#include <core/subdev.h> #include <core/subdev.h>
struct nvkm_pmu { struct nvkm_pmu {
const struct nvkm_pmu_func *func;
struct nvkm_subdev subdev; struct nvkm_subdev subdev;
struct { struct {
@ -20,24 +21,20 @@ struct nvkm_pmu {
u32 message; u32 message;
u32 data[2]; u32 data[2];
} recv; } recv;
int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32);
void (*pgob)(struct nvkm_pmu *, bool);
}; };
static inline struct nvkm_pmu * int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process,
nvkm_pmu(void *obj) u32 message, u32 data0, u32 data1);
{ void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable);
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU);
}
extern struct nvkm_oclass *gt215_pmu_oclass; int gt215_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
extern struct nvkm_oclass *gf100_pmu_oclass; int gf100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
extern struct nvkm_oclass *gf110_pmu_oclass; int gf119_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
extern struct nvkm_oclass *gk104_pmu_oclass; int gk104_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
extern struct nvkm_oclass *gk110_pmu_oclass; int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
extern struct nvkm_oclass *gk208_pmu_oclass; int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
extern struct nvkm_oclass *gk20a_pmu_oclass; int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
/* interface to MEMX process running on PMU */ /* interface to MEMX process running on PMU */
struct nvkm_memx; struct nvkm_memx;

46
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -1111,7 +1111,7 @@ nva3_chipset = {
.mc = g98_mc_new, .mc = g98_mc_new,
.mmu = nv50_mmu_new, .mmu = nv50_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new, .pmu = gt215_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1144,7 +1144,7 @@ nva5_chipset = {
.mc = g98_mc_new, .mc = g98_mc_new,
.mmu = nv50_mmu_new, .mmu = nv50_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new, .pmu = gt215_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1176,7 +1176,7 @@ nva8_chipset = {
.mc = g98_mc_new, .mc = g98_mc_new,
.mmu = nv50_mmu_new, .mmu = nv50_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new, .pmu = gt215_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1270,7 +1270,7 @@ nvaf_chipset = {
.mc = g98_mc_new, .mc = g98_mc_new,
.mmu = nv50_mmu_new, .mmu = nv50_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new, .pmu = gt215_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1304,7 +1304,7 @@ nvc0_chipset = {
.mc = gf100_mc_new, .mc = gf100_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new, .pmu = gf100_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1339,7 +1339,7 @@ nvc1_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new, .pmu = gf100_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1373,7 +1373,7 @@ nvc3_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new, .pmu = gf100_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1407,7 +1407,7 @@ nvc4_chipset = {
.mc = gf100_mc_new, .mc = gf100_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new, .pmu = gf100_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1442,7 +1442,7 @@ nvc8_chipset = {
.mc = gf100_mc_new, .mc = gf100_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new, .pmu = gf100_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1477,7 +1477,7 @@ nvce_chipset = {
.mc = gf100_mc_new, .mc = gf100_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new, .pmu = gf100_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1512,7 +1512,7 @@ nvcf_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new, .pmu = gf100_pmu_new,
// .therm = gt215_therm_new, // .therm = gt215_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1578,7 +1578,7 @@ nvd9_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf110_pmu_new, .pmu = gf119_pmu_new,
// .therm = gf110_therm_new, // .therm = gf110_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1612,7 +1612,7 @@ nve4_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk104_pmu_new, .pmu = gk104_pmu_new,
// .therm = gf110_therm_new, // .therm = gf110_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1648,7 +1648,7 @@ nve6_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk104_pmu_new, .pmu = gk104_pmu_new,
// .therm = gf110_therm_new, // .therm = gf110_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1684,7 +1684,7 @@ nve7_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gf110_pmu_new, .pmu = gf119_pmu_new,
// .therm = gf110_therm_new, // .therm = gf110_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1715,7 +1715,7 @@ nvea_chipset = {
.ltc = gk104_ltc_new, .ltc = gk104_ltc_new,
.mc = gk20a_mc_new, .mc = gk20a_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
// .pmu = gk20a_pmu_new, .pmu = gk20a_pmu_new,
// .timer = gk20a_timer_new, // .timer = gk20a_timer_new,
// .volt = gk20a_volt_new, // .volt = gk20a_volt_new,
// .ce[2] = gk104_ce2_new, // .ce[2] = gk104_ce2_new,
@ -1744,7 +1744,7 @@ nvf0_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk110_pmu_new, .pmu = gk110_pmu_new,
// .therm = gf110_therm_new, // .therm = gf110_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1780,7 +1780,7 @@ nvf1_chipset = {
.mc = gf106_mc_new, .mc = gf106_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk110_pmu_new, .pmu = gk110_pmu_new,
// .therm = gf110_therm_new, // .therm = gf110_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1816,7 +1816,7 @@ nv106_chipset = {
.mc = gk20a_mc_new, .mc = gk20a_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new, .pmu = gk208_pmu_new,
// .therm = gf110_therm_new, // .therm = gf110_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1851,7 +1851,7 @@ nv108_chipset = {
.mc = gk20a_mc_new, .mc = gk20a_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new, .pmu = gk208_pmu_new,
// .therm = gf110_therm_new, // .therm = gf110_therm_new,
// .timer = nv04_timer_new, // .timer = nv04_timer_new,
// .volt = nv40_volt_new, // .volt = nv40_volt_new,
@ -1886,7 +1886,7 @@ nv117_chipset = {
.mc = gk20a_mc_new, .mc = gk20a_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new, .pmu = gm107_pmu_new,
// .therm = gm107_therm_new, // .therm = gm107_therm_new,
// .timer = gk20a_timer_new, // .timer = gk20a_timer_new,
// .ce[0] = gk104_ce0_new, // .ce[0] = gk104_ce0_new,
@ -1915,7 +1915,7 @@ nv124_chipset = {
.mc = gk20a_mc_new, .mc = gk20a_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new, .pmu = gm107_pmu_new,
// .timer = gk20a_timer_new, // .timer = gk20a_timer_new,
// .ce[0] = gm204_ce0_new, // .ce[0] = gm204_ce0_new,
// .ce[1] = gm204_ce1_new, // .ce[1] = gm204_ce1_new,
@ -1944,7 +1944,7 @@ nv126_chipset = {
.mc = gk20a_mc_new, .mc = gk20a_mc_new,
.mmu = gf100_mmu_new, .mmu = gf100_mmu_new,
.mxm = nv50_mxm_new, .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new, .pmu = gm107_pmu_new,
// .timer = gk20a_timer_new, // .timer = gk20a_timer_new,
// .ce[0] = gm204_ce0_new, // .ce[0] = gm204_ce0_new,
// .ce[1] = gm204_ce1_new, // .ce[1] = gm204_ce1_new,

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -30,7 +30,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc0: case 0xc0:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@ -47,7 +46,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc4: case 0xc4:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@ -64,7 +62,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc3: case 0xc3:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@ -80,7 +77,6 @@ gf100_identify(struct nvkm_device *device)
case 0xce: case 0xce:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@ -97,7 +93,6 @@ gf100_identify(struct nvkm_device *device)
case 0xcf: case 0xcf:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@ -113,7 +108,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc1: case 0xc1:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@ -129,7 +123,6 @@ gf100_identify(struct nvkm_device *device)
case 0xc8: case 0xc8:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
@ -146,7 +139,6 @@ gf100_identify(struct nvkm_device *device)
case 0xd9: case 0xd9:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -30,7 +30,6 @@ gk104_identify(struct nvkm_device *device)
case 0xe4: case 0xe4:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@ -48,7 +47,6 @@ gk104_identify(struct nvkm_device *device)
case 0xe7: case 0xe7:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@ -66,7 +64,6 @@ gk104_identify(struct nvkm_device *device)
case 0xe6: case 0xe6:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@ -90,12 +87,10 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
break; break;
case 0xf0: case 0xf0:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@ -113,7 +108,6 @@ gk104_identify(struct nvkm_device *device)
case 0xf1: case 0xf1:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
@ -131,7 +125,6 @@ gk104_identify(struct nvkm_device *device)
case 0x106: case 0x106:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
@ -148,7 +141,6 @@ gk104_identify(struct nvkm_device *device)
case 0x108: case 0x108:
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;

3
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -30,7 +30,6 @@ gm100_identify(struct nvkm_device *device)
case 0x117: case 0x117:
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0 #if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -58,7 +57,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif #endif
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0 #if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif #endif
@ -83,7 +81,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif #endif
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0 #if 0
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif #endif

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -177,7 +177,6 @@ nv50_identify(struct nvkm_device *device)
case 0xa3: case 0xa3:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -194,7 +193,6 @@ nv50_identify(struct nvkm_device *device)
case 0xa5: case 0xa5:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -210,7 +208,6 @@ nv50_identify(struct nvkm_device *device)
case 0xa8: case 0xa8:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
@ -226,7 +223,6 @@ nv50_identify(struct nvkm_device *device)
case 0xaf: case 0xaf:
device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass; device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;

9
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View File

@ -185,15 +185,13 @@ gk104_gr_init(struct nvkm_object *object)
struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr_oclass *oclass = (void *)object->oclass;
struct gf100_gr *gr = (void *)object; struct gf100_gr *gr = (void *)object;
struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_device *device = gr->base.engine.subdev.device;
struct nvkm_pmu *pmu = device->pmu;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
u32 data[TPC_MAX / 8] = {}; u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX]; u8 tpcnr[GPC_MAX];
int gpc, tpc, rop; int gpc, tpc, rop;
int ret, i; int ret, i;
if (pmu) nvkm_pmu_pgob(device->pmu, false);
pmu->pgob(pmu, false);
ret = nvkm_gr_init(&gr->base); ret = nvkm_gr_init(&gr->base);
if (ret) if (ret)
@ -315,9 +313,8 @@ gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject) struct nvkm_object **pobject)
{ {
struct nvkm_pmu *pmu = nvkm_pmu(parent); struct nvkm_device *device = (void *)parent;
if (pmu) nvkm_pmu_pgob(device->pmu, false);
pmu->pgob(pmu, false);
return gf100_gr_ctor(parent, engine, oclass, data, size, pobject); return gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
} }

3
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild
View File

@ -2,8 +2,9 @@ nvkm-y += nvkm/subdev/pmu/base.o
nvkm-y += nvkm/subdev/pmu/memx.o nvkm-y += nvkm/subdev/pmu/memx.o
nvkm-y += nvkm/subdev/pmu/gt215.o nvkm-y += nvkm/subdev/pmu/gt215.o
nvkm-y += nvkm/subdev/pmu/gf100.o nvkm-y += nvkm/subdev/pmu/gf100.o
nvkm-y += nvkm/subdev/pmu/gf110.o nvkm-y += nvkm/subdev/pmu/gf119.o
nvkm-y += nvkm/subdev/pmu/gk104.o nvkm-y += nvkm/subdev/pmu/gk104.o
nvkm-y += nvkm/subdev/pmu/gk110.o nvkm-y += nvkm/subdev/pmu/gk110.o
nvkm-y += nvkm/subdev/pmu/gk208.o nvkm-y += nvkm/subdev/pmu/gk208.o
nvkm-y += nvkm/subdev/pmu/gk20a.o nvkm-y += nvkm/subdev/pmu/gk20a.o
nvkm-y += nvkm/subdev/pmu/gm107.o

84
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c
View File

@ -28,12 +28,11 @@
void void
nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
{ {
const struct nvkm_pmu_impl *impl = (void *)nv_oclass(pmu); if (pmu->func->pgob)
if (impl->pgob) pmu->func->pgob(pmu, enable);
impl->pgob(pmu, enable);
} }
static int int
nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
u32 process, u32 message, u32 data0, u32 data1) u32 process, u32 message, u32 data0, u32 data1)
{ {
@ -144,7 +143,7 @@ nvkm_pmu_recv(struct work_struct *work)
static void static void
nvkm_pmu_intr(struct nvkm_subdev *subdev) nvkm_pmu_intr(struct nvkm_subdev *subdev)
{ {
struct nvkm_pmu *pmu = container_of(subdev, typeof(*pmu), subdev); struct nvkm_pmu *pmu = nvkm_pmu(subdev);
struct nvkm_device *device = pmu->subdev.device; struct nvkm_device *device = pmu->subdev.device;
u32 disp = nvkm_rd32(device, 0x10a01c); u32 disp = nvkm_rd32(device, 0x10a01c);
u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16); u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16);
@ -180,33 +179,23 @@ nvkm_pmu_intr(struct nvkm_subdev *subdev)
} }
} }
int static int
_nvkm_pmu_fini(struct nvkm_object *object, bool suspend) nvkm_pmu_fini(struct nvkm_subdev *subdev, bool suspend)
{ {
struct nvkm_pmu *pmu = (void *)object; struct nvkm_pmu *pmu = nvkm_pmu(subdev);
struct nvkm_device *device = pmu->subdev.device; struct nvkm_device *device = pmu->subdev.device;
nvkm_wr32(device, 0x10a014, 0x00000060); nvkm_wr32(device, 0x10a014, 0x00000060);
flush_work(&pmu->recv.work); flush_work(&pmu->recv.work);
return 0;
return nvkm_subdev_fini_old(&pmu->subdev, suspend);
} }
int static int
_nvkm_pmu_init(struct nvkm_object *object) nvkm_pmu_init(struct nvkm_subdev *subdev)
{ {
const struct nvkm_pmu_impl *impl = (void *)object->oclass; struct nvkm_pmu *pmu = nvkm_pmu(subdev);
struct nvkm_pmu *pmu = (void *)object;
struct nvkm_device *device = pmu->subdev.device; struct nvkm_device *device = pmu->subdev.device;
int ret, i; int i;
ret = nvkm_subdev_init_old(&pmu->subdev);
if (ret)
return ret;
nv_subdev(pmu)->intr = nvkm_pmu_intr;
pmu->message = nvkm_pmu_send;
pmu->pgob = nvkm_pmu_pgob;
/* prevent previous ucode from running, wait for idle, reset */ /* prevent previous ucode from running, wait for idle, reset */
nvkm_wr32(device, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */ nvkm_wr32(device, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
@ -224,15 +213,15 @@ _nvkm_pmu_init(struct nvkm_object *object)
/* upload data segment */ /* upload data segment */
nvkm_wr32(device, 0x10a1c0, 0x01000000); nvkm_wr32(device, 0x10a1c0, 0x01000000);
for (i = 0; i < impl->data.size / 4; i++) for (i = 0; i < pmu->func->data.size / 4; i++)
nvkm_wr32(device, 0x10a1c4, impl->data.data[i]); nvkm_wr32(device, 0x10a1c4, pmu->func->data.data[i]);
/* upload code segment */ /* upload code segment */
nvkm_wr32(device, 0x10a180, 0x01000000); nvkm_wr32(device, 0x10a180, 0x01000000);
for (i = 0; i < impl->code.size / 4; i++) { for (i = 0; i < pmu->func->code.size / 4; i++) {
if ((i & 0x3f) == 0) if ((i & 0x3f) == 0)
nvkm_wr32(device, 0x10a188, i >> 6); nvkm_wr32(device, 0x10a188, i >> 6);
nvkm_wr32(device, 0x10a184, impl->code.data[i]); nvkm_wr32(device, 0x10a184, pmu->func->code.data[i]);
} }
/* start it running */ /* start it running */
@ -262,31 +251,30 @@ _nvkm_pmu_init(struct nvkm_object *object)
return 0; return 0;
} }
static void *
nvkm_pmu_dtor(struct nvkm_subdev *subdev)
{
return nvkm_pmu(subdev);
}
static const struct nvkm_subdev_func
nvkm_pmu = {
.dtor = nvkm_pmu_dtor,
.init = nvkm_pmu_init,
.fini = nvkm_pmu_fini,
.intr = nvkm_pmu_intr,
};
int int
nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_pmu_new_(const struct nvkm_pmu_func *func, struct nvkm_device *device,
struct nvkm_oclass *oclass, int length, void **pobject) int index, struct nvkm_pmu **ppmu)
{ {
struct nvkm_pmu *pmu; struct nvkm_pmu *pmu;
int ret; if (!(pmu = *ppmu = kzalloc(sizeof(*pmu), GFP_KERNEL)))
return -ENOMEM;
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU", nvkm_subdev_ctor(&nvkm_pmu, device, index, 0, &pmu->subdev);
"pmu", length, pobject); pmu->func = func;
pmu = *pobject;
if (ret)
return ret;
INIT_WORK(&pmu->recv.work, nvkm_pmu_recv); INIT_WORK(&pmu->recv.work, nvkm_pmu_recv);
init_waitqueue_head(&pmu->recv.wait); init_waitqueue_head(&pmu->recv.wait);
return 0; return 0;
} }
int
_nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_pmu *pmu;
int ret = nvkm_pmu_create(parent, engine, oclass, &pmu);
*pobject = nv_object(pmu);
return ret;
}

4
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4 → drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4
View File

@ -32,7 +32,7 @@
#include "macros.fuc" #include "macros.fuc"
.section #gf110_pmu_data .section #gf119_pmu_data
#define INCLUDE_PROC #define INCLUDE_PROC
#include "kernel.fuc" #include "kernel.fuc"
#include "arith.fuc" #include "arith.fuc"
@ -56,7 +56,7 @@
#undef INCLUDE_DATA #undef INCLUDE_DATA
.align 256 .align 256
.section #gf110_pmu_code .section #gf119_pmu_code
#define INCLUDE_CODE #define INCLUDE_CODE
#include "kernel.fuc" #include "kernel.fuc"
#include "arith.fuc" #include "arith.fuc"

4
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h → drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h
View File

@ -1,4 +1,4 @@
uint32_t gf110_pmu_data[] = { uint32_t gf119_pmu_data[] = {
/* 0x0000: proc_kern */ /* 0x0000: proc_kern */
0x52544e49, 0x52544e49,
0x00000000, 0x00000000,
@ -915,7 +915,7 @@ uint32_t gf110_pmu_data[] = {
0x00000000, 0x00000000,
}; };
uint32_t gf110_pmu_code[] = { uint32_t gf119_pmu_code[] = {
0x034d0ef5, 0x034d0ef5,
/* 0x0004: rd32 */ /* 0x0004: rd32 */
0x07a007f1, 0x07a007f1,

19
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c
View File

@ -24,17 +24,16 @@
#include "priv.h" #include "priv.h"
#include "fuc/gf100.fuc3.h" #include "fuc/gf100.fuc3.h"
struct nvkm_oclass * static const struct nvkm_pmu_func
gf100_pmu_oclass = &(struct nvkm_pmu_impl) { gf100_pmu = {
.base.handle = NV_SUBDEV(PMU, 0xc0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_pmu_ctor,
.dtor = _nvkm_pmu_dtor,
.init = _nvkm_pmu_init,
.fini = _nvkm_pmu_fini,
},
.code.data = gf100_pmu_code, .code.data = gf100_pmu_code,
.code.size = sizeof(gf100_pmu_code), .code.size = sizeof(gf100_pmu_code),
.data.data = gf100_pmu_data, .data.data = gf100_pmu_data,
.data.size = sizeof(gf100_pmu_data), .data.size = sizeof(gf100_pmu_data),
}.base; };
int
gf100_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
{
return nvkm_pmu_new_(&gf100_pmu, device, index, ppmu);
}

29
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c → drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c
View File

@ -22,19 +22,18 @@
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#include "priv.h" #include "priv.h"
#include "fuc/gf110.fuc4.h" #include "fuc/gf119.fuc4.h"
struct nvkm_oclass * static const struct nvkm_pmu_func
gf110_pmu_oclass = &(struct nvkm_pmu_impl) { gf119_pmu = {
.base.handle = NV_SUBDEV(PMU, 0xd0), .code.data = gf119_pmu_code,
.base.ofuncs = &(struct nvkm_ofuncs) { .code.size = sizeof(gf119_pmu_code),
.ctor = _nvkm_pmu_ctor, .data.data = gf119_pmu_data,
.dtor = _nvkm_pmu_dtor, .data.size = sizeof(gf119_pmu_data),
.init = _nvkm_pmu_init, };
.fini = _nvkm_pmu_fini,
}, int
.code.data = gf110_pmu_code, gf119_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
.code.size = sizeof(gf110_pmu_code), {
.data.data = gf110_pmu_data, return nvkm_pmu_new_(&gf119_pmu, device, index, ppmu);
.data.size = sizeof(gf110_pmu_data), }
}.base;

25
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c
View File

@ -21,10 +21,10 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#define gf110_pmu_code gk104_pmu_code #define gf119_pmu_code gk104_pmu_code
#define gf110_pmu_data gk104_pmu_data #define gf119_pmu_data gk104_pmu_data
#include "priv.h" #include "priv.h"
#include "fuc/gf110.fuc4.h" #include "fuc/gf119.fuc4.h"
#include <core/device.h> #include <core/device.h>
#include <core/option.h> #include <core/option.h>
@ -103,18 +103,17 @@ gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
} }
} }
struct nvkm_oclass * static const struct nvkm_pmu_func
gk104_pmu_oclass = &(struct nvkm_pmu_impl) { gk104_pmu = {
.base.handle = NV_SUBDEV(PMU, 0xe4),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_pmu_ctor,
.dtor = _nvkm_pmu_dtor,
.init = _nvkm_pmu_init,
.fini = _nvkm_pmu_fini,
},
.code.data = gk104_pmu_code, .code.data = gk104_pmu_code,
.code.size = sizeof(gk104_pmu_code), .code.size = sizeof(gk104_pmu_code),
.data.data = gk104_pmu_data, .data.data = gk104_pmu_data,
.data.size = sizeof(gk104_pmu_data), .data.size = sizeof(gk104_pmu_data),
.pgob = gk104_pmu_pgob, .pgob = gk104_pmu_pgob,
}.base; };
int
gk104_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
{
return nvkm_pmu_new_(&gk104_pmu, device, index, ppmu);
}

25
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c
View File

@ -21,10 +21,10 @@
* *
* Authors: Ben Skeggs * Authors: Ben Skeggs
*/ */
#define gf110_pmu_code gk110_pmu_code #define gf119_pmu_code gk110_pmu_code
#define gf110_pmu_data gk110_pmu_data #define gf119_pmu_data gk110_pmu_data
#include "priv.h" #include "priv.h"
#include "fuc/gf110.fuc4.h" #include "fuc/gf119.fuc4.h"
#include <subdev/timer.h> #include <subdev/timer.h>
@ -82,18 +82,17 @@ gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
nvkm_rd32(device, 0x000200); nvkm_rd32(device, 0x000200);
} }
struct nvkm_oclass * static const struct nvkm_pmu_func
gk110_pmu_oclass = &(struct nvkm_pmu_impl) { gk110_pmu = {
.base.handle = NV_SUBDEV(PMU, 0xf0),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_pmu_ctor,
.dtor = _nvkm_pmu_dtor,
.init = _nvkm_pmu_init,
.fini = _nvkm_pmu_fini,
},
.code.data = gk110_pmu_code, .code.data = gk110_pmu_code,
.code.size = sizeof(gk110_pmu_code), .code.size = sizeof(gk110_pmu_code),
.data.data = gk110_pmu_data, .data.data = gk110_pmu_data,
.data.size = sizeof(gk110_pmu_data), .data.size = sizeof(gk110_pmu_data),
.pgob = gk110_pmu_pgob, .pgob = gk110_pmu_pgob,
}.base; };
int
gk110_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
{
return nvkm_pmu_new_(&gk110_pmu, device, index, ppmu);
}

19
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c
View File

@ -24,18 +24,17 @@
#include "priv.h" #include "priv.h"
#include "fuc/gk208.fuc5.h" #include "fuc/gk208.fuc5.h"
struct nvkm_oclass * static const struct nvkm_pmu_func
gk208_pmu_oclass = &(struct nvkm_pmu_impl) { gk208_pmu = {
.base.handle = NV_SUBDEV(PMU, 0x00),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_pmu_ctor,
.dtor = _nvkm_pmu_dtor,
.init = _nvkm_pmu_init,
.fini = _nvkm_pmu_fini,
},
.code.data = gk208_pmu_code, .code.data = gk208_pmu_code,
.code.size = sizeof(gk208_pmu_code), .code.size = sizeof(gk208_pmu_code),
.data.data = gk208_pmu_data, .data.data = gk208_pmu_data,
.data.size = sizeof(gk208_pmu_data), .data.size = sizeof(gk208_pmu_data),
.pgob = gk110_pmu_pgob, .pgob = gk110_pmu_pgob,
}.base; };
int
gk208_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
{
return nvkm_pmu_new_(&gk208_pmu, device, index, ppmu);
}

62
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
View File

@ -19,6 +19,7 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#define gk20a_pmu(p) container_of((p), struct gk20a_pmu, base.subdev)
#include "priv.h" #include "priv.h"
#include <subdev/clk.h> #include <subdev/clk.h>
@ -165,27 +166,24 @@ resched:
} }
static int static int
gk20a_pmu_fini(struct nvkm_object *object, bool suspend) gk20a_pmu_fini(struct nvkm_subdev *subdev, bool suspend)
{ {
struct gk20a_pmu *pmu = (void *)object; struct gk20a_pmu *pmu = gk20a_pmu(subdev);
nvkm_timer_alarm_cancel(pmu, &pmu->alarm); nvkm_timer_alarm_cancel(pmu, &pmu->alarm);
return 0;
}
return nvkm_subdev_fini_old(&pmu->base.subdev, suspend); static void *
gk20a_pmu_dtor(struct nvkm_subdev *subdev)
{
return gk20a_pmu(subdev);
} }
static int static int
gk20a_pmu_init(struct nvkm_object *object) gk20a_pmu_init(struct nvkm_subdev *subdev)
{ {
struct gk20a_pmu *pmu = (void *)object; struct gk20a_pmu *pmu = gk20a_pmu(subdev);
struct nvkm_device *device = pmu->base.subdev.device; struct nvkm_device *device = pmu->base.subdev.device;
int ret;
ret = nvkm_subdev_init_old(&pmu->base.subdev);
if (ret)
return ret;
pmu->base.pgob = nvkm_pmu_pgob;
/* init pwr perf counter */ /* init pwr perf counter */
nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
@ -193,7 +191,7 @@ gk20a_pmu_init(struct nvkm_object *object)
nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
nvkm_timer_alarm(pmu, 2000000000, &pmu->alarm); nvkm_timer_alarm(pmu, 2000000000, &pmu->alarm);
return ret; return 0;
} }
static struct gk20a_pmu_dvfs_data static struct gk20a_pmu_dvfs_data
@ -203,32 +201,26 @@ gk20a_dvfs_data= {
.p_smooth = 1, .p_smooth = 1,
}; };
static int static const struct nvkm_subdev_func
gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk20a_pmu = {
struct nvkm_oclass *oclass, void *data, u32 size, .init = gk20a_pmu_init,
struct nvkm_object **pobject) .fini = gk20a_pmu_fini,
.dtor = gk20a_pmu_dtor,
};
int
gk20a_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
{ {
static const struct nvkm_pmu_func func = {};
struct gk20a_pmu *pmu; struct gk20a_pmu *pmu;
int ret;
ret = nvkm_pmu_create(parent, engine, oclass, &pmu); if (!(pmu = kzalloc(sizeof(*pmu), GFP_KERNEL)))
*pobject = nv_object(pmu); return -ENOMEM;
if (ret) pmu->base.func = &func;
return ret; *ppmu = &pmu->base;
nvkm_subdev_ctor(&gk20a_pmu, device, index, 0, &pmu->base.subdev);
pmu->data = &gk20a_dvfs_data; pmu->data = &gk20a_dvfs_data;
nvkm_alarm_init(&pmu->alarm, gk20a_pmu_dvfs_work); nvkm_alarm_init(&pmu->alarm, gk20a_pmu_dvfs_work);
return 0; return 0;
} }
struct nvkm_oclass *
gk20a_pmu_oclass = &(struct nvkm_pmu_impl) {
.base.handle = NV_SUBDEV(PMU, 0xea),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_pmu_ctor,
.dtor = _nvkm_pmu_dtor,
.init = gk20a_pmu_init,
.fini = gk20a_pmu_fini,
},
}.base;

41
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c Normal file
View File

@ -0,0 +1,41 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
#define gk208_pmu_code gm107_pmu_code
#define gk208_pmu_data gm107_pmu_data
#include "fuc/gk208.fuc5.h"
static const struct nvkm_pmu_func
gm107_pmu = {
.code.data = gm107_pmu_code,
.code.size = sizeof(gm107_pmu_code),
.data.data = gm107_pmu_data,
.data.size = sizeof(gm107_pmu_data),
};
int
gm107_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
{
return nvkm_pmu_new_(&gm107_pmu, device, index, ppmu);
}

26
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
View File

@ -24,27 +24,25 @@
#include "priv.h" #include "priv.h"
#include "fuc/gt215.fuc3.h" #include "fuc/gt215.fuc3.h"
static int static void
gt215_pmu_init(struct nvkm_object *object) gt215_pmu_reset(struct nvkm_pmu *pmu)
{ {
struct nvkm_pmu *pmu = (void *)object;
struct nvkm_device *device = pmu->subdev.device; struct nvkm_device *device = pmu->subdev.device;
nvkm_mask(device, 0x022210, 0x00000001, 0x00000000); nvkm_mask(device, 0x022210, 0x00000001, 0x00000000);
nvkm_mask(device, 0x022210, 0x00000001, 0x00000001); nvkm_mask(device, 0x022210, 0x00000001, 0x00000001);
return nvkm_pmu_init(pmu);
} }
struct nvkm_oclass * static const struct nvkm_pmu_func
gt215_pmu_oclass = &(struct nvkm_pmu_impl) { gt215_pmu = {
.base.handle = NV_SUBDEV(PMU, 0xa3), .reset = gt215_pmu_reset,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_pmu_ctor,
.dtor = _nvkm_pmu_dtor,
.init = gt215_pmu_init,
.fini = _nvkm_pmu_fini,
},
.code.data = gt215_pmu_code, .code.data = gt215_pmu_code,
.code.size = sizeof(gt215_pmu_code), .code.size = sizeof(gt215_pmu_code),
.data.data = gt215_pmu_data, .data.data = gt215_pmu_data,
.data.size = sizeof(gt215_pmu_data), .data.size = sizeof(gt215_pmu_data),
}.base; };
int
gt215_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
{
return nvkm_pmu_new_(&gt215_pmu, device, index, ppmu);
}

12
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c
View File

@ -47,8 +47,8 @@ nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
u32 reply[2]; u32 reply[2];
int ret; int ret;
ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO, ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
MEMX_INFO_DATA, 0); MEMX_INFO_DATA, 0);
if (ret) if (ret)
return ret; return ret;
@ -85,8 +85,8 @@ nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec)
/* call MEMX process to execute the script, and wait for reply */ /* call MEMX process to execute the script, and wait for reply */
if (exec) { if (exec) {
pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC, nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
memx->base, finish); memx->base, finish);
} }
nvkm_debug(subdev, "Exec took %uns, PMU_IN %08x\n", nvkm_debug(subdev, "Exec took %uns, PMU_IN %08x\n",
@ -168,8 +168,8 @@ nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
u32 reply[2], base, size, i; u32 reply[2], base, size, i;
int ret; int ret;
ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO, ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
MEMX_INFO_TRAIN, 0); MEMX_INFO_TRAIN, 0);
if (ret) if (ret)
return ret; return ret;

30
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h
View File

@ -1,38 +1,20 @@
#ifndef __NVKM_PMU_PRIV_H__ #ifndef __NVKM_PMU_PRIV_H__
#define __NVKM_PMU_PRIV_H__ #define __NVKM_PMU_PRIV_H__
#define nvkm_pmu(p) container_of((p), struct nvkm_pmu, subdev)
#include <subdev/pmu.h> #include <subdev/pmu.h>
#include <subdev/pmu/fuc/os.h> #include <subdev/pmu/fuc/os.h>
#define nvkm_pmu_create(p, e, o, d) \ int nvkm_pmu_new_(const struct nvkm_pmu_func *, struct nvkm_device *,
nvkm_pmu_create_((p), (e), (o), sizeof(**d), (void **)d) int index, struct nvkm_pmu **);
#define nvkm_pmu_destroy(p) \
nvkm_subdev_destroy(&(p)->base)
#define nvkm_pmu_init(p) ({ \
struct nvkm_pmu *_pmu = (p); \
_nvkm_pmu_init(nv_object(_pmu)); \
})
#define nvkm_pmu_fini(p,s) ({ \
struct nvkm_pmu *_pmu = (p); \
_nvkm_pmu_fini(nv_object(_pmu), (s)); \
})
int nvkm_pmu_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_pmu_func {
struct nvkm_oclass *, int, void **); void (*reset)(struct nvkm_pmu *);
int _nvkm_pmu_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
#define _nvkm_pmu_dtor _nvkm_subdev_dtor
int _nvkm_pmu_init(struct nvkm_object *);
int _nvkm_pmu_fini(struct nvkm_object *, bool);
void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable);
struct nvkm_pmu_impl {
struct nvkm_oclass base;
struct { struct {
u32 *data; u32 *data;
u32 size; u32 size;
} code; } code;
struct { struct {
u32 *data; u32 *data;
u32 size; u32 size;