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drm/nouveau/pmu: convert to new-style nvkm_subdev
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
a4f7bd3608
commit
e2ca4e7d6e
@ -3,6 +3,7 @@
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#include <core/subdev.h>
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struct nvkm_pmu {
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const struct nvkm_pmu_func *func;
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struct nvkm_subdev subdev;
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struct {
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@ -20,24 +21,20 @@ struct nvkm_pmu {
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u32 message;
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u32 data[2];
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} recv;
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int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32);
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void (*pgob)(struct nvkm_pmu *, bool);
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};
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static inline struct nvkm_pmu *
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nvkm_pmu(void *obj)
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{
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return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU);
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}
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int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process,
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u32 message, u32 data0, u32 data1);
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void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable);
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extern struct nvkm_oclass *gt215_pmu_oclass;
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extern struct nvkm_oclass *gf100_pmu_oclass;
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extern struct nvkm_oclass *gf110_pmu_oclass;
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extern struct nvkm_oclass *gk104_pmu_oclass;
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extern struct nvkm_oclass *gk110_pmu_oclass;
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extern struct nvkm_oclass *gk208_pmu_oclass;
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extern struct nvkm_oclass *gk20a_pmu_oclass;
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int gt215_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
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int gf100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
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int gf119_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
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int gk104_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
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int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
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int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
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int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
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int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **);
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/* interface to MEMX process running on PMU */
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struct nvkm_memx;
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@ -1111,7 +1111,7 @@ nva3_chipset = {
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.mc = g98_mc_new,
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.mmu = nv50_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gt215_pmu_new,
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.pmu = gt215_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1144,7 +1144,7 @@ nva5_chipset = {
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.mc = g98_mc_new,
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.mmu = nv50_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gt215_pmu_new,
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.pmu = gt215_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1176,7 +1176,7 @@ nva8_chipset = {
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.mc = g98_mc_new,
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.mmu = nv50_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gt215_pmu_new,
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.pmu = gt215_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1270,7 +1270,7 @@ nvaf_chipset = {
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.mc = g98_mc_new,
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.mmu = nv50_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gt215_pmu_new,
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.pmu = gt215_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1304,7 +1304,7 @@ nvc0_chipset = {
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.mc = gf100_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf100_pmu_new,
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.pmu = gf100_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1339,7 +1339,7 @@ nvc1_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf100_pmu_new,
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.pmu = gf100_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1373,7 +1373,7 @@ nvc3_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf100_pmu_new,
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.pmu = gf100_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1407,7 +1407,7 @@ nvc4_chipset = {
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.mc = gf100_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf100_pmu_new,
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.pmu = gf100_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1442,7 +1442,7 @@ nvc8_chipset = {
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.mc = gf100_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf100_pmu_new,
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.pmu = gf100_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1477,7 +1477,7 @@ nvce_chipset = {
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.mc = gf100_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf100_pmu_new,
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.pmu = gf100_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1512,7 +1512,7 @@ nvcf_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf100_pmu_new,
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.pmu = gf100_pmu_new,
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// .therm = gt215_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1578,7 +1578,7 @@ nvd9_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf110_pmu_new,
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.pmu = gf119_pmu_new,
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// .therm = gf110_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1612,7 +1612,7 @@ nve4_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk104_pmu_new,
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.pmu = gk104_pmu_new,
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// .therm = gf110_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1648,7 +1648,7 @@ nve6_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk104_pmu_new,
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.pmu = gk104_pmu_new,
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// .therm = gf110_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1684,7 +1684,7 @@ nve7_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gf110_pmu_new,
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.pmu = gf119_pmu_new,
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// .therm = gf110_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1715,7 +1715,7 @@ nvea_chipset = {
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.ltc = gk104_ltc_new,
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.mc = gk20a_mc_new,
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.mmu = gf100_mmu_new,
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// .pmu = gk20a_pmu_new,
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.pmu = gk20a_pmu_new,
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// .timer = gk20a_timer_new,
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// .volt = gk20a_volt_new,
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// .ce[2] = gk104_ce2_new,
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@ -1744,7 +1744,7 @@ nvf0_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk110_pmu_new,
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.pmu = gk110_pmu_new,
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// .therm = gf110_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1780,7 +1780,7 @@ nvf1_chipset = {
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.mc = gf106_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk110_pmu_new,
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.pmu = gk110_pmu_new,
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// .therm = gf110_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1816,7 +1816,7 @@ nv106_chipset = {
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.mc = gk20a_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk208_pmu_new,
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.pmu = gk208_pmu_new,
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// .therm = gf110_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1851,7 +1851,7 @@ nv108_chipset = {
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.mc = gk20a_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk208_pmu_new,
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.pmu = gk208_pmu_new,
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// .therm = gf110_therm_new,
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// .timer = nv04_timer_new,
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// .volt = nv40_volt_new,
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@ -1886,7 +1886,7 @@ nv117_chipset = {
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.mc = gk20a_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk208_pmu_new,
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.pmu = gm107_pmu_new,
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// .therm = gm107_therm_new,
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// .timer = gk20a_timer_new,
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// .ce[0] = gk104_ce0_new,
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@ -1915,7 +1915,7 @@ nv124_chipset = {
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.mc = gk20a_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk208_pmu_new,
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.pmu = gm107_pmu_new,
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// .timer = gk20a_timer_new,
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// .ce[0] = gm204_ce0_new,
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// .ce[1] = gm204_ce1_new,
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@ -1944,7 +1944,7 @@ nv126_chipset = {
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.mc = gk20a_mc_new,
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.mmu = gf100_mmu_new,
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.mxm = nv50_mxm_new,
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// .pmu = gk208_pmu_new,
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.pmu = gm107_pmu_new,
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// .timer = gk20a_timer_new,
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// .ce[0] = gm204_ce0_new,
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// .ce[1] = gm204_ce1_new,
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@ -30,7 +30,6 @@ gf100_identify(struct nvkm_device *device)
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case 0xc0:
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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@ -47,7 +46,6 @@ gf100_identify(struct nvkm_device *device)
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case 0xc4:
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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@ -64,7 +62,6 @@ gf100_identify(struct nvkm_device *device)
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case 0xc3:
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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@ -80,7 +77,6 @@ gf100_identify(struct nvkm_device *device)
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case 0xce:
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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@ -97,7 +93,6 @@ gf100_identify(struct nvkm_device *device)
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case 0xcf:
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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@ -113,7 +108,6 @@ gf100_identify(struct nvkm_device *device)
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case 0xc1:
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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@ -129,7 +123,6 @@ gf100_identify(struct nvkm_device *device)
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case 0xc8:
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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@ -146,7 +139,6 @@ gf100_identify(struct nvkm_device *device)
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case 0xd9:
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device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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@ -30,7 +30,6 @@ gk104_identify(struct nvkm_device *device)
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case 0xe4:
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device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
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@ -48,7 +47,6 @@ gk104_identify(struct nvkm_device *device)
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case 0xe7:
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device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
|
||||
@ -66,7 +64,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
case 0xe6:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
|
||||
@ -90,12 +87,10 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
|
||||
break;
|
||||
case 0xf0:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
|
||||
@ -113,7 +108,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
case 0xf1:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
|
||||
@ -131,7 +125,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
case 0x106:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
|
||||
@ -148,7 +141,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
case 0x108:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
|
||||
|
@ -30,7 +30,6 @@ gm100_identify(struct nvkm_device *device)
|
||||
case 0x117:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
|
||||
#if 0
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
@ -58,7 +57,6 @@ gm100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
|
||||
#endif
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
#if 0
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
#endif
|
||||
@ -83,7 +81,6 @@ gm100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
|
||||
#endif
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
#if 0
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
#endif
|
||||
|
@ -177,7 +177,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
case 0xa3:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -194,7 +193,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
case 0xa5:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -210,7 +208,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
case 0xa8:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -226,7 +223,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
case 0xaf:
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
|
@ -185,15 +185,13 @@ gk104_gr_init(struct nvkm_object *object)
|
||||
struct gf100_gr_oclass *oclass = (void *)object->oclass;
|
||||
struct gf100_gr *gr = (void *)object;
|
||||
struct nvkm_device *device = gr->base.engine.subdev.device;
|
||||
struct nvkm_pmu *pmu = device->pmu;
|
||||
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
|
||||
u32 data[TPC_MAX / 8] = {};
|
||||
u8 tpcnr[GPC_MAX];
|
||||
int gpc, tpc, rop;
|
||||
int ret, i;
|
||||
|
||||
if (pmu)
|
||||
pmu->pgob(pmu, false);
|
||||
nvkm_pmu_pgob(device->pmu, false);
|
||||
|
||||
ret = nvkm_gr_init(&gr->base);
|
||||
if (ret)
|
||||
@ -315,9 +313,8 @@ gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nvkm_pmu *pmu = nvkm_pmu(parent);
|
||||
if (pmu)
|
||||
pmu->pgob(pmu, false);
|
||||
struct nvkm_device *device = (void *)parent;
|
||||
nvkm_pmu_pgob(device->pmu, false);
|
||||
return gf100_gr_ctor(parent, engine, oclass, data, size, pobject);
|
||||
}
|
||||
|
||||
|
@ -2,8 +2,9 @@ nvkm-y += nvkm/subdev/pmu/base.o
|
||||
nvkm-y += nvkm/subdev/pmu/memx.o
|
||||
nvkm-y += nvkm/subdev/pmu/gt215.o
|
||||
nvkm-y += nvkm/subdev/pmu/gf100.o
|
||||
nvkm-y += nvkm/subdev/pmu/gf110.o
|
||||
nvkm-y += nvkm/subdev/pmu/gf119.o
|
||||
nvkm-y += nvkm/subdev/pmu/gk104.o
|
||||
nvkm-y += nvkm/subdev/pmu/gk110.o
|
||||
nvkm-y += nvkm/subdev/pmu/gk208.o
|
||||
nvkm-y += nvkm/subdev/pmu/gk20a.o
|
||||
nvkm-y += nvkm/subdev/pmu/gm107.o
|
||||
|
@ -28,12 +28,11 @@
|
||||
void
|
||||
nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
|
||||
{
|
||||
const struct nvkm_pmu_impl *impl = (void *)nv_oclass(pmu);
|
||||
if (impl->pgob)
|
||||
impl->pgob(pmu, enable);
|
||||
if (pmu->func->pgob)
|
||||
pmu->func->pgob(pmu, enable);
|
||||
}
|
||||
|
||||
static int
|
||||
int
|
||||
nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
|
||||
u32 process, u32 message, u32 data0, u32 data1)
|
||||
{
|
||||
@ -144,7 +143,7 @@ nvkm_pmu_recv(struct work_struct *work)
|
||||
static void
|
||||
nvkm_pmu_intr(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nvkm_pmu *pmu = container_of(subdev, typeof(*pmu), subdev);
|
||||
struct nvkm_pmu *pmu = nvkm_pmu(subdev);
|
||||
struct nvkm_device *device = pmu->subdev.device;
|
||||
u32 disp = nvkm_rd32(device, 0x10a01c);
|
||||
u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16);
|
||||
@ -180,33 +179,23 @@ nvkm_pmu_intr(struct nvkm_subdev *subdev)
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
_nvkm_pmu_fini(struct nvkm_object *object, bool suspend)
|
||||
static int
|
||||
nvkm_pmu_fini(struct nvkm_subdev *subdev, bool suspend)
|
||||
{
|
||||
struct nvkm_pmu *pmu = (void *)object;
|
||||
struct nvkm_pmu *pmu = nvkm_pmu(subdev);
|
||||
struct nvkm_device *device = pmu->subdev.device;
|
||||
|
||||
nvkm_wr32(device, 0x10a014, 0x00000060);
|
||||
flush_work(&pmu->recv.work);
|
||||
|
||||
return nvkm_subdev_fini_old(&pmu->subdev, suspend);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
_nvkm_pmu_init(struct nvkm_object *object)
|
||||
static int
|
||||
nvkm_pmu_init(struct nvkm_subdev *subdev)
|
||||
{
|
||||
const struct nvkm_pmu_impl *impl = (void *)object->oclass;
|
||||
struct nvkm_pmu *pmu = (void *)object;
|
||||
struct nvkm_pmu *pmu = nvkm_pmu(subdev);
|
||||
struct nvkm_device *device = pmu->subdev.device;
|
||||
int ret, i;
|
||||
|
||||
ret = nvkm_subdev_init_old(&pmu->subdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_subdev(pmu)->intr = nvkm_pmu_intr;
|
||||
pmu->message = nvkm_pmu_send;
|
||||
pmu->pgob = nvkm_pmu_pgob;
|
||||
int i;
|
||||
|
||||
/* prevent previous ucode from running, wait for idle, reset */
|
||||
nvkm_wr32(device, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
|
||||
@ -224,15 +213,15 @@ _nvkm_pmu_init(struct nvkm_object *object)
|
||||
|
||||
/* upload data segment */
|
||||
nvkm_wr32(device, 0x10a1c0, 0x01000000);
|
||||
for (i = 0; i < impl->data.size / 4; i++)
|
||||
nvkm_wr32(device, 0x10a1c4, impl->data.data[i]);
|
||||
for (i = 0; i < pmu->func->data.size / 4; i++)
|
||||
nvkm_wr32(device, 0x10a1c4, pmu->func->data.data[i]);
|
||||
|
||||
/* upload code segment */
|
||||
nvkm_wr32(device, 0x10a180, 0x01000000);
|
||||
for (i = 0; i < impl->code.size / 4; i++) {
|
||||
for (i = 0; i < pmu->func->code.size / 4; i++) {
|
||||
if ((i & 0x3f) == 0)
|
||||
nvkm_wr32(device, 0x10a188, i >> 6);
|
||||
nvkm_wr32(device, 0x10a184, impl->code.data[i]);
|
||||
nvkm_wr32(device, 0x10a184, pmu->func->code.data[i]);
|
||||
}
|
||||
|
||||
/* start it running */
|
||||
@ -262,31 +251,30 @@ _nvkm_pmu_init(struct nvkm_object *object)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *
|
||||
nvkm_pmu_dtor(struct nvkm_subdev *subdev)
|
||||
{
|
||||
return nvkm_pmu(subdev);
|
||||
}
|
||||
|
||||
static const struct nvkm_subdev_func
|
||||
nvkm_pmu = {
|
||||
.dtor = nvkm_pmu_dtor,
|
||||
.init = nvkm_pmu_init,
|
||||
.fini = nvkm_pmu_fini,
|
||||
.intr = nvkm_pmu_intr,
|
||||
};
|
||||
|
||||
int
|
||||
nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, int length, void **pobject)
|
||||
nvkm_pmu_new_(const struct nvkm_pmu_func *func, struct nvkm_device *device,
|
||||
int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
struct nvkm_pmu *pmu;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU",
|
||||
"pmu", length, pobject);
|
||||
pmu = *pobject;
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!(pmu = *ppmu = kzalloc(sizeof(*pmu), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
nvkm_subdev_ctor(&nvkm_pmu, device, index, 0, &pmu->subdev);
|
||||
pmu->func = func;
|
||||
INIT_WORK(&pmu->recv.work, nvkm_pmu_recv);
|
||||
init_waitqueue_head(&pmu->recv.wait);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
_nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
struct nvkm_pmu *pmu;
|
||||
int ret = nvkm_pmu_create(parent, engine, oclass, &pmu);
|
||||
*pobject = nv_object(pmu);
|
||||
return ret;
|
||||
}
|
||||
|
@ -32,7 +32,7 @@
|
||||
|
||||
#include "macros.fuc"
|
||||
|
||||
.section #gf110_pmu_data
|
||||
.section #gf119_pmu_data
|
||||
#define INCLUDE_PROC
|
||||
#include "kernel.fuc"
|
||||
#include "arith.fuc"
|
||||
@ -56,7 +56,7 @@
|
||||
#undef INCLUDE_DATA
|
||||
.align 256
|
||||
|
||||
.section #gf110_pmu_code
|
||||
.section #gf119_pmu_code
|
||||
#define INCLUDE_CODE
|
||||
#include "kernel.fuc"
|
||||
#include "arith.fuc"
|
@ -1,4 +1,4 @@
|
||||
uint32_t gf110_pmu_data[] = {
|
||||
uint32_t gf119_pmu_data[] = {
|
||||
/* 0x0000: proc_kern */
|
||||
0x52544e49,
|
||||
0x00000000,
|
||||
@ -915,7 +915,7 @@ uint32_t gf110_pmu_data[] = {
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
uint32_t gf110_pmu_code[] = {
|
||||
uint32_t gf119_pmu_code[] = {
|
||||
0x034d0ef5,
|
||||
/* 0x0004: rd32 */
|
||||
0x07a007f1,
|
@ -24,17 +24,16 @@
|
||||
#include "priv.h"
|
||||
#include "fuc/gf100.fuc3.h"
|
||||
|
||||
struct nvkm_oclass *
|
||||
gf100_pmu_oclass = &(struct nvkm_pmu_impl) {
|
||||
.base.handle = NV_SUBDEV(PMU, 0xc0),
|
||||
.base.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = _nvkm_pmu_ctor,
|
||||
.dtor = _nvkm_pmu_dtor,
|
||||
.init = _nvkm_pmu_init,
|
||||
.fini = _nvkm_pmu_fini,
|
||||
},
|
||||
static const struct nvkm_pmu_func
|
||||
gf100_pmu = {
|
||||
.code.data = gf100_pmu_code,
|
||||
.code.size = sizeof(gf100_pmu_code),
|
||||
.data.data = gf100_pmu_data,
|
||||
.data.size = sizeof(gf100_pmu_data),
|
||||
}.base;
|
||||
};
|
||||
|
||||
int
|
||||
gf100_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
return nvkm_pmu_new_(&gf100_pmu, device, index, ppmu);
|
||||
}
|
||||
|
@ -22,19 +22,18 @@
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "priv.h"
|
||||
#include "fuc/gf110.fuc4.h"
|
||||
#include "fuc/gf119.fuc4.h"
|
||||
|
||||
struct nvkm_oclass *
|
||||
gf110_pmu_oclass = &(struct nvkm_pmu_impl) {
|
||||
.base.handle = NV_SUBDEV(PMU, 0xd0),
|
||||
.base.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = _nvkm_pmu_ctor,
|
||||
.dtor = _nvkm_pmu_dtor,
|
||||
.init = _nvkm_pmu_init,
|
||||
.fini = _nvkm_pmu_fini,
|
||||
},
|
||||
.code.data = gf110_pmu_code,
|
||||
.code.size = sizeof(gf110_pmu_code),
|
||||
.data.data = gf110_pmu_data,
|
||||
.data.size = sizeof(gf110_pmu_data),
|
||||
}.base;
|
||||
static const struct nvkm_pmu_func
|
||||
gf119_pmu = {
|
||||
.code.data = gf119_pmu_code,
|
||||
.code.size = sizeof(gf119_pmu_code),
|
||||
.data.data = gf119_pmu_data,
|
||||
.data.size = sizeof(gf119_pmu_data),
|
||||
};
|
||||
|
||||
int
|
||||
gf119_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
return nvkm_pmu_new_(&gf119_pmu, device, index, ppmu);
|
||||
}
|
@ -21,10 +21,10 @@
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#define gf110_pmu_code gk104_pmu_code
|
||||
#define gf110_pmu_data gk104_pmu_data
|
||||
#define gf119_pmu_code gk104_pmu_code
|
||||
#define gf119_pmu_data gk104_pmu_data
|
||||
#include "priv.h"
|
||||
#include "fuc/gf110.fuc4.h"
|
||||
#include "fuc/gf119.fuc4.h"
|
||||
|
||||
#include <core/device.h>
|
||||
#include <core/option.h>
|
||||
@ -103,18 +103,17 @@ gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
|
||||
}
|
||||
}
|
||||
|
||||
struct nvkm_oclass *
|
||||
gk104_pmu_oclass = &(struct nvkm_pmu_impl) {
|
||||
.base.handle = NV_SUBDEV(PMU, 0xe4),
|
||||
.base.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = _nvkm_pmu_ctor,
|
||||
.dtor = _nvkm_pmu_dtor,
|
||||
.init = _nvkm_pmu_init,
|
||||
.fini = _nvkm_pmu_fini,
|
||||
},
|
||||
static const struct nvkm_pmu_func
|
||||
gk104_pmu = {
|
||||
.code.data = gk104_pmu_code,
|
||||
.code.size = sizeof(gk104_pmu_code),
|
||||
.data.data = gk104_pmu_data,
|
||||
.data.size = sizeof(gk104_pmu_data),
|
||||
.pgob = gk104_pmu_pgob,
|
||||
}.base;
|
||||
};
|
||||
|
||||
int
|
||||
gk104_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
return nvkm_pmu_new_(&gk104_pmu, device, index, ppmu);
|
||||
}
|
||||
|
@ -21,10 +21,10 @@
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#define gf110_pmu_code gk110_pmu_code
|
||||
#define gf110_pmu_data gk110_pmu_data
|
||||
#define gf119_pmu_code gk110_pmu_code
|
||||
#define gf119_pmu_data gk110_pmu_data
|
||||
#include "priv.h"
|
||||
#include "fuc/gf110.fuc4.h"
|
||||
#include "fuc/gf119.fuc4.h"
|
||||
|
||||
#include <subdev/timer.h>
|
||||
|
||||
@ -82,18 +82,17 @@ gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
|
||||
nvkm_rd32(device, 0x000200);
|
||||
}
|
||||
|
||||
struct nvkm_oclass *
|
||||
gk110_pmu_oclass = &(struct nvkm_pmu_impl) {
|
||||
.base.handle = NV_SUBDEV(PMU, 0xf0),
|
||||
.base.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = _nvkm_pmu_ctor,
|
||||
.dtor = _nvkm_pmu_dtor,
|
||||
.init = _nvkm_pmu_init,
|
||||
.fini = _nvkm_pmu_fini,
|
||||
},
|
||||
static const struct nvkm_pmu_func
|
||||
gk110_pmu = {
|
||||
.code.data = gk110_pmu_code,
|
||||
.code.size = sizeof(gk110_pmu_code),
|
||||
.data.data = gk110_pmu_data,
|
||||
.data.size = sizeof(gk110_pmu_data),
|
||||
.pgob = gk110_pmu_pgob,
|
||||
}.base;
|
||||
};
|
||||
|
||||
int
|
||||
gk110_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
return nvkm_pmu_new_(&gk110_pmu, device, index, ppmu);
|
||||
}
|
||||
|
@ -24,18 +24,17 @@
|
||||
#include "priv.h"
|
||||
#include "fuc/gk208.fuc5.h"
|
||||
|
||||
struct nvkm_oclass *
|
||||
gk208_pmu_oclass = &(struct nvkm_pmu_impl) {
|
||||
.base.handle = NV_SUBDEV(PMU, 0x00),
|
||||
.base.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = _nvkm_pmu_ctor,
|
||||
.dtor = _nvkm_pmu_dtor,
|
||||
.init = _nvkm_pmu_init,
|
||||
.fini = _nvkm_pmu_fini,
|
||||
},
|
||||
static const struct nvkm_pmu_func
|
||||
gk208_pmu = {
|
||||
.code.data = gk208_pmu_code,
|
||||
.code.size = sizeof(gk208_pmu_code),
|
||||
.data.data = gk208_pmu_data,
|
||||
.data.size = sizeof(gk208_pmu_data),
|
||||
.pgob = gk110_pmu_pgob,
|
||||
}.base;
|
||||
};
|
||||
|
||||
int
|
||||
gk208_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
return nvkm_pmu_new_(&gk208_pmu, device, index, ppmu);
|
||||
}
|
||||
|
@ -19,6 +19,7 @@
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#define gk20a_pmu(p) container_of((p), struct gk20a_pmu, base.subdev)
|
||||
#include "priv.h"
|
||||
|
||||
#include <subdev/clk.h>
|
||||
@ -165,27 +166,24 @@ resched:
|
||||
}
|
||||
|
||||
static int
|
||||
gk20a_pmu_fini(struct nvkm_object *object, bool suspend)
|
||||
gk20a_pmu_fini(struct nvkm_subdev *subdev, bool suspend)
|
||||
{
|
||||
struct gk20a_pmu *pmu = (void *)object;
|
||||
|
||||
struct gk20a_pmu *pmu = gk20a_pmu(subdev);
|
||||
nvkm_timer_alarm_cancel(pmu, &pmu->alarm);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return nvkm_subdev_fini_old(&pmu->base.subdev, suspend);
|
||||
static void *
|
||||
gk20a_pmu_dtor(struct nvkm_subdev *subdev)
|
||||
{
|
||||
return gk20a_pmu(subdev);
|
||||
}
|
||||
|
||||
static int
|
||||
gk20a_pmu_init(struct nvkm_object *object)
|
||||
gk20a_pmu_init(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct gk20a_pmu *pmu = (void *)object;
|
||||
struct gk20a_pmu *pmu = gk20a_pmu(subdev);
|
||||
struct nvkm_device *device = pmu->base.subdev.device;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_subdev_init_old(&pmu->base.subdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmu->base.pgob = nvkm_pmu_pgob;
|
||||
|
||||
/* init pwr perf counter */
|
||||
nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
|
||||
@ -193,7 +191,7 @@ gk20a_pmu_init(struct nvkm_object *object)
|
||||
nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
|
||||
|
||||
nvkm_timer_alarm(pmu, 2000000000, &pmu->alarm);
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct gk20a_pmu_dvfs_data
|
||||
@ -203,32 +201,26 @@ gk20a_dvfs_data= {
|
||||
.p_smooth = 1,
|
||||
};
|
||||
|
||||
static int
|
||||
gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
static const struct nvkm_subdev_func
|
||||
gk20a_pmu = {
|
||||
.init = gk20a_pmu_init,
|
||||
.fini = gk20a_pmu_fini,
|
||||
.dtor = gk20a_pmu_dtor,
|
||||
};
|
||||
|
||||
int
|
||||
gk20a_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
static const struct nvkm_pmu_func func = {};
|
||||
struct gk20a_pmu *pmu;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_pmu_create(parent, engine, oclass, &pmu);
|
||||
*pobject = nv_object(pmu);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (!(pmu = kzalloc(sizeof(*pmu), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
pmu->base.func = &func;
|
||||
*ppmu = &pmu->base;
|
||||
|
||||
nvkm_subdev_ctor(&gk20a_pmu, device, index, 0, &pmu->base.subdev);
|
||||
pmu->data = &gk20a_dvfs_data;
|
||||
|
||||
nvkm_alarm_init(&pmu->alarm, gk20a_pmu_dvfs_work);
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nvkm_oclass *
|
||||
gk20a_pmu_oclass = &(struct nvkm_pmu_impl) {
|
||||
.base.handle = NV_SUBDEV(PMU, 0xea),
|
||||
.base.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = gk20a_pmu_ctor,
|
||||
.dtor = _nvkm_pmu_dtor,
|
||||
.init = gk20a_pmu_init,
|
||||
.fini = gk20a_pmu_fini,
|
||||
},
|
||||
}.base;
|
||||
|
41
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c
Normal file
41
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright 2013 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "priv.h"
|
||||
#define gk208_pmu_code gm107_pmu_code
|
||||
#define gk208_pmu_data gm107_pmu_data
|
||||
#include "fuc/gk208.fuc5.h"
|
||||
|
||||
static const struct nvkm_pmu_func
|
||||
gm107_pmu = {
|
||||
.code.data = gm107_pmu_code,
|
||||
.code.size = sizeof(gm107_pmu_code),
|
||||
.data.data = gm107_pmu_data,
|
||||
.data.size = sizeof(gm107_pmu_data),
|
||||
};
|
||||
|
||||
int
|
||||
gm107_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
return nvkm_pmu_new_(&gm107_pmu, device, index, ppmu);
|
||||
}
|
@ -24,27 +24,25 @@
|
||||
#include "priv.h"
|
||||
#include "fuc/gt215.fuc3.h"
|
||||
|
||||
static int
|
||||
gt215_pmu_init(struct nvkm_object *object)
|
||||
static void
|
||||
gt215_pmu_reset(struct nvkm_pmu *pmu)
|
||||
{
|
||||
struct nvkm_pmu *pmu = (void *)object;
|
||||
struct nvkm_device *device = pmu->subdev.device;
|
||||
nvkm_mask(device, 0x022210, 0x00000001, 0x00000000);
|
||||
nvkm_mask(device, 0x022210, 0x00000001, 0x00000001);
|
||||
return nvkm_pmu_init(pmu);
|
||||
}
|
||||
|
||||
struct nvkm_oclass *
|
||||
gt215_pmu_oclass = &(struct nvkm_pmu_impl) {
|
||||
.base.handle = NV_SUBDEV(PMU, 0xa3),
|
||||
.base.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = _nvkm_pmu_ctor,
|
||||
.dtor = _nvkm_pmu_dtor,
|
||||
.init = gt215_pmu_init,
|
||||
.fini = _nvkm_pmu_fini,
|
||||
},
|
||||
static const struct nvkm_pmu_func
|
||||
gt215_pmu = {
|
||||
.reset = gt215_pmu_reset,
|
||||
.code.data = gt215_pmu_code,
|
||||
.code.size = sizeof(gt215_pmu_code),
|
||||
.data.data = gt215_pmu_data,
|
||||
.data.size = sizeof(gt215_pmu_data),
|
||||
}.base;
|
||||
};
|
||||
|
||||
int
|
||||
gt215_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
|
||||
{
|
||||
return nvkm_pmu_new_(>215_pmu, device, index, ppmu);
|
||||
}
|
||||
|
@ -47,8 +47,8 @@ nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
|
||||
u32 reply[2];
|
||||
int ret;
|
||||
|
||||
ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
|
||||
MEMX_INFO_DATA, 0);
|
||||
ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
|
||||
MEMX_INFO_DATA, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -85,8 +85,8 @@ nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec)
|
||||
|
||||
/* call MEMX process to execute the script, and wait for reply */
|
||||
if (exec) {
|
||||
pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
|
||||
memx->base, finish);
|
||||
nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
|
||||
memx->base, finish);
|
||||
}
|
||||
|
||||
nvkm_debug(subdev, "Exec took %uns, PMU_IN %08x\n",
|
||||
@ -168,8 +168,8 @@ nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
|
||||
u32 reply[2], base, size, i;
|
||||
int ret;
|
||||
|
||||
ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
|
||||
MEMX_INFO_TRAIN, 0);
|
||||
ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
|
||||
MEMX_INFO_TRAIN, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -1,38 +1,20 @@
|
||||
#ifndef __NVKM_PMU_PRIV_H__
|
||||
#define __NVKM_PMU_PRIV_H__
|
||||
#define nvkm_pmu(p) container_of((p), struct nvkm_pmu, subdev)
|
||||
#include <subdev/pmu.h>
|
||||
#include <subdev/pmu/fuc/os.h>
|
||||
|
||||
#define nvkm_pmu_create(p, e, o, d) \
|
||||
nvkm_pmu_create_((p), (e), (o), sizeof(**d), (void **)d)
|
||||
#define nvkm_pmu_destroy(p) \
|
||||
nvkm_subdev_destroy(&(p)->base)
|
||||
#define nvkm_pmu_init(p) ({ \
|
||||
struct nvkm_pmu *_pmu = (p); \
|
||||
_nvkm_pmu_init(nv_object(_pmu)); \
|
||||
})
|
||||
#define nvkm_pmu_fini(p,s) ({ \
|
||||
struct nvkm_pmu *_pmu = (p); \
|
||||
_nvkm_pmu_fini(nv_object(_pmu), (s)); \
|
||||
})
|
||||
int nvkm_pmu_new_(const struct nvkm_pmu_func *, struct nvkm_device *,
|
||||
int index, struct nvkm_pmu **);
|
||||
|
||||
int nvkm_pmu_create_(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, int, void **);
|
||||
struct nvkm_pmu_func {
|
||||
void (*reset)(struct nvkm_pmu *);
|
||||
|
||||
int _nvkm_pmu_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, void *, u32,
|
||||
struct nvkm_object **);
|
||||
#define _nvkm_pmu_dtor _nvkm_subdev_dtor
|
||||
int _nvkm_pmu_init(struct nvkm_object *);
|
||||
int _nvkm_pmu_fini(struct nvkm_object *, bool);
|
||||
void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable);
|
||||
|
||||
struct nvkm_pmu_impl {
|
||||
struct nvkm_oclass base;
|
||||
struct {
|
||||
u32 *data;
|
||||
u32 size;
|
||||
} code;
|
||||
|
||||
struct {
|
||||
u32 *data;
|
||||
u32 size;
|
||||
|
Loading…
Reference in New Issue
Block a user