mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-11 21:38:32 +08:00
Hi3798CV200 clock driver updates for 4.17:
- Add COMBPHY0 and USB2_OTG_UTMI clock support.
- Correct the parent clock of HISTB_IR_CLK.
- Fix unregister call sequence in hi3798cv200_clk_register() function.
- A coding-style improvement on Hi3798CV200 driver code indent.
- Add a HiSilicon specific phase clock type and using the type for eMMC
clocks on Hi3798CV200.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJapjczAAoJEFBXWFqHsHzOZt8H/RXGC7Ir7Y4TRtdj91R9UsQf
PsPHUqznHWvBKlHWRIKZWBlT+q3n9wDPlTl5o2iA+7KqV2cfK6Em+a6e/DHnTQ5l
jPo9h25bPAyY4g5l+1SdqiKCBAwG8rSIpzHoJl36AwdGzOxeNnhQX/NZSdqrNOGe
9VSrTMYQ1tnwlTuqnbql8uzwufYVJ3ZnVSV1SwibM1TeSGuAAP//tg4crOPwrzL9
xQbvsO03/ifD+Yzb/NkLjeimkRv8Poh9Ilyn8C8tF9dKIwiC8ZabluEGFYdC0mo7
XcFmX8sRTtgDtum8dDsDokQ2aGPdIgcdW0lPuinGuOeDGgIc/u1dBP33ibvjzr4=
=5Se1
-----END PGP SIGNATURE-----
Merge tag 'clk-hi3798cv200-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-hisi
Pull Hi3798CV200 clock driver updates for 4.17 from Shawn Guo:
- Add COMBPHY0 and USB2_OTG_UTMI clock support.
- Correct the parent clock of HISTB_IR_CLK.
- Fix unregister call sequence in hi3798cv200_clk_register() function.
- A coding-style improvement on Hi3798CV200 driver code indent.
- Add a HiSilicon specific phase clock type and using the type for eMMC
clocks on Hi3798CV200.
* tag 'clk-hi3798cv200-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
clk: hi3798cv200: add emmc sample and drive clock
clk: hisilicon: add hisi phase clock support
clk: hi3798cv200: add COMBPHY0 clock support
clk: hi3798cv200: fix define indentation
clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
clk: hi3798cv200: correct IR clock parent
clk: hi3798cv200: fix unregister call sequence in error path
This commit is contained in:
Stephen Boyd
commit
e26a20339d
@ -3,7 +3,7 @@
|
||||
# Hisilicon Clock specific Makefile
|
||||
#
|
||||
|
||||
obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
|
||||
obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o
|
||||
|
||||
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
|
||||
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
|
||||
|
||||
121
drivers/clk/hisilicon/clk-hisi-phase.c
Normal file
121
drivers/clk/hisilicon/clk-hisi-phase.c
Normal file
@ -0,0 +1,121 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2017 HiSilicon Technologies Co., Ltd.
|
||||
*
|
||||
* Simple HiSilicon phase clock implementation.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
struct clk_hisi_phase {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u32 *phase_degrees;
|
||||
u32 *phase_regvals;
|
||||
u8 phase_num;
|
||||
u32 mask;
|
||||
u8 shift;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_hisi_phase(_hw) container_of(_hw, struct clk_hisi_phase, hw)
|
||||
|
||||
static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase,
|
||||
u32 regval)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < phase->phase_num; i++)
|
||||
if (phase->phase_regvals[i] == regval)
|
||||
return phase->phase_degrees[i];
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int hisi_clk_get_phase(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);
|
||||
u32 regval;
|
||||
|
||||
regval = readl(phase->reg);
|
||||
regval = (regval & phase->mask) >> phase->shift;
|
||||
|
||||
return hisi_phase_regval_to_degrees(phase, regval);
|
||||
}
|
||||
|
||||
static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase,
|
||||
int degrees)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < phase->phase_num; i++)
|
||||
if (phase->phase_degrees[i] == degrees)
|
||||
return phase->phase_regvals[i];
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int hisi_clk_set_phase(struct clk_hw *hw, int degrees)
|
||||
{
|
||||
struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);
|
||||
unsigned long flags = 0;
|
||||
int regval;
|
||||
u32 val;
|
||||
|
||||
regval = hisi_phase_degrees_to_regval(phase, degrees);
|
||||
if (regval < 0)
|
||||
return regval;
|
||||
|
||||
spin_lock_irqsave(phase->lock, flags);
|
||||
|
||||
val = clk_readl(phase->reg);
|
||||
val &= ~phase->mask;
|
||||
val |= regval << phase->shift;
|
||||
clk_writel(val, phase->reg);
|
||||
|
||||
spin_unlock_irqrestore(phase->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops clk_phase_ops = {
|
||||
.get_phase = hisi_clk_get_phase,
|
||||
.set_phase = hisi_clk_set_phase,
|
||||
};
|
||||
|
||||
struct clk *clk_register_hisi_phase(struct device *dev,
|
||||
const struct hisi_phase_clock *clks,
|
||||
void __iomem *base, spinlock_t *lock)
|
||||
{
|
||||
struct clk_hisi_phase *phase;
|
||||
struct clk_init_data init;
|
||||
|
||||
phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL);
|
||||
if (!phase)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = clks->name;
|
||||
init.ops = &clk_phase_ops;
|
||||
init.flags = clks->flags | CLK_IS_BASIC;
|
||||
init.parent_names = clks->parent_names ? &clks->parent_names : NULL;
|
||||
init.num_parents = clks->parent_names ? 1 : 0;
|
||||
|
||||
phase->reg = base + clks->offset;
|
||||
phase->shift = clks->shift;
|
||||
phase->mask = (BIT(clks->width) - 1) << clks->shift;
|
||||
phase->lock = lock;
|
||||
phase->phase_degrees = clks->phase_degrees;
|
||||
phase->phase_regvals = clks->phase_regvals;
|
||||
phase->phase_num = clks->phase_num;
|
||||
phase->hw.init = &init;
|
||||
|
||||
return devm_clk_register(dev, &phase->hw);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_register_hisi_phase);
|
||||
@ -197,6 +197,30 @@ err:
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hisi_clk_register_mux);
|
||||
|
||||
int hisi_clk_register_phase(struct device *dev,
|
||||
const struct hisi_phase_clock *clks,
|
||||
int nums, struct hisi_clock_data *data)
|
||||
{
|
||||
void __iomem *base = data->base;
|
||||
struct clk *clk;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = clk_register_hisi_phase(dev, &clks[i], base,
|
||||
&hisi_clk_lock);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n", __func__,
|
||||
clks[i].name);
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
data->clk_data.clks[clks[i].id] = clk;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hisi_clk_register_phase);
|
||||
|
||||
int hisi_clk_register_divider(const struct hisi_divider_clock *clks,
|
||||
int nums, struct hisi_clock_data *data)
|
||||
{
|
||||
|
||||
@ -68,6 +68,19 @@ struct hisi_mux_clock {
|
||||
const char *alias;
|
||||
};
|
||||
|
||||
struct hisi_phase_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_names;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u32 *phase_degrees;
|
||||
u32 *phase_regvals;
|
||||
u8 phase_num;
|
||||
};
|
||||
|
||||
struct hisi_divider_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
@ -120,6 +133,12 @@ int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
|
||||
int, struct hisi_clock_data *);
|
||||
int hisi_clk_register_mux(const struct hisi_mux_clock *, int,
|
||||
struct hisi_clock_data *);
|
||||
struct clk *clk_register_hisi_phase(struct device *dev,
|
||||
const struct hisi_phase_clock *clks,
|
||||
void __iomem *base, spinlock_t *lock);
|
||||
int hisi_clk_register_phase(struct device *dev,
|
||||
const struct hisi_phase_clock *clks,
|
||||
int nums, struct hisi_clock_data *data);
|
||||
int hisi_clk_register_divider(const struct hisi_divider_clock *,
|
||||
int, struct hisi_clock_data *);
|
||||
int hisi_clk_register_gate(const struct hisi_gate_clock *,
|
||||
|
||||
@ -27,30 +27,31 @@
|
||||
#include "reset.h"
|
||||
|
||||
/* hi3798CV200 core CRG */
|
||||
#define HI3798CV200_INNER_CLK_OFFSET 64
|
||||
#define HI3798CV200_FIXED_24M 65
|
||||
#define HI3798CV200_FIXED_25M 66
|
||||
#define HI3798CV200_FIXED_50M 67
|
||||
#define HI3798CV200_FIXED_75M 68
|
||||
#define HI3798CV200_FIXED_100M 69
|
||||
#define HI3798CV200_FIXED_150M 70
|
||||
#define HI3798CV200_FIXED_200M 71
|
||||
#define HI3798CV200_FIXED_250M 72
|
||||
#define HI3798CV200_FIXED_300M 73
|
||||
#define HI3798CV200_FIXED_400M 74
|
||||
#define HI3798CV200_MMC_MUX 75
|
||||
#define HI3798CV200_ETH_PUB_CLK 76
|
||||
#define HI3798CV200_ETH_BUS_CLK 77
|
||||
#define HI3798CV200_ETH_BUS0_CLK 78
|
||||
#define HI3798CV200_ETH_BUS1_CLK 79
|
||||
#define HI3798CV200_COMBPHY1_MUX 80
|
||||
#define HI3798CV200_FIXED_12M 81
|
||||
#define HI3798CV200_FIXED_48M 82
|
||||
#define HI3798CV200_FIXED_60M 83
|
||||
#define HI3798CV200_FIXED_166P5M 84
|
||||
#define HI3798CV200_SDIO0_MUX 85
|
||||
#define HI3798CV200_INNER_CLK_OFFSET 64
|
||||
#define HI3798CV200_FIXED_24M 65
|
||||
#define HI3798CV200_FIXED_25M 66
|
||||
#define HI3798CV200_FIXED_50M 67
|
||||
#define HI3798CV200_FIXED_75M 68
|
||||
#define HI3798CV200_FIXED_100M 69
|
||||
#define HI3798CV200_FIXED_150M 70
|
||||
#define HI3798CV200_FIXED_200M 71
|
||||
#define HI3798CV200_FIXED_250M 72
|
||||
#define HI3798CV200_FIXED_300M 73
|
||||
#define HI3798CV200_FIXED_400M 74
|
||||
#define HI3798CV200_MMC_MUX 75
|
||||
#define HI3798CV200_ETH_PUB_CLK 76
|
||||
#define HI3798CV200_ETH_BUS_CLK 77
|
||||
#define HI3798CV200_ETH_BUS0_CLK 78
|
||||
#define HI3798CV200_ETH_BUS1_CLK 79
|
||||
#define HI3798CV200_COMBPHY1_MUX 80
|
||||
#define HI3798CV200_FIXED_12M 81
|
||||
#define HI3798CV200_FIXED_48M 82
|
||||
#define HI3798CV200_FIXED_60M 83
|
||||
#define HI3798CV200_FIXED_166P5M 84
|
||||
#define HI3798CV200_SDIO0_MUX 85
|
||||
#define HI3798CV200_COMBPHY0_MUX 86
|
||||
|
||||
#define HI3798CV200_CRG_NR_CLKS 128
|
||||
#define HI3798CV200_CRG_NR_CLKS 128
|
||||
|
||||
static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
|
||||
{ HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
|
||||
@ -74,9 +75,9 @@ static const char *const mmc_mux_p[] = {
|
||||
"100m", "50m", "25m", "200m", "150m" };
|
||||
static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
|
||||
|
||||
static const char *const comphy1_mux_p[] = {
|
||||
static const char *const comphy_mux_p[] = {
|
||||
"100m", "25m"};
|
||||
static u32 comphy1_mux_table[] = {2, 3};
|
||||
static u32 comphy_mux_table[] = {2, 3};
|
||||
|
||||
static const char *const sdio_mux_p[] = {
|
||||
"100m", "50m", "150m", "166p5m" };
|
||||
@ -85,14 +86,29 @@ static u32 sdio_mux_table[] = {0, 1, 2, 3};
|
||||
static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
|
||||
{ HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
|
||||
CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
|
||||
{ HI3798CV200_COMBPHY0_MUX, "combphy0_mux",
|
||||
comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
|
||||
CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
|
||||
{ HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
|
||||
comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),
|
||||
CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },
|
||||
comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
|
||||
CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
|
||||
{ HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
|
||||
ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
|
||||
0x9c, 8, 2, 0, sdio_mux_table, },
|
||||
};
|
||||
|
||||
static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
|
||||
static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315};
|
||||
|
||||
static struct hisi_phase_clock hi3798cv200_phase_clks[] = {
|
||||
{ HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu",
|
||||
CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
|
||||
mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
|
||||
{ HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu",
|
||||
CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
|
||||
mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
|
||||
};
|
||||
|
||||
static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
|
||||
/* UART */
|
||||
{ HISTB_UART2_CLK, "clk_uart2", "75m",
|
||||
@ -147,6 +163,9 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
|
||||
CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
|
||||
{ HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",
|
||||
CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
|
||||
/* COMBPHY0 */
|
||||
{ HISTB_COMBPHY0_CLK, "clk_combphy0", "combphy0_mux",
|
||||
CLK_SET_RATE_PARENT, 0x188, 0, 0, },
|
||||
/* COMBPHY1 */
|
||||
{ HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
|
||||
CLK_SET_RATE_PARENT, 0x188, 8, 0, },
|
||||
@ -161,6 +180,8 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
|
||||
CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
|
||||
{ HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
|
||||
CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
|
||||
{ HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m",
|
||||
CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
|
||||
{ HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
|
||||
CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
|
||||
{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
|
||||
@ -177,6 +198,14 @@ static struct hisi_clock_data *hi3798cv200_clk_register(
|
||||
if (!clk_data)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
/* hisi_phase_clock is resource managed */
|
||||
ret = hisi_clk_register_phase(&pdev->dev,
|
||||
hi3798cv200_phase_clks,
|
||||
ARRAY_SIZE(hi3798cv200_phase_clks),
|
||||
clk_data);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
|
||||
ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
|
||||
clk_data);
|
||||
@ -202,18 +231,17 @@ static struct hisi_clock_data *hi3798cv200_clk_register(
|
||||
|
||||
return clk_data;
|
||||
|
||||
unregister_fixed_rate:
|
||||
hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
|
||||
ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
|
||||
unregister_gate:
|
||||
hisi_clk_unregister_gate(hi3798cv200_gate_clks,
|
||||
ARRAY_SIZE(hi3798cv200_gate_clks),
|
||||
clk_data);
|
||||
|
||||
unregister_mux:
|
||||
hisi_clk_unregister_mux(hi3798cv200_mux_clks,
|
||||
ARRAY_SIZE(hi3798cv200_mux_clks),
|
||||
clk_data);
|
||||
unregister_gate:
|
||||
hisi_clk_unregister_gate(hi3798cv200_gate_clks,
|
||||
ARRAY_SIZE(hi3798cv200_gate_clks),
|
||||
unregister_fixed_rate:
|
||||
hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
|
||||
ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
|
||||
clk_data);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
@ -245,7 +273,7 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
|
||||
#define HI3798CV200_SYSCTRL_NR_CLKS 16
|
||||
|
||||
static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
|
||||
{ HISTB_IR_CLK, "clk_ir", "100m",
|
||||
{ HISTB_IR_CLK, "clk_ir", "24m",
|
||||
CLK_SET_RATE_PARENT, 0x48, 4, 0, },
|
||||
{ HISTB_TIMER01_CLK, "clk_timer01", "24m",
|
||||
CLK_SET_RATE_PARENT, 0x48, 6, 0, },
|
||||
|
||||
@ -22,18 +22,18 @@
|
||||
#define HISTB_OSC_CLK 0
|
||||
#define HISTB_APB_CLK 1
|
||||
#define HISTB_AHB_CLK 2
|
||||
#define HISTB_UART1_CLK 3
|
||||
#define HISTB_UART2_CLK 4
|
||||
#define HISTB_UART3_CLK 5
|
||||
#define HISTB_I2C0_CLK 6
|
||||
#define HISTB_I2C1_CLK 7
|
||||
#define HISTB_I2C2_CLK 8
|
||||
#define HISTB_I2C3_CLK 9
|
||||
#define HISTB_I2C4_CLK 10
|
||||
#define HISTB_I2C5_CLK 11
|
||||
#define HISTB_SPI0_CLK 12
|
||||
#define HISTB_SPI1_CLK 13
|
||||
#define HISTB_SPI2_CLK 14
|
||||
#define HISTB_UART1_CLK 3
|
||||
#define HISTB_UART2_CLK 4
|
||||
#define HISTB_UART3_CLK 5
|
||||
#define HISTB_I2C0_CLK 6
|
||||
#define HISTB_I2C1_CLK 7
|
||||
#define HISTB_I2C2_CLK 8
|
||||
#define HISTB_I2C3_CLK 9
|
||||
#define HISTB_I2C4_CLK 10
|
||||
#define HISTB_I2C5_CLK 11
|
||||
#define HISTB_SPI0_CLK 12
|
||||
#define HISTB_SPI1_CLK 13
|
||||
#define HISTB_SPI2_CLK 14
|
||||
#define HISTB_SCI_CLK 15
|
||||
#define HISTB_FMC_CLK 16
|
||||
#define HISTB_MMC_BIU_CLK 17
|
||||
@ -43,7 +43,7 @@
|
||||
#define HISTB_SDIO0_BIU_CLK 21
|
||||
#define HISTB_SDIO0_CIU_CLK 22
|
||||
#define HISTB_SDIO0_DRV_CLK 23
|
||||
#define HISTB_SDIO0_SAMPLE_CLK 24
|
||||
#define HISTB_SDIO0_SAMPLE_CLK 24
|
||||
#define HISTB_PCIE_AUX_CLK 25
|
||||
#define HISTB_PCIE_PIPE_CLK 26
|
||||
#define HISTB_PCIE_SYS_CLK 27
|
||||
@ -53,21 +53,22 @@
|
||||
#define HISTB_ETH1_MAC_CLK 31
|
||||
#define HISTB_ETH1_MACIF_CLK 32
|
||||
#define HISTB_COMBPHY1_CLK 33
|
||||
#define HISTB_USB2_BUS_CLK 34
|
||||
#define HISTB_USB2_PHY_CLK 35
|
||||
#define HISTB_USB2_UTMI_CLK 36
|
||||
#define HISTB_USB2_12M_CLK 37
|
||||
#define HISTB_USB2_48M_CLK 38
|
||||
#define HISTB_USB2_OTG_UTMI_CLK 39
|
||||
#define HISTB_USB2_PHY1_REF_CLK 40
|
||||
#define HISTB_USB2_PHY2_REF_CLK 41
|
||||
#define HISTB_USB2_BUS_CLK 34
|
||||
#define HISTB_USB2_PHY_CLK 35
|
||||
#define HISTB_USB2_UTMI_CLK 36
|
||||
#define HISTB_USB2_12M_CLK 37
|
||||
#define HISTB_USB2_48M_CLK 38
|
||||
#define HISTB_USB2_OTG_UTMI_CLK 39
|
||||
#define HISTB_USB2_PHY1_REF_CLK 40
|
||||
#define HISTB_USB2_PHY2_REF_CLK 41
|
||||
#define HISTB_COMBPHY0_CLK 42
|
||||
|
||||
/* clocks provided by mcu CRG */
|
||||
#define HISTB_MCE_CLK 1
|
||||
#define HISTB_IR_CLK 2
|
||||
#define HISTB_TIMER01_CLK 3
|
||||
#define HISTB_LEDC_CLK 4
|
||||
#define HISTB_UART0_CLK 5
|
||||
#define HISTB_LSADC_CLK 6
|
||||
#define HISTB_MCE_CLK 1
|
||||
#define HISTB_IR_CLK 2
|
||||
#define HISTB_TIMER01_CLK 3
|
||||
#define HISTB_LEDC_CLK 4
|
||||
#define HISTB_UART0_CLK 5
|
||||
#define HISTB_LSADC_CLK 6
|
||||
|
||||
#endif /* __DTS_HISTB_CLOCK_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user