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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mce/AMD: Fix UP build error x86: Specify a size for the cmp in the NMI handler x86/nmi: Test saved %cs in NMI to determine nested NMI case x86/amd: Fix L1i and L2 cache sharing information for AMD family 15h processors x86/microcode: Remove noisy AMD microcode warning
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commit
e25bda5642
@ -326,8 +326,7 @@ static void __cpuinit amd_calc_l3_indices(struct amd_northbridge *nb)
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l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
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}
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static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf,
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int index)
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static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int index)
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{
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int node;
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@ -725,14 +724,16 @@ static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
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#define CPUID4_INFO_IDX(x, y) (&((per_cpu(ici_cpuid4_info, x))[y]))
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#ifdef CONFIG_SMP
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static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
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static int __cpuinit cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
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{
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struct _cpuid4_info *this_leaf, *sibling_leaf;
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unsigned long num_threads_sharing;
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int index_msb, i, sibling;
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struct _cpuid4_info *this_leaf;
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int ret, i, sibling;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
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ret = 0;
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if (index == 3) {
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ret = 1;
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for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
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if (!per_cpu(ici_cpuid4_info, i))
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continue;
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@ -743,8 +744,35 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
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set_bit(sibling, this_leaf->shared_cpu_map);
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}
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}
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return;
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} else if ((c->x86 == 0x15) && ((index == 1) || (index == 2))) {
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ret = 1;
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for_each_cpu(i, cpu_sibling_mask(cpu)) {
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if (!per_cpu(ici_cpuid4_info, i))
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continue;
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this_leaf = CPUID4_INFO_IDX(i, index);
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for_each_cpu(sibling, cpu_sibling_mask(cpu)) {
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if (!cpu_online(sibling))
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continue;
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set_bit(sibling, this_leaf->shared_cpu_map);
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}
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}
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}
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return ret;
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}
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static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
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{
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struct _cpuid4_info *this_leaf, *sibling_leaf;
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unsigned long num_threads_sharing;
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int index_msb, i;
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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if (c->x86_vendor == X86_VENDOR_AMD) {
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if (cache_shared_amd_cpu_map_setup(cpu, index))
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return;
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}
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this_leaf = CPUID4_INFO_IDX(cpu, index);
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num_threads_sharing = 1 + this_leaf->base.eax.split.num_threads_sharing;
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@ -528,6 +528,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
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sprintf(name, "threshold_bank%i", bank);
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#ifdef CONFIG_SMP
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if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
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i = cpumask_first(cpu_llc_shared_mask(cpu));
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@ -553,6 +554,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
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goto out;
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}
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#endif
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b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
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if (!b) {
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@ -1531,11 +1531,18 @@ ENTRY(nmi)
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/* Use %rdx as out temp variable throughout */
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pushq_cfi %rdx
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/*
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* If %cs was not the kernel segment, then the NMI triggered in user
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* space, which means it is definitely not nested.
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*/
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cmpl $__KERNEL_CS, 16(%rsp)
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jne first_nmi
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/*
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* Check the special variable on the stack to see if NMIs are
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* executing.
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*/
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cmp $1, -8(%rsp)
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cmpl $1, -8(%rsp)
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je nested_nmi
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/*
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@ -360,7 +360,6 @@ out:
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static enum ucode_state
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request_microcode_user(int cpu, const void __user *buf, size_t size)
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{
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pr_info("AMD microcode update via /dev/cpu/microcode not supported\n");
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return UCODE_ERROR;
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}
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