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sata_mv cosmetic fixes
Various cosmetic fixes in preparation for real code changes later on. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Mark Lord
Jeff Garzik
parent
83c063dd73
commit
e12bef50b7
@ -1,6 +1,7 @@
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/*
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* sata_mv.c - Marvell SATA support
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*
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* Copyright 2008: Marvell Corporation, all rights reserved.
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* Copyright 2005: EMC Corporation, all rights reserved.
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* Copyright 2005 Red Hat, Inc. All rights reserved.
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*
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@ -61,7 +62,6 @@
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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@ -131,7 +131,7 @@ enum {
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MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
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MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
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/* SoC integrated controllers, no PCI interface */
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MV_FLAG_SOC = (1 << 28),
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MV_FLAG_SOC = (1 << 28),
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MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
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@ -141,6 +141,7 @@ enum {
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CRQB_FLAG_READ = (1 << 0),
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CRQB_TAG_SHIFT = 1,
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CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
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CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
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CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
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CRQB_CMD_ADDR_SHIFT = 8,
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CRQB_CMD_CS = (0x2 << 11),
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@ -199,7 +200,7 @@ enum {
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TWSI_INT = (1 << 24),
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HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
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HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
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HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
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HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
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HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
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PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
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HC_MAIN_RSVD),
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@ -223,13 +224,18 @@ enum {
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SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
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SATA_ACTIVE_OFS = 0x350,
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SATA_FIS_IRQ_CAUSE_OFS = 0x364,
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LTMODE_OFS = 0x30c,
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PHY_MODE3 = 0x310,
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PHY_MODE4 = 0x314,
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PHY_MODE2 = 0x330,
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SATA_IFCTL_OFS = 0x344,
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SATA_IFSTAT_OFS = 0x34c,
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VENDOR_UNIQUE_FIS_OFS = 0x35c,
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FIS_CFG_OFS = 0x360,
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MV5_PHY_MODE = 0x74,
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MV5_LT_MODE = 0x30,
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MV5_PHY_CTL = 0x0C,
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SATA_INTERFACE_CTL = 0x050,
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SATA_INTERFACE_CFG = 0x050,
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MV_M2_PREAMP_MASK = 0x7e0,
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@ -240,6 +246,8 @@ enum {
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EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
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EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
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EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
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EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
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EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
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EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
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EDMA_ERR_IRQ_MASK_OFS = 0xc,
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@ -298,6 +306,7 @@ enum {
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EDMA_ERR_LNK_DATA_RX |
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EDMA_ERR_LNK_DATA_TX |
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EDMA_ERR_TRANS_PROTO,
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EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
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EDMA_ERR_PRD_PAR |
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EDMA_ERR_DEV_DCON |
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@ -344,7 +353,6 @@ enum {
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/* Port private flags (pp_flags) */
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MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
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MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
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MV_PP_FLAG_HAD_A_RESET = (1 << 2), /* 1st hard reset complete? */
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};
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#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
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@ -506,11 +514,11 @@ static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
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void __iomem *mmio);
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static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
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static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
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static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
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static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
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unsigned int port_no);
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static void mv_edma_cfg(struct mv_port_priv *pp, struct mv_host_priv *hpriv,
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void __iomem *port_mmio, int want_ncq);
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static int __mv_stop_dma(struct ata_port *ap);
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static int mv_stop_edma(struct ata_port *ap);
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static int mv_stop_edma_engine(struct ata_port *ap);
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static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
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/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
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* because we have to allow room for worst case splitting of
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@ -714,6 +722,14 @@ static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
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(mv_hardport_from_port(port) * MV_PORT_REG_SZ);
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}
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static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
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{
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void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
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unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
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return hc_mmio + ofs;
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}
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static inline void __iomem *mv_host_base(struct ata_host *host)
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{
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struct mv_host_priv *hpriv = host->private_data;
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@ -789,7 +805,7 @@ static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
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if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
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int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
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if (want_ncq != using_ncq)
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__mv_stop_dma(ap);
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mv_stop_edma_engine(ap);
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}
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if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
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struct mv_host_priv *hpriv = ap->host->private_data;
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@ -810,7 +826,7 @@ static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
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hc_mmio + HC_IRQ_CAUSE_OFS);
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}
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mv_edma_cfg(pp, hpriv, port_mmio, want_ncq);
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mv_edma_cfg(ap, want_ncq);
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/* clear FIS IRQ Cause */
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writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
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@ -824,7 +840,7 @@ static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
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}
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/**
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* __mv_stop_dma - Disable eDMA engine
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* mv_stop_edma_engine - Disable eDMA engine
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* @ap: ATA channel to manipulate
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*
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* Verify the local cache of the eDMA state is accurate with a
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@ -833,7 +849,7 @@ static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
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* LOCKING:
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* Inherited from caller.
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*/
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static int __mv_stop_dma(struct ata_port *ap)
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static int mv_stop_edma_engine(struct ata_port *ap)
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{
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void __iomem *port_mmio = mv_ap_base(ap);
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struct mv_port_priv *pp = ap->private_data;
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@ -866,13 +882,13 @@ static int __mv_stop_dma(struct ata_port *ap)
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return err;
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}
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static int mv_stop_dma(struct ata_port *ap)
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static int mv_stop_edma(struct ata_port *ap)
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{
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unsigned long flags;
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int rc;
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spin_lock_irqsave(&ap->host->lock, flags);
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rc = __mv_stop_dma(ap);
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rc = mv_stop_edma_engine(ap);
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spin_unlock_irqrestore(&ap->host->lock, flags);
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return rc;
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@ -1007,10 +1023,12 @@ static void mv6_dev_config(struct ata_device *adev)
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adev->max_sectors = ATA_MAX_SECTORS;
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}
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static void mv_edma_cfg(struct mv_port_priv *pp, struct mv_host_priv *hpriv,
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void __iomem *port_mmio, int want_ncq)
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static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
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{
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u32 cfg;
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struct mv_port_priv *pp = ap->private_data;
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struct mv_host_priv *hpriv = ap->host->private_data;
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void __iomem *port_mmio = mv_ap_base(ap);
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/* set up non-NCQ EDMA configuration */
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cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
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@ -1118,7 +1136,7 @@ static int mv_port_start(struct ata_port *ap)
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spin_lock_irqsave(&ap->host->lock, flags);
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mv_edma_cfg(pp, hpriv, port_mmio, 0);
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mv_edma_cfg(ap, 0);
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mv_set_edma_ptrs(port_mmio, hpriv, pp);
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spin_unlock_irqrestore(&ap->host->lock, flags);
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@ -1145,7 +1163,7 @@ out_port_free_dma_mem:
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*/
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static void mv_port_stop(struct ata_port *ap)
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{
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mv_stop_dma(ap);
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mv_stop_edma(ap);
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mv_port_free_dma_mem(ap);
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}
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@ -1315,8 +1333,7 @@ static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
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(qc->tf.protocol != ATA_PROT_NCQ))
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return;
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/* Fill in Gen IIE command request block
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*/
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/* Fill in Gen IIE command request block */
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if (!(qc->tf.flags & ATA_TFLAG_WRITE))
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flags |= CRQB_FLAG_READ;
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@ -1384,7 +1401,7 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
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* port. Turn off EDMA so there won't be problems accessing
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* shadow block, etc registers.
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*/
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__mv_stop_dma(ap);
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mv_stop_edma_engine(ap);
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return ata_qc_issue_prot(qc);
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}
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@ -1407,10 +1424,10 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
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* @reset_allowed: bool: 0 == don't trigger from reset here
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*
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* In most cases, just clear the interrupt and move on. However,
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* some cases require an eDMA reset, which is done right before
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* the COMRESET in mv_phy_reset(). The SERR case requires a
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* clear of pending errors in the SATA SERROR register. Finally,
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* if the port disabled DMA, update our cached copy to match.
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* some cases require an eDMA reset, which also performs a COMRESET.
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* The SERR case requires a clear of pending errors in the SATA
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* SERROR register. Finally, if the port disabled DMA,
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* update our cached copy to match.
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*
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* LOCKING:
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* Inherited from caller.
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@ -1648,9 +1665,9 @@ static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
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pp = ap->private_data;
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shift = port << 1; /* (port * 2) */
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if (port >= MV_PORTS_PER_HC) {
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if (port >= MV_PORTS_PER_HC)
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shift++; /* skip bit 8 in the HC Main IRQ reg */
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}
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have_err_bits = ((PORT0_ERR << shift) & relevant);
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if (unlikely(have_err_bits)) {
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@ -1739,6 +1756,7 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
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void __iomem *mmio = hpriv->base;
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u32 irq_stat, irq_mask;
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/* Note to self: &host->lock == &ap->host->lock == ap->lock */
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spin_lock(&host->lock);
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irq_stat = readl(hpriv->main_cause_reg_addr);
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@ -1772,14 +1790,6 @@ out_unlock:
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return IRQ_RETVAL(handled);
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}
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static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
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{
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void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
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unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
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return hc_mmio + ofs;
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}
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static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
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{
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unsigned int ofs;
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@ -1907,7 +1917,7 @@ static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
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writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
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mv_channel_reset(hpriv, mmio, port);
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mv_reset_channel(hpriv, mmio, port);
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ZERO(0x028); /* command */
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writel(0x11f, port_mmio + EDMA_CFG_OFS);
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@ -2125,14 +2135,15 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
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m4 = readl(port_mmio + PHY_MODE4);
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if (hp_flags & MV_HP_ERRATA_60X1B2)
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tmp = readl(port_mmio + 0x310);
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tmp = readl(port_mmio + PHY_MODE3);
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/* workaround for errata FEr SATA#10 (part 1) */
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m4 = (m4 & ~(1 << 1)) | (1 << 0);
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writel(m4, port_mmio + PHY_MODE4);
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if (hp_flags & MV_HP_ERRATA_60X1B2)
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writel(tmp, port_mmio + 0x310);
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writel(tmp, port_mmio + PHY_MODE3);
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}
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/* Revert values of pre-emphasis and signal amps to the saved ones */
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@ -2182,7 +2193,7 @@ static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
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writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
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mv_channel_reset(hpriv, mmio, port);
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mv_reset_channel(hpriv, mmio, port);
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ZERO(0x028); /* command */
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writel(0x101f, port_mmio + EDMA_CFG_OFS);
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@ -2239,7 +2250,7 @@ static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
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return;
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}
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static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
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static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
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unsigned int port_no)
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{
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void __iomem *port_mmio = mv_port_base(mmio, port_no);
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@ -2247,10 +2258,10 @@ static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
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writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
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if (IS_GEN_II(hpriv)) {
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u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
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u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG);
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ifctl |= (1 << 7); /* enable gen2i speed */
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ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
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writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
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writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG);
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}
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udelay(25); /* allow reset propagation */
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@ -2372,14 +2383,7 @@ comreset_retry:
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static int mv_prereset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct mv_port_priv *pp = ap->private_data;
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mv_stop_dma(ap);
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if (!(pp->pp_flags & MV_PP_FLAG_HAD_A_RESET))
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pp->pp_flags |= MV_PP_FLAG_HAD_A_RESET;
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mv_stop_edma(link->ap);
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return 0;
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}
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@ -2390,10 +2394,8 @@ static int mv_hardreset(struct ata_link *link, unsigned int *class,
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struct mv_host_priv *hpriv = ap->host->private_data;
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void __iomem *mmio = hpriv->base;
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mv_stop_dma(ap);
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mv_channel_reset(hpriv, mmio, ap->port_no);
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mv_stop_edma(ap);
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mv_reset_channel(hpriv, mmio, ap->port_no);
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mv_phy_reset(ap, class, deadline);
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return 0;
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@ -2715,10 +2717,10 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
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if (IS_GEN_II(hpriv)) {
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void __iomem *port_mmio = mv_port_base(mmio, port);
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u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
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u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG);
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ifctl |= (1 << 7); /* enable gen2i speed */
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ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
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writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
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writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG);
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}
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hpriv->ops->phy_errata(hpriv, mmio, port);
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