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net/mlx5: Add support check for TSAR types in QoS scheduling

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Introduce a new function, mlx5_qos_tsar_type_supported(), to handle the
validation of TSAR types within QoS scheduling contexts.

Refactor the existing code to use this new function, replacing direct
checks for TSAR type support in the NIC scheduling hierarchy.

Signed-off-by: Carolina Jubran <cjubran@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Carolina Jubran 2024-10-08 21:32:22 +03:00 committed by Paolo Abeni
parent f91c69f43c
commit e1013c7929
4 changed files with 34 additions and 2 deletions
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4
drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c
View File

@ -602,7 +602,9 @@ static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *exta
if (!mlx5_qos_element_type_supported(dev,
SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR,
SCHEDULING_HIERARCHY_E_SWITCH) ||
!(MLX5_CAP_QOS(dev, esw_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
!mlx5_qos_tsar_type_supported(dev,
TSAR_ELEMENT_TSAR_TYPE_DWRR,
SCHEDULING_HIERARCHY_E_SWITCH))
return -EOPNOTSUPP;
MLX5_SET(scheduling_context, tsar_ctx, element_type,

1
drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h
View File

@ -225,6 +225,7 @@ int mlx5_core_sriov_set_msix_vec_count(struct pci_dev *vf, int msix_vec_count);
int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy);
bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy);
int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
void *context, u32 *element_id);
int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,

4
drivers/net/ethernet/mellanox/mlx5/core/qos.c
View File

@ -52,7 +52,9 @@ int mlx5_qos_create_inner_node(struct mlx5_core_dev *mdev, u32 parent_id,
if (!mlx5_qos_element_type_supported(mdev,
SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR,
SCHEDULING_HIERARCHY_NIC) ||
!(MLX5_CAP_QOS(mdev, nic_tsar_type) & TSAR_TYPE_CAP_MASK_DWRR))
!mlx5_qos_tsar_type_supported(mdev,
TSAR_ELEMENT_TSAR_TYPE_DWRR,
SCHEDULING_HIERARCHY_NIC))
return -EOPNOTSUPP;
MLX5_SET(scheduling_context, sched_ctx, parent_element_id, parent_id);

27
drivers/net/ethernet/mellanox/mlx5/core/rl.c
View File

@ -34,6 +34,33 @@
#include <linux/mlx5/driver.h>
#include "mlx5_core.h"
bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy)
{
int cap;
switch (hierarchy) {
case SCHEDULING_HIERARCHY_E_SWITCH:
cap = MLX5_CAP_QOS(dev, esw_tsar_type);
break;
case SCHEDULING_HIERARCHY_NIC:
cap = MLX5_CAP_QOS(dev, nic_tsar_type);
break;
default:
return false;
}
switch (type) {
case TSAR_ELEMENT_TSAR_TYPE_DWRR:
return cap & TSAR_TYPE_CAP_MASK_DWRR;
case TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN:
return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN;
case TSAR_ELEMENT_TSAR_TYPE_ETS:
return cap & TSAR_TYPE_CAP_MASK_ETS;
}
return false;
}
bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy)
{
int cap;