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dt-bindings: net: dsa: convert binding for mediatek switches
Convert txt binding to yaml binding for Mediatek switches. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Frank Wunderlich
Jakub Kicinski
parent
68d5428931
commit
e0dda31197
406
Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
Normal file
406
Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
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@ -0,0 +1,406 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek MT7530 Ethernet switch
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maintainers:
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- Sean Wang <sean.wang@mediatek.com>
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- Landen Chao <Landen.Chao@mediatek.com>
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- DENG Qingfang <dqfext@gmail.com>
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description: |
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Port 5 of mt7530 and mt7621 switch is muxed between:
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1. GMAC5: GMAC5 can interface with another external MAC or PHY.
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2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
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of the SOC. Used in many setups where port 0/4 becomes the WAN port.
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Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
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GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
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connected to external component!
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Port 5 modes/configurations:
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1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
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GMAC of the SOC.
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In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
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GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
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2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
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It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
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and RGMII delay.
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3. Port 5 is muxed to GMAC5 and can interface to an external phy.
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Port 5 becomes an extra switch port.
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Only works on platform where external phy TX<->RX lines are swapped.
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Like in the Ubiquiti ER-X-SFP.
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4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
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Currently a 2nd CPU port is not supported by DSA code.
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Depending on how the external PHY is wired:
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1. normal: The PHY can only connect to 2nd GMAC but not to the switch
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2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
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a ethernet port. But can't interface to the 2nd GMAC.
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Based on the DT the port 5 mode is configured.
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Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
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When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
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phy-mode must be set, see also example 2 below!
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* mt7621: phy-mode = "rgmii-txid";
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* mt7623: phy-mode = "rgmii";
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CPU-Ports need a phy-mode property:
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Allowed values on mt7530 and mt7621:
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- "rgmii"
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- "trgmii"
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On mt7531:
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- "1000base-x"
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- "2500base-x"
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- "sgmii"
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properties:
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compatible:
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enum:
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- mediatek,mt7530
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- mediatek,mt7531
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- mediatek,mt7621
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core-supply:
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description:
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Phandle to the regulator node necessary for the core power.
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"#gpio-cells":
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const: 2
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gpio-controller:
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type: boolean
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description:
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if defined, MT7530's LED controller will run on GPIO mode.
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"#interrupt-cells":
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const: 1
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interrupt-controller: true
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interrupts:
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maxItems: 1
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io-supply:
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description:
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Phandle to the regulator node necessary for the I/O power.
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See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
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for details for the regulator setup on these boards.
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mediatek,mcm:
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type: boolean
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description:
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if defined, indicates that either MT7530 is the part on multi-chip
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module belong to MT7623A has or the remotely standalone chip as the
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function MT7623N reference board provided for.
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reset-gpios:
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maxItems: 1
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reset-names:
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const: mcm
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resets:
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description:
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Phandle pointing to the system reset controller with line index for
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the ethsys.
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maxItems: 1
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patternProperties:
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"^(ethernet-)?ports$":
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type: object
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patternProperties:
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"^(ethernet-)?port@[0-9]+$":
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type: object
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description: Ethernet switch ports
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unevaluatedProperties: false
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properties:
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reg:
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description:
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Port address described must be 6 for CPU port and from 0 to
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5 for user ports.
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allOf:
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- $ref: dsa-port.yaml#
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- if:
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properties:
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label:
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items:
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- const: cpu
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then:
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required:
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- reg
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- phy-mode
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required:
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- compatible
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- reg
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allOf:
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- $ref: "dsa.yaml#"
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- if:
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required:
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- mediatek,mcm
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then:
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required:
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- resets
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- reset-names
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else:
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required:
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- reset-gpios
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- dependencies:
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interrupt-controller: [ interrupts ]
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- if:
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properties:
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compatible:
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items:
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- const: mediatek,mt7530
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then:
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required:
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- core-supply
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- io-supply
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@0 {
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compatible = "mediatek,mt7530";
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reg = <0>;
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core-supply = <&mt6323_vpa_reg>;
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io-supply = <&mt6323_vemc3v3_reg>;
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reset-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "trgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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- |
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//Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "rgmii-txid";
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phy-handle = <&phy4>;
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Internal phy */
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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mt7530: switch@1f {
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compatible = "mediatek,mt7621";
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reg = <0x1f>;
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mediatek,mcm;
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resets = <&rstctrl 2>;
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reset-names = "mcm";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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/* Commented out. Port 4 is handled by 2nd GMAC.
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port@4 {
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reg = <4>;
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label = "lan4";
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};
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*/
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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- |
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//Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
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ethernet {
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#address-cells = <1>;
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#size-cells = <0>;
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gmac_0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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mdio0: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* External phy */
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ephy5: ethernet-phy@7 {
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reg = <7>;
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};
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switch@1f {
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compatible = "mediatek,mt7621";
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reg = <0x1f>;
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mediatek,mcm;
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resets = <&rstctrl 2>;
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reset-names = "mcm";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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};
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port@5 {
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reg = <5>;
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label = "lan5";
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phy-mode = "rgmii";
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phy-handle = <&ephy5>;
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};
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cpu_port0: port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac_0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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@ -1,327 +0,0 @@
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Mediatek MT7530 Ethernet switch
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================================
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Required properties:
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- compatible: may be compatible = "mediatek,mt7530"
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or compatible = "mediatek,mt7621"
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or compatible = "mediatek,mt7531"
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- #address-cells: Must be 1.
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- #size-cells: Must be 0.
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- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
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on multi-chip module belong to MT7623A has or the remotely standalone
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chip as the function MT7623N reference board provided for.
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If compatible mediatek,mt7530 is set then the following properties are required
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- core-supply: Phandle to the regulator node necessary for the core power.
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- io-supply: Phandle to the regulator node necessary for the I/O power.
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See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
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for details for the regulator setup on these boards.
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If the property mediatek,mcm isn't defined, following property is required
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- reset-gpios: Should be a gpio specifier for a reset line.
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Else, following properties are required
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- resets : Phandle pointing to the system reset controller with
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line index for the ethsys.
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- reset-names : Should be set to "mcm".
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Required properties for the child nodes within ports container:
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- reg: Port address described must be 6 for CPU port and from 0 to 5 for
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user ports.
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- phy-mode: String, the following values are acceptable for port labeled
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"cpu":
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If compatible mediatek,mt7530 or mediatek,mt7621 is set,
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must be either "trgmii" or "rgmii"
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If compatible mediatek,mt7531 is set,
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must be either "sgmii", "1000base-x" or "2500base-x"
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Port 5 of mt7530 and mt7621 switch is muxed between:
|
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1. GMAC5: GMAC5 can interface with another external MAC or PHY.
|
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2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
|
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of the SOC. Used in many setups where port 0/4 becomes the WAN port.
|
||||
Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
|
||||
GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
|
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connected to external component!
|
||||
|
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Port 5 modes/configurations:
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1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
|
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GMAC of the SOC.
|
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In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
|
||||
GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
|
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2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
|
||||
It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
|
||||
and RGMII delay.
|
||||
3. Port 5 is muxed to GMAC5 and can interface to an external phy.
|
||||
Port 5 becomes an extra switch port.
|
||||
Only works on platform where external phy TX<->RX lines are swapped.
|
||||
Like in the Ubiquiti ER-X-SFP.
|
||||
4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
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Currently a 2nd CPU port is not supported by DSA code.
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||||
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||||
Depending on how the external PHY is wired:
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1. normal: The PHY can only connect to 2nd GMAC but not to the switch
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2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
|
||||
a ethernet port. But can't interface to the 2nd GMAC.
|
||||
|
||||
Based on the DT the port 5 mode is configured.
|
||||
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||||
Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
|
||||
When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
|
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phy-mode must be set, see also example 2 below!
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* mt7621: phy-mode = "rgmii-txid";
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* mt7623: phy-mode = "rgmii";
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Optional properties:
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- gpio-controller: Boolean; if defined, MT7530's LED controller will run on
|
||||
GPIO mode.
|
||||
- #gpio-cells: Must be 2 if gpio-controller is defined.
|
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- interrupt-controller: Boolean; Enables the internal interrupt controller.
|
||||
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If interrupt-controller is defined, the following properties are required.
|
||||
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||||
- #interrupt-cells: Must be 1.
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- interrupts: Parent interrupt for the interrupt controller.
|
||||
|
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See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
|
||||
required, optional properties and how the integrated switch subnodes must
|
||||
be specified.
|
||||
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||||
Example:
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||||
|
||||
&mdio0 {
|
||||
switch@0 {
|
||||
compatible = "mediatek,mt7530";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
core-supply = <&mt6323_vpa_reg>;
|
||||
io-supply = <&mt6323_vemc3v3_reg>;
|
||||
reset-gpios = <&pio 33 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "trgmii";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
|
||||
|
||||
ð {
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-mode = "rgmii-txid";
|
||||
phy-handle = <&phy4>;
|
||||
};
|
||||
|
||||
mdio: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Internal phy */
|
||||
phy4: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
mt7530: switch@1f {
|
||||
compatible = "mediatek,mt7621";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1f>;
|
||||
pinctrl-names = "default";
|
||||
mediatek,mcm;
|
||||
|
||||
resets = <&rstctrl 2>;
|
||||
reset-names = "mcm";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
/* Commented out. Port 4 is handled by 2nd GMAC.
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
};
|
||||
*/
|
||||
|
||||
cpu_port0: port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
|
||||
|
||||
ð {
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
mdio: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* External phy */
|
||||
ephy5: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
};
|
||||
|
||||
mt7530: switch@1f {
|
||||
compatible = "mediatek,mt7621";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1f>;
|
||||
pinctrl-names = "default";
|
||||
mediatek,mcm;
|
||||
|
||||
resets = <&rstctrl 2>;
|
||||
reset-names = "mcm";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan5";
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&ephy5>;
|
||||
};
|
||||
|
||||
cpu_port0: port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user