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I3C for 6.4
Subsystem: - OF alias bus numbering - convert to platform remove callback returning void New driver: AST2600 controller, based on Synopsys DesignWare IP Drivers: - dw: add infrastructure to support different platform integrations -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEBqsFVZXh8s/0O5JiY6TcMGxwOjIFAmRO5S0ACgkQY6TcMGxw OjKFhBAAgeWIJdEPIiL0VjgaM2rcDKS4LD0qAfrrgOh9fyBZMnMt/7jg94naQ8wL z6IQWORO2FDbijCWOQNTw5hPQwUJWTB/rYqKtyCy3hzbmBqkz03O3HjnQsmVmna7 iOzXWpYyvmXyiRFuKKBzmBcTyYvZxHc6d8XUzgmUlGEN0J1haIAqZJlCqDjkJ78h QgsqbCZM7CrEpePDStrK5DxOpaB/is1NVL1eBfl2VKWwp0diIPckAk/GBkXxSnLd 7BLsHFyBWTWiGnxJICOYcdpPQGGpb1JGkW7Td+tGW/14h46Cqn3UZAzleQKL5ecP op2dw7erNGlVDjtRYAOvinpIjc6JS/PQtPsX8a3OLLFyRwY49K/NRpmmI+uW/TQk cijWMqXa1Q0cBB90CfRwkzHoQhwK1WhdlyvpHIJ9RZn/VP+4zzGniVeu7V3b5bWw EfbiDf0yhEHyLWqK9iwIcSjUMWQD5f9zEo5yvv8Fs8/nXhXYTy/BRDZ6CmM46GpD 0nsxaEpXxx0+trtnCa2UNO2xc1R5DcJDeTezOxYpxg2X/fSWRyjFINMlmQ1RV5HY KmberJgqpfXc0Azr1J1LRqfqi8UqYPIG0LLG7z8+wpM2QZvsVo04ZeeEQG+Dcxh1 mASL+rSa72NBsVx6ZaU6pMXgOrmdSY6lj/cPKsTl6eF5aPCHog0= =MXBr -----END PGP SIGNATURE----- Merge tag 'i3c/for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux Pull i3c updates from Alexandre Belloni: "Subsystem: - OF alias bus numbering - convert to platform remove callback returning void New driver: - AST2600 controller, based on Synopsys DesignWare IP Driver update: - dw: add infrastructure to support different platform integrations" * tag 'i3c/for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux: i3c: ast2600: set variable ast2600_i3c_ops storage-class-specifier to static i3c: ast2600: fix register setting for 545 ohm pullups i3c: ast2600: enable IBI support i3c: dw: Add a platform facility for IBI PEC workarounds i3c: dw: Add support for in-band interrupts i3c: dw: Turn DAT array entry into a struct i3c: dw: Create a generic fifo read function i3c: Allow OF-alias-based persistent bus numbering i3c: ast2600: Add AST2600 platform-specific driver dt-bindings: i3c: Add AST2600 i3c controller i3c: dw: Add infrastructure for platform-specific implementations i3c: dw: use bus mode rather than device reg for conditional tCAS setting i3c: dw: Return the length from a read priv_xfer i3c: svc: Convert to platform remove callback returning void i3c: mipi-i3c-hci: Convert to platform remove callback returning void i3c: cdns: Convert to platform remove callback returning void i3c: dw: Convert to platform remove callback returning void i3c: Make i3c_master_unregister() return void i3c: dw: drop of_match_ptr for ID table i3c: Correct reference to the I²C device data type
This commit is contained in:
commit
e0906f1feb
@ -0,0 +1,72 @@
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i3c/aspeed,ast2600-i3c.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ASPEED AST2600 i3c controller
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maintainers:
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- Jeremy Kerr <jk@codeconstruct.com.au>
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allOf:
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- $ref: i3c.yaml#
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properties:
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compatible:
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const: aspeed,ast2600-i3c
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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interrupts:
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maxItems: 1
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sda-pullup-ohms:
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enum: [545, 750, 2000]
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default: 2000
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description: |
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Value to configure SDA pullup resistor, in Ohms.
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aspeed,global-regs:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to i3c global register syscon node
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- description: index of this i3c controller in the global register set
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description: |
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A (phandle, controller index) reference to the i3c global register set
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used for this device.
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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- aspeed,global-regs
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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i3c-master@2000 {
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compatible = "aspeed,ast2600-i3c";
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reg = <0x2000 0x1000>;
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#address-cells = <3>;
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#size-cells = <0>;
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clocks = <&syscon 0>;
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resets = <&syscon 0>;
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aspeed,global-regs = <&i3c_global 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i3c1_default>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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};
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...
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@ -9778,6 +9778,12 @@ S: Orphan
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F: Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml
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F: drivers/i3c/master/dw*
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I3C DRIVER FOR ASPEED AST2600
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M: Jeremy Kerr <jk@codeconstruct.com.au>
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S: Maintained
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F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml
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F: drivers/i3c/master/ast2600-i3c-master.c
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I3C SUBSYSTEM
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M: Alexandre Belloni <alexandre.belloni@bootlin.com>
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L: linux-i3c@lists.infradead.org (moderated for non-subscribers)
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|
@ -21,6 +21,7 @@
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static DEFINE_IDR(i3c_bus_idr);
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static DEFINE_MUTEX(i3c_core_lock);
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static int __i3c_first_dynamic_bus_num;
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/**
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* i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
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@ -419,9 +420,9 @@ static void i3c_bus_cleanup(struct i3c_bus *i3cbus)
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mutex_unlock(&i3c_core_lock);
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}
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static int i3c_bus_init(struct i3c_bus *i3cbus)
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static int i3c_bus_init(struct i3c_bus *i3cbus, struct device_node *np)
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{
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int ret;
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int ret, start, end, id = -1;
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init_rwsem(&i3cbus->lock);
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INIT_LIST_HEAD(&i3cbus->devs.i2c);
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@ -429,8 +430,19 @@ static int i3c_bus_init(struct i3c_bus *i3cbus)
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i3c_bus_init_addrslots(i3cbus);
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i3cbus->mode = I3C_BUS_MODE_PURE;
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if (np)
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id = of_alias_get_id(np, "i3c");
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mutex_lock(&i3c_core_lock);
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ret = idr_alloc(&i3c_bus_idr, i3cbus, 0, 0, GFP_KERNEL);
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if (id >= 0) {
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start = id;
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end = start + 1;
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} else {
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start = __i3c_first_dynamic_bus_num;
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end = 0;
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}
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ret = idr_alloc(&i3c_bus_idr, i3cbus, start, end, GFP_KERNEL);
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mutex_unlock(&i3c_core_lock);
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if (ret < 0)
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@ -2606,7 +2618,7 @@ int i3c_master_register(struct i3c_master_controller *master,
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INIT_LIST_HEAD(&master->boardinfo.i2c);
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INIT_LIST_HEAD(&master->boardinfo.i3c);
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ret = i3c_bus_init(i3cbus);
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ret = i3c_bus_init(i3cbus, master->dev.of_node);
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if (ret)
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return ret;
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@ -2695,17 +2707,13 @@ EXPORT_SYMBOL_GPL(i3c_master_register);
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* @master: master used to send frames on the bus
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*
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* Basically undo everything done in i3c_master_register().
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*
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* Return: 0 in case of success, a negative error code otherwise.
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*/
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int i3c_master_unregister(struct i3c_master_controller *master)
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void i3c_master_unregister(struct i3c_master_controller *master)
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{
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i3c_master_i2c_adapter_cleanup(master);
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i3c_master_unregister_i3c_devs(master);
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i3c_master_bus_cleanup(master);
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device_unregister(&master->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(i3c_master_unregister);
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@ -2834,8 +2842,16 @@ void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev)
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static int __init i3c_init(void)
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{
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int res = bus_register_notifier(&i2c_bus_type, &i2cdev_notifier);
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int res;
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res = of_alias_get_highest_id("i3c");
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if (res >= 0) {
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mutex_lock(&i3c_core_lock);
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__i3c_first_dynamic_bus_num = res + 1;
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mutex_unlock(&i3c_core_lock);
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}
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res = bus_register_notifier(&i2c_bus_type, &i2cdev_notifier);
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if (res)
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return res;
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|
@ -22,6 +22,20 @@ config DW_I3C_MASTER
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This driver can also be built as a module. If so, the module
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will be called dw-i3c-master.
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config AST2600_I3C_MASTER
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tristate "ASPEED AST2600 I3C master driver"
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depends on DW_I3C_MASTER
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depends on ARCH_ASPEED || COMPILE_TEST
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select MFD_SYSCON
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help
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Support for ASPEED AST2600 I3C Controller.
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This hardware is an instance of the DW I3C controller; this
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driver adds platform- specific support for AST2600 hardware.
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This driver can also be built as a module. If so, the module
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will be called ast2600-i3c-master.
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config SVC_I3C_MASTER
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tristate "Silvaco I3C Dual-Role Master driver"
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depends on I3C
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@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_CDNS_I3C_MASTER) += i3c-master-cdns.o
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obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o
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obj-$(CONFIG_AST2600_I3C_MASTER) += ast2600-i3c-master.o
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obj-$(CONFIG_SVC_I3C_MASTER) += svc-i3c-master.o
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obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci/
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|
189
drivers/i3c/master/ast2600-i3c-master.c
Normal file
189
drivers/i3c/master/ast2600-i3c-master.c
Normal file
@ -0,0 +1,189 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023 Code Construct
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*
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* Author: Jeremy Kerr <jk@codeconstruct.com.au>
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "dw-i3c-master.h"
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/* AST2600-specific global register set */
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#define AST2600_I3CG_REG0(idx) (((idx) * 4 * 4) + 0x10)
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#define AST2600_I3CG_REG1(idx) (((idx) * 4 * 4) + 0x14)
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#define AST2600_I3CG_REG0_SDA_PULLUP_EN_MASK GENMASK(29, 28)
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#define AST2600_I3CG_REG0_SDA_PULLUP_EN_2K (0x0 << 28)
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#define AST2600_I3CG_REG0_SDA_PULLUP_EN_750 (0x2 << 28)
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#define AST2600_I3CG_REG0_SDA_PULLUP_EN_545 (0x3 << 28)
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#define AST2600_I3CG_REG1_I2C_MODE BIT(0)
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#define AST2600_I3CG_REG1_TEST_MODE BIT(1)
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#define AST2600_I3CG_REG1_ACT_MODE_MASK GENMASK(3, 2)
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#define AST2600_I3CG_REG1_ACT_MODE(x) (((x) << 2) & AST2600_I3CG_REG1_ACT_MODE_MASK)
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#define AST2600_I3CG_REG1_PENDING_INT_MASK GENMASK(7, 4)
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#define AST2600_I3CG_REG1_PENDING_INT(x) (((x) << 4) & AST2600_I3CG_REG1_PENDING_INT_MASK)
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#define AST2600_I3CG_REG1_SA_MASK GENMASK(14, 8)
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#define AST2600_I3CG_REG1_SA(x) (((x) << 8) & AST2600_I3CG_REG1_SA_MASK)
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#define AST2600_I3CG_REG1_SA_EN BIT(15)
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#define AST2600_I3CG_REG1_INST_ID_MASK GENMASK(19, 16)
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#define AST2600_I3CG_REG1_INST_ID(x) (((x) << 16) & AST2600_I3CG_REG1_INST_ID_MASK)
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#define AST2600_DEFAULT_SDA_PULLUP_OHMS 2000
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#define DEV_ADDR_TABLE_IBI_PEC BIT(11)
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struct ast2600_i3c {
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struct dw_i3c_master dw;
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struct regmap *global_regs;
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unsigned int global_idx;
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unsigned int sda_pullup;
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};
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static struct ast2600_i3c *to_ast2600_i3c(struct dw_i3c_master *dw)
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{
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return container_of(dw, struct ast2600_i3c, dw);
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}
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static int ast2600_i3c_pullup_to_reg(unsigned int ohms, u32 *regp)
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{
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u32 reg;
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switch (ohms) {
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case 2000:
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reg = AST2600_I3CG_REG0_SDA_PULLUP_EN_2K;
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break;
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case 750:
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reg = AST2600_I3CG_REG0_SDA_PULLUP_EN_750;
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break;
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case 545:
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reg = AST2600_I3CG_REG0_SDA_PULLUP_EN_545;
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break;
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default:
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return -EINVAL;
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}
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if (regp)
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*regp = reg;
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return 0;
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}
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static int ast2600_i3c_init(struct dw_i3c_master *dw)
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{
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struct ast2600_i3c *i3c = to_ast2600_i3c(dw);
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u32 reg = 0;
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int rc;
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/* reg0: set SDA pullup values */
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rc = ast2600_i3c_pullup_to_reg(i3c->sda_pullup, ®);
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if (rc)
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return rc;
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rc = regmap_write(i3c->global_regs,
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AST2600_I3CG_REG0(i3c->global_idx), reg);
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if (rc)
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return rc;
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/* reg1: set up the instance id, but leave everything else disabled,
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* as it's all for client mode
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*/
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reg = AST2600_I3CG_REG1_INST_ID(i3c->global_idx);
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rc = regmap_write(i3c->global_regs,
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AST2600_I3CG_REG1(i3c->global_idx), reg);
|
||||
|
||||
return rc;
|
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}
|
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|
||||
static void ast2600_i3c_set_dat_ibi(struct dw_i3c_master *i3c,
|
||||
struct i3c_dev_desc *dev,
|
||||
bool enable, u32 *dat)
|
||||
{
|
||||
/*
|
||||
* The ast2600 i3c controller will lock up on receiving 4n+1-byte IBIs
|
||||
* if the PEC is disabled. We have no way to restrict the length of
|
||||
* IBIs sent to the controller, so we need to unconditionally enable
|
||||
* PEC checking, which means we drop a byte of payload data
|
||||
*/
|
||||
if (enable && dev->info.bcr & I3C_BCR_IBI_PAYLOAD) {
|
||||
dev_warn_once(&i3c->base.dev,
|
||||
"Enabling PEC workaround. IBI payloads will be truncated\n");
|
||||
*dat |= DEV_ADDR_TABLE_IBI_PEC;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct dw_i3c_platform_ops ast2600_i3c_ops = {
|
||||
.init = ast2600_i3c_init,
|
||||
.set_dat_ibi = ast2600_i3c_set_dat_ibi,
|
||||
};
|
||||
|
||||
static int ast2600_i3c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct of_phandle_args gspec;
|
||||
struct ast2600_i3c *i3c;
|
||||
int rc;
|
||||
|
||||
i3c = devm_kzalloc(&pdev->dev, sizeof(*i3c), GFP_KERNEL);
|
||||
if (!i3c)
|
||||
return -ENOMEM;
|
||||
|
||||
rc = of_parse_phandle_with_fixed_args(np, "aspeed,global-regs", 1, 0,
|
||||
&gspec);
|
||||
if (rc)
|
||||
return -ENODEV;
|
||||
|
||||
i3c->global_regs = syscon_node_to_regmap(gspec.np);
|
||||
of_node_put(gspec.np);
|
||||
|
||||
if (IS_ERR(i3c->global_regs))
|
||||
return PTR_ERR(i3c->global_regs);
|
||||
|
||||
i3c->global_idx = gspec.args[0];
|
||||
|
||||
rc = of_property_read_u32(np, "sda-pullup-ohms", &i3c->sda_pullup);
|
||||
if (rc)
|
||||
i3c->sda_pullup = AST2600_DEFAULT_SDA_PULLUP_OHMS;
|
||||
|
||||
rc = ast2600_i3c_pullup_to_reg(i3c->sda_pullup, NULL);
|
||||
if (rc)
|
||||
dev_err(&pdev->dev, "invalid sda-pullup value %d\n",
|
||||
i3c->sda_pullup);
|
||||
|
||||
i3c->dw.platform_ops = &ast2600_i3c_ops;
|
||||
i3c->dw.ibi_capable = true;
|
||||
return dw_i3c_common_probe(&i3c->dw, pdev);
|
||||
}
|
||||
|
||||
static void ast2600_i3c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_i3c_master *dw_i3c = platform_get_drvdata(pdev);
|
||||
|
||||
dw_i3c_common_remove(dw_i3c);
|
||||
}
|
||||
|
||||
static const struct of_device_id ast2600_i3c_master_of_match[] = {
|
||||
{ .compatible = "aspeed,ast2600-i3c", },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ast2600_i3c_master_of_match);
|
||||
|
||||
static struct platform_driver ast2600_i3c_driver = {
|
||||
.probe = ast2600_i3c_probe,
|
||||
.remove_new = ast2600_i3c_remove,
|
||||
.driver = {
|
||||
.name = "ast2600-i3c-master",
|
||||
.of_match_table = ast2600_i3c_master_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(ast2600_i3c_driver);
|
||||
|
||||
MODULE_AUTHOR("Jeremy Kerr <jk@codeconstruct.com.au>");
|
||||
MODULE_DESCRIPTION("ASPEED AST2600 I3C driver");
|
||||
MODULE_LICENSE("GPL");
|
@ -21,6 +21,8 @@
|
||||
#include <linux/reset.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "dw-i3c-master.h"
|
||||
|
||||
#define DEVICE_CTRL 0x0
|
||||
#define DEV_CTRL_ENABLE BIT(31)
|
||||
#define DEV_CTRL_RESUME BIT(30)
|
||||
@ -74,7 +76,22 @@
|
||||
|
||||
#define RX_TX_DATA_PORT 0x14
|
||||
#define IBI_QUEUE_STATUS 0x18
|
||||
#define IBI_QUEUE_STATUS_IBI_ID(x) (((x) & GENMASK(15, 8)) >> 8)
|
||||
#define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0))
|
||||
#define IBI_QUEUE_IBI_ADDR(x) (IBI_QUEUE_STATUS_IBI_ID(x) >> 1)
|
||||
#define IBI_QUEUE_IBI_RNW(x) (IBI_QUEUE_STATUS_IBI_ID(x) & BIT(0))
|
||||
#define IBI_TYPE_MR(x) \
|
||||
((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
|
||||
#define IBI_TYPE_HJ(x) \
|
||||
((IBI_QUEUE_IBI_ADDR(x) == I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
|
||||
#define IBI_TYPE_SIRQ(x) \
|
||||
((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && IBI_QUEUE_IBI_RNW(x))
|
||||
|
||||
#define QUEUE_THLD_CTRL 0x1c
|
||||
#define QUEUE_THLD_CTRL_IBI_STAT_MASK GENMASK(31, 24)
|
||||
#define QUEUE_THLD_CTRL_IBI_STAT(x) (((x) - 1) << 24)
|
||||
#define QUEUE_THLD_CTRL_IBI_DATA_MASK GENMASK(20, 16)
|
||||
#define QUEUE_THLD_CTRL_IBI_DATA(x) ((x) << 16)
|
||||
#define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8)
|
||||
#define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8)
|
||||
|
||||
@ -184,13 +201,13 @@
|
||||
#define EXTENDED_CAPABILITY 0xe8
|
||||
#define SLAVE_CONFIG 0xec
|
||||
|
||||
#define DEV_ADDR_TABLE_IBI_MDB BIT(12)
|
||||
#define DEV_ADDR_TABLE_SIR_REJECT BIT(13)
|
||||
#define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31)
|
||||
#define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16))
|
||||
#define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0))
|
||||
#define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2))
|
||||
|
||||
#define MAX_DEVS 32
|
||||
|
||||
#define I3C_BUS_SDR1_SCL_RATE 8000000
|
||||
#define I3C_BUS_SDR2_SCL_RATE 6000000
|
||||
#define I3C_BUS_SDR3_SCL_RATE 4000000
|
||||
@ -201,11 +218,6 @@
|
||||
|
||||
#define XFER_TIMEOUT (msecs_to_jiffies(1000))
|
||||
|
||||
struct dw_i3c_master_caps {
|
||||
u8 cmdfifodepth;
|
||||
u8 datafifodepth;
|
||||
};
|
||||
|
||||
struct dw_i3c_cmd {
|
||||
u32 cmd_lo;
|
||||
u32 cmd_hi;
|
||||
@ -224,27 +236,9 @@ struct dw_i3c_xfer {
|
||||
struct dw_i3c_cmd cmds[];
|
||||
};
|
||||
|
||||
struct dw_i3c_master {
|
||||
struct i3c_master_controller base;
|
||||
u16 maxdevs;
|
||||
u16 datstartaddr;
|
||||
u32 free_pos;
|
||||
struct {
|
||||
struct list_head list;
|
||||
struct dw_i3c_xfer *cur;
|
||||
spinlock_t lock;
|
||||
} xferqueue;
|
||||
struct dw_i3c_master_caps caps;
|
||||
void __iomem *regs;
|
||||
struct reset_control *core_rst;
|
||||
struct clk *core_clk;
|
||||
char version[5];
|
||||
char type[5];
|
||||
u8 addrs[MAX_DEVS];
|
||||
};
|
||||
|
||||
struct dw_i3c_i2c_dev_data {
|
||||
u8 index;
|
||||
struct i3c_generic_ibi_pool *ibi_pool;
|
||||
};
|
||||
|
||||
static u8 even_parity(u8 p)
|
||||
@ -315,7 +309,7 @@ static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
|
||||
int pos;
|
||||
|
||||
for (pos = 0; pos < master->maxdevs; pos++) {
|
||||
if (addr == master->addrs[pos])
|
||||
if (addr == master->devs[pos].addr)
|
||||
return pos;
|
||||
}
|
||||
|
||||
@ -342,18 +336,30 @@ static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
|
||||
}
|
||||
}
|
||||
|
||||
static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
|
||||
u8 *bytes, int nbytes)
|
||||
static void dw_i3c_master_read_fifo(struct dw_i3c_master *master,
|
||||
int reg, u8 *bytes, int nbytes)
|
||||
{
|
||||
readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
|
||||
readsl(master->regs + reg, bytes, nbytes / 4);
|
||||
if (nbytes & 3) {
|
||||
u32 tmp;
|
||||
|
||||
readsl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
|
||||
readsl(master->regs + reg, &tmp, 1);
|
||||
memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
|
||||
}
|
||||
}
|
||||
|
||||
static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
|
||||
u8 *bytes, int nbytes)
|
||||
{
|
||||
return dw_i3c_master_read_fifo(master, RX_TX_DATA_PORT, bytes, nbytes);
|
||||
}
|
||||
|
||||
static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master,
|
||||
u8 *bytes, int nbytes)
|
||||
{
|
||||
return dw_i3c_master_read_fifo(master, IBI_QUEUE_STATUS, bytes, nbytes);
|
||||
}
|
||||
|
||||
static struct dw_i3c_xfer *
|
||||
dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
|
||||
{
|
||||
@ -538,7 +544,11 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
|
||||
scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
|
||||
writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
|
||||
|
||||
if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT))
|
||||
/*
|
||||
* In pure i3c mode, MST_FREE represents tCAS. In shared mode, this
|
||||
* will be set up by dw_i2c_clk_cfg as tLOW.
|
||||
*/
|
||||
if (master->base.bus.mode == I3C_BUS_MODE_PURE)
|
||||
writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
|
||||
|
||||
lcnt = max_t(u8,
|
||||
@ -598,6 +608,10 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
|
||||
u32 thld_ctrl;
|
||||
int ret;
|
||||
|
||||
ret = master->platform_ops->init(master);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
switch (bus->mode) {
|
||||
case I3C_BUS_MODE_MIXED_FAST:
|
||||
case I3C_BUS_MODE_MIXED_LIMITED:
|
||||
@ -615,7 +629,11 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
|
||||
}
|
||||
|
||||
thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
|
||||
thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
|
||||
thld_ctrl &= ~(QUEUE_THLD_CTRL_RESP_BUF_MASK |
|
||||
QUEUE_THLD_CTRL_IBI_STAT_MASK |
|
||||
QUEUE_THLD_CTRL_IBI_STAT_MASK);
|
||||
thld_ctrl |= QUEUE_THLD_CTRL_IBI_STAT(1) |
|
||||
QUEUE_THLD_CTRL_IBI_DATA(31);
|
||||
writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
|
||||
|
||||
thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
|
||||
@ -779,7 +797,7 @@ static int dw_i3c_master_daa(struct i3c_master_controller *m)
|
||||
if (ret < 0)
|
||||
return -ENOSPC;
|
||||
|
||||
master->addrs[pos] = ret;
|
||||
master->devs[pos].addr = ret;
|
||||
p = even_parity(ret);
|
||||
last_addr = ret;
|
||||
ret |= (p << 7);
|
||||
@ -816,7 +834,7 @@ static int dw_i3c_master_daa(struct i3c_master_controller *m)
|
||||
|
||||
for (pos = 0; pos < master->maxdevs; pos++) {
|
||||
if (newdevs & BIT(pos))
|
||||
i3c_master_add_i3c_dev_locked(m, master->addrs[pos]);
|
||||
i3c_master_add_i3c_dev_locked(m, master->devs[pos].addr);
|
||||
}
|
||||
|
||||
dw_i3c_master_free_xfer(xfer);
|
||||
@ -887,6 +905,13 @@ static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
|
||||
if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
|
||||
dw_i3c_master_dequeue_xfer(master, xfer);
|
||||
|
||||
for (i = 0; i < i3c_nxfers; i++) {
|
||||
struct dw_i3c_cmd *cmd = &xfer->cmds[i];
|
||||
|
||||
if (i3c_xfers[i].rnw)
|
||||
i3c_xfers[i].len = cmd->rx_len;
|
||||
}
|
||||
|
||||
ret = xfer->ret;
|
||||
dw_i3c_master_free_xfer(xfer);
|
||||
|
||||
@ -908,11 +933,11 @@ static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
|
||||
master->regs +
|
||||
DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
|
||||
|
||||
master->addrs[data->index] = 0;
|
||||
master->devs[data->index].addr = 0;
|
||||
master->free_pos |= BIT(data->index);
|
||||
|
||||
data->index = pos;
|
||||
master->addrs[pos] = dev->info.dyn_addr;
|
||||
master->devs[pos].addr = dev->info.dyn_addr;
|
||||
master->free_pos &= ~BIT(pos);
|
||||
}
|
||||
|
||||
@ -920,7 +945,7 @@ static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
|
||||
master->regs +
|
||||
DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
|
||||
|
||||
master->addrs[data->index] = dev->info.dyn_addr;
|
||||
master->devs[data->index].addr = dev->info.dyn_addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -941,11 +966,11 @@ static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
|
||||
return -ENOMEM;
|
||||
|
||||
data->index = pos;
|
||||
master->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr;
|
||||
master->devs[pos].addr = dev->info.dyn_addr ? : dev->info.static_addr;
|
||||
master->free_pos &= ~BIT(pos);
|
||||
i3c_dev_set_master_data(dev, data);
|
||||
|
||||
writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->addrs[pos]),
|
||||
writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->devs[pos].addr),
|
||||
master->regs +
|
||||
DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
|
||||
|
||||
@ -963,7 +988,7 @@ static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
|
||||
DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
|
||||
|
||||
i3c_dev_set_master_data(dev, NULL);
|
||||
master->addrs[data->index] = 0;
|
||||
master->devs[data->index].addr = 0;
|
||||
master->free_pos |= BIT(data->index);
|
||||
kfree(data);
|
||||
}
|
||||
@ -1049,7 +1074,7 @@ static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
|
||||
return -ENOMEM;
|
||||
|
||||
data->index = pos;
|
||||
master->addrs[pos] = dev->addr;
|
||||
master->devs[pos].addr = dev->addr;
|
||||
master->free_pos &= ~BIT(pos);
|
||||
i2c_dev_set_master_data(dev, data);
|
||||
|
||||
@ -1072,11 +1097,243 @@ static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
|
||||
DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
|
||||
|
||||
i2c_dev_set_master_data(dev, NULL);
|
||||
master->addrs[data->index] = 0;
|
||||
master->devs[data->index].addr = 0;
|
||||
master->free_pos |= BIT(data->index);
|
||||
kfree(data);
|
||||
}
|
||||
|
||||
static int dw_i3c_master_request_ibi(struct i3c_dev_desc *dev,
|
||||
const struct i3c_ibi_setup *req)
|
||||
{
|
||||
struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
|
||||
struct i3c_master_controller *m = i3c_dev_get_master(dev);
|
||||
struct dw_i3c_master *master = to_dw_i3c_master(m);
|
||||
unsigned long flags;
|
||||
|
||||
data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
|
||||
if (IS_ERR(data->ibi_pool))
|
||||
return PTR_ERR(data->ibi_pool);
|
||||
|
||||
spin_lock_irqsave(&master->devs_lock, flags);
|
||||
master->devs[data->index].ibi_dev = dev;
|
||||
spin_unlock_irqrestore(&master->devs_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dw_i3c_master_free_ibi(struct i3c_dev_desc *dev)
|
||||
{
|
||||
struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
|
||||
struct i3c_master_controller *m = i3c_dev_get_master(dev);
|
||||
struct dw_i3c_master *master = to_dw_i3c_master(m);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&master->devs_lock, flags);
|
||||
master->devs[data->index].ibi_dev = NULL;
|
||||
spin_unlock_irqrestore(&master->devs_lock, flags);
|
||||
|
||||
i3c_generic_ibi_free_pool(data->ibi_pool);
|
||||
data->ibi_pool = NULL;
|
||||
}
|
||||
|
||||
static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master,
|
||||
struct i3c_dev_desc *dev,
|
||||
u8 idx, bool enable)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 dat_entry, reg;
|
||||
bool global;
|
||||
|
||||
dat_entry = DEV_ADDR_TABLE_LOC(master->datstartaddr, idx);
|
||||
|
||||
spin_lock_irqsave(&master->devs_lock, flags);
|
||||
reg = readl(master->regs + dat_entry);
|
||||
if (enable) {
|
||||
reg &= ~DEV_ADDR_TABLE_SIR_REJECT;
|
||||
if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD)
|
||||
reg |= DEV_ADDR_TABLE_IBI_MDB;
|
||||
} else {
|
||||
reg |= DEV_ADDR_TABLE_SIR_REJECT;
|
||||
}
|
||||
master->platform_ops->set_dat_ibi(master, dev, enable, ®);
|
||||
writel(reg, master->regs + dat_entry);
|
||||
|
||||
reg = readl(master->regs + IBI_SIR_REQ_REJECT);
|
||||
if (enable) {
|
||||
global = reg == 0xffffffff;
|
||||
reg &= ~BIT(idx);
|
||||
} else {
|
||||
global = reg == 0;
|
||||
reg |= BIT(idx);
|
||||
}
|
||||
writel(reg, master->regs + IBI_SIR_REQ_REJECT);
|
||||
|
||||
if (global) {
|
||||
reg = readl(master->regs + INTR_STATUS_EN);
|
||||
reg &= ~INTR_IBI_THLD_STAT;
|
||||
if (enable)
|
||||
reg |= INTR_IBI_THLD_STAT;
|
||||
writel(reg, master->regs + INTR_STATUS_EN);
|
||||
|
||||
reg = readl(master->regs + INTR_SIGNAL_EN);
|
||||
reg &= ~INTR_IBI_THLD_STAT;
|
||||
if (enable)
|
||||
reg |= INTR_IBI_THLD_STAT;
|
||||
writel(reg, master->regs + INTR_SIGNAL_EN);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&master->devs_lock, flags);
|
||||
}
|
||||
|
||||
static int dw_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
|
||||
{
|
||||
struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
|
||||
struct i3c_master_controller *m = i3c_dev_get_master(dev);
|
||||
struct dw_i3c_master *master = to_dw_i3c_master(m);
|
||||
int rc;
|
||||
|
||||
dw_i3c_master_set_sir_enabled(master, dev, data->index, true);
|
||||
|
||||
rc = i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
|
||||
|
||||
if (rc)
|
||||
dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int dw_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
|
||||
{
|
||||
struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
|
||||
struct i3c_master_controller *m = i3c_dev_get_master(dev);
|
||||
struct dw_i3c_master *master = to_dw_i3c_master(m);
|
||||
int rc;
|
||||
|
||||
rc = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
dw_i3c_master_set_sir_enabled(master, dev, data->index, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
|
||||
struct i3c_ibi_slot *slot)
|
||||
{
|
||||
struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
|
||||
|
||||
i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
|
||||
}
|
||||
|
||||
static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < DIV_ROUND_UP(len, 4); i++)
|
||||
readl(master->regs + IBI_QUEUE_STATUS);
|
||||
}
|
||||
|
||||
static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master,
|
||||
u32 status)
|
||||
{
|
||||
struct dw_i3c_i2c_dev_data *data;
|
||||
struct i3c_ibi_slot *slot;
|
||||
struct i3c_dev_desc *dev;
|
||||
unsigned long flags;
|
||||
u8 addr, len;
|
||||
int idx;
|
||||
|
||||
addr = IBI_QUEUE_IBI_ADDR(status);
|
||||
len = IBI_QUEUE_STATUS_DATA_LEN(status);
|
||||
|
||||
/*
|
||||
* We be tempted to check the error status in bit 30; however, due
|
||||
* to the PEC errata workaround on some platform implementations (see
|
||||
* ast2600_i3c_set_dat_ibi()), those will almost always have a PEC
|
||||
* error on IBI payload data, as well as losing the last byte of
|
||||
* payload.
|
||||
*
|
||||
* If we implement error status checking on that bit, we may need
|
||||
* a new platform op to validate it.
|
||||
*/
|
||||
|
||||
spin_lock_irqsave(&master->devs_lock, flags);
|
||||
idx = dw_i3c_master_get_addr_pos(master, addr);
|
||||
if (idx < 0) {
|
||||
dev_dbg_ratelimited(&master->base.dev,
|
||||
"IBI from unknown addr 0x%x\n", addr);
|
||||
goto err_drain;
|
||||
}
|
||||
|
||||
dev = master->devs[idx].ibi_dev;
|
||||
if (!dev || !dev->ibi) {
|
||||
dev_dbg_ratelimited(&master->base.dev,
|
||||
"IBI from non-requested dev idx %d\n", idx);
|
||||
goto err_drain;
|
||||
}
|
||||
|
||||
data = i3c_dev_get_master_data(dev);
|
||||
slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
|
||||
if (!slot) {
|
||||
dev_dbg_ratelimited(&master->base.dev,
|
||||
"No IBI slots available\n");
|
||||
goto err_drain;
|
||||
}
|
||||
|
||||
if (dev->ibi->max_payload_len < len) {
|
||||
dev_dbg_ratelimited(&master->base.dev,
|
||||
"IBI payload len %d greater than max %d\n",
|
||||
len, dev->ibi->max_payload_len);
|
||||
goto err_drain;
|
||||
}
|
||||
|
||||
if (len) {
|
||||
dw_i3c_master_read_ibi_fifo(master, slot->data, len);
|
||||
slot->len = len;
|
||||
}
|
||||
i3c_master_queue_ibi(dev, slot);
|
||||
|
||||
spin_unlock_irqrestore(&master->devs_lock, flags);
|
||||
|
||||
return;
|
||||
|
||||
err_drain:
|
||||
dw_i3c_master_drain_ibi_queue(master, len);
|
||||
|
||||
spin_unlock_irqrestore(&master->devs_lock, flags);
|
||||
}
|
||||
|
||||
/* "ibis": referring to In-Band Interrupts, and not
|
||||
* https://en.wikipedia.org/wiki/Australian_white_ibis. The latter should
|
||||
* not be handled.
|
||||
*/
|
||||
static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master)
|
||||
{
|
||||
unsigned int i, len, n_ibis;
|
||||
u32 reg;
|
||||
|
||||
reg = readl(master->regs + QUEUE_STATUS_LEVEL);
|
||||
n_ibis = QUEUE_STATUS_IBI_STATUS_CNT(reg);
|
||||
if (!n_ibis)
|
||||
return;
|
||||
|
||||
for (i = 0; i < n_ibis; i++) {
|
||||
reg = readl(master->regs + IBI_QUEUE_STATUS);
|
||||
|
||||
if (IBI_TYPE_SIRQ(reg)) {
|
||||
dw_i3c_master_handle_ibi_sir(master, reg);
|
||||
} else {
|
||||
len = IBI_QUEUE_STATUS_DATA_LEN(reg);
|
||||
dev_info(&master->base.dev,
|
||||
"unsupported IBI type 0x%lx len %d\n",
|
||||
IBI_QUEUE_STATUS_IBI_ID(reg), len);
|
||||
dw_i3c_master_drain_ibi_queue(master, len);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
|
||||
{
|
||||
struct dw_i3c_master *master = dev_id;
|
||||
@ -1095,6 +1352,9 @@ static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
|
||||
writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
|
||||
spin_unlock(&master->xferqueue.lock);
|
||||
|
||||
if (status & INTR_IBI_THLD_STAT)
|
||||
dw_i3c_master_irq_handle_ibis(master);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
@ -1113,14 +1373,51 @@ static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
|
||||
.i2c_xfers = dw_i3c_master_i2c_xfers,
|
||||
};
|
||||
|
||||
static int dw_i3c_probe(struct platform_device *pdev)
|
||||
static const struct i3c_master_controller_ops dw_mipi_i3c_ibi_ops = {
|
||||
.bus_init = dw_i3c_master_bus_init,
|
||||
.bus_cleanup = dw_i3c_master_bus_cleanup,
|
||||
.attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
|
||||
.reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
|
||||
.detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
|
||||
.do_daa = dw_i3c_master_daa,
|
||||
.supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
|
||||
.send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
|
||||
.priv_xfers = dw_i3c_master_priv_xfers,
|
||||
.attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
|
||||
.detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
|
||||
.i2c_xfers = dw_i3c_master_i2c_xfers,
|
||||
.request_ibi = dw_i3c_master_request_ibi,
|
||||
.free_ibi = dw_i3c_master_free_ibi,
|
||||
.enable_ibi = dw_i3c_master_enable_ibi,
|
||||
.disable_ibi = dw_i3c_master_disable_ibi,
|
||||
.recycle_ibi_slot = dw_i3c_master_recycle_ibi_slot,
|
||||
};
|
||||
|
||||
/* default platform ops implementations */
|
||||
static int dw_i3c_platform_init_nop(struct dw_i3c_master *i3c)
|
||||
{
|
||||
struct dw_i3c_master *master;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dw_i3c_platform_set_dat_ibi_nop(struct dw_i3c_master *i3c,
|
||||
struct i3c_dev_desc *dev,
|
||||
bool enable, u32 *dat)
|
||||
{
|
||||
}
|
||||
|
||||
static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = {
|
||||
.init = dw_i3c_platform_init_nop,
|
||||
.set_dat_ibi = dw_i3c_platform_set_dat_ibi_nop,
|
||||
};
|
||||
|
||||
int dw_i3c_common_probe(struct dw_i3c_master *master,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
const struct i3c_master_controller_ops *ops;
|
||||
int ret, irq;
|
||||
|
||||
master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
|
||||
if (!master)
|
||||
return -ENOMEM;
|
||||
if (!master->platform_ops)
|
||||
master->platform_ops = &dw_i3c_platform_ops_default;
|
||||
|
||||
master->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(master->regs))
|
||||
@ -1166,8 +1463,11 @@ static int dw_i3c_probe(struct platform_device *pdev)
|
||||
master->maxdevs = ret >> 16;
|
||||
master->free_pos = GENMASK(master->maxdevs - 1, 0);
|
||||
|
||||
ret = i3c_master_register(&master->base, &pdev->dev,
|
||||
&dw_mipi_i3c_ops, false);
|
||||
ops = &dw_mipi_i3c_ops;
|
||||
if (master->ibi_capable)
|
||||
ops = &dw_mipi_i3c_ibi_ops;
|
||||
|
||||
ret = i3c_master_register(&master->base, &pdev->dev, ops, false);
|
||||
if (ret)
|
||||
goto err_assert_rst;
|
||||
|
||||
@ -1181,21 +1481,36 @@ err_disable_core_clk:
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dw_i3c_common_probe);
|
||||
|
||||
static int dw_i3c_remove(struct platform_device *pdev)
|
||||
void dw_i3c_common_remove(struct dw_i3c_master *master)
|
||||
{
|
||||
struct dw_i3c_master *master = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = i3c_master_unregister(&master->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
i3c_master_unregister(&master->base);
|
||||
|
||||
reset_control_assert(master->core_rst);
|
||||
|
||||
clk_disable_unprepare(master->core_clk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dw_i3c_common_remove);
|
||||
|
||||
return 0;
|
||||
/* base platform implementation */
|
||||
|
||||
static int dw_i3c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_i3c_master *master;
|
||||
|
||||
master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
|
||||
if (!master)
|
||||
return -ENOMEM;
|
||||
|
||||
return dw_i3c_common_probe(master, pdev);
|
||||
}
|
||||
|
||||
static void dw_i3c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct dw_i3c_master *master = platform_get_drvdata(pdev);
|
||||
|
||||
dw_i3c_common_remove(master);
|
||||
}
|
||||
|
||||
static const struct of_device_id dw_i3c_master_of_match[] = {
|
||||
@ -1206,10 +1521,10 @@ MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);
|
||||
|
||||
static struct platform_driver dw_i3c_driver = {
|
||||
.probe = dw_i3c_probe,
|
||||
.remove = dw_i3c_remove,
|
||||
.remove_new = dw_i3c_remove,
|
||||
.driver = {
|
||||
.name = "dw-i3c-master",
|
||||
.of_match_table = of_match_ptr(dw_i3c_master_of_match),
|
||||
.of_match_table = dw_i3c_master_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(dw_i3c_driver);
|
||||
|
84
drivers/i3c/master/dw-i3c-master.h
Normal file
84
drivers/i3c/master/dw-i3c-master.h
Normal file
@ -0,0 +1,84 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2023 Code Construct
|
||||
*
|
||||
* Author: Jeremy Kerr <jk@codeconstruct.com.au>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/i3c/master.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define DW_I3C_MAX_DEVS 32
|
||||
|
||||
struct dw_i3c_master_caps {
|
||||
u8 cmdfifodepth;
|
||||
u8 datafifodepth;
|
||||
};
|
||||
|
||||
struct dw_i3c_dat_entry {
|
||||
u8 addr;
|
||||
struct i3c_dev_desc *ibi_dev;
|
||||
};
|
||||
|
||||
struct dw_i3c_master {
|
||||
struct i3c_master_controller base;
|
||||
u16 maxdevs;
|
||||
u16 datstartaddr;
|
||||
u32 free_pos;
|
||||
struct {
|
||||
struct list_head list;
|
||||
struct dw_i3c_xfer *cur;
|
||||
spinlock_t lock;
|
||||
} xferqueue;
|
||||
struct dw_i3c_master_caps caps;
|
||||
void __iomem *regs;
|
||||
struct reset_control *core_rst;
|
||||
struct clk *core_clk;
|
||||
char version[5];
|
||||
char type[5];
|
||||
bool ibi_capable;
|
||||
|
||||
/*
|
||||
* Per-device hardware data, used to manage the device address table
|
||||
* (DAT)
|
||||
*
|
||||
* Locking: the devs array may be referenced in IRQ context while
|
||||
* processing an IBI. However, IBIs (for a specific device, which
|
||||
* implies a specific DAT entry) can only happen while interrupts are
|
||||
* requested for that device, which is serialised against other
|
||||
* insertions/removals from the array by the global i3c infrastructure.
|
||||
* So, devs_lock protects against concurrent updates to devs->ibi_dev
|
||||
* between request_ibi/free_ibi and the IBI irq event.
|
||||
*/
|
||||
struct dw_i3c_dat_entry devs[DW_I3C_MAX_DEVS];
|
||||
spinlock_t devs_lock;
|
||||
|
||||
/* platform-specific data */
|
||||
const struct dw_i3c_platform_ops *platform_ops;
|
||||
};
|
||||
|
||||
struct dw_i3c_platform_ops {
|
||||
/*
|
||||
* Called on early bus init: the i3c has been set up, but before any
|
||||
* transactions have taken place. Platform implementations may use to
|
||||
* perform actual device enabling with the i3c core ready.
|
||||
*/
|
||||
int (*init)(struct dw_i3c_master *i3c);
|
||||
|
||||
/*
|
||||
* Initialise a DAT entry to enable/disable IBIs. Allows the platform
|
||||
* to perform any device workarounds on the DAT entry before
|
||||
* inserting into the hardware table.
|
||||
*
|
||||
* Called with the DAT lock held; must not sleep.
|
||||
*/
|
||||
void (*set_dat_ibi)(struct dw_i3c_master *i3c,
|
||||
struct i3c_dev_desc *dev, bool enable, u32 *reg);
|
||||
};
|
||||
|
||||
extern int dw_i3c_common_probe(struct dw_i3c_master *master,
|
||||
struct platform_device *pdev);
|
||||
extern void dw_i3c_common_remove(struct dw_i3c_master *master);
|
||||
|
@ -1662,24 +1662,19 @@ err_disable_pclk:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int cdns_i3c_master_remove(struct platform_device *pdev)
|
||||
static void cdns_i3c_master_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct cdns_i3c_master *master = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = i3c_master_unregister(&master->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
i3c_master_unregister(&master->base);
|
||||
|
||||
clk_disable_unprepare(master->sysclk);
|
||||
clk_disable_unprepare(master->pclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver cdns_i3c_master = {
|
||||
.probe = cdns_i3c_master_probe,
|
||||
.remove = cdns_i3c_master_remove,
|
||||
.remove_new = cdns_i3c_master_remove,
|
||||
.driver = {
|
||||
.name = "cdns-i3c-master",
|
||||
.of_match_table = cdns_i3c_master_of_ids,
|
||||
|
@ -765,11 +765,11 @@ static int i3c_hci_probe(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int i3c_hci_remove(struct platform_device *pdev)
|
||||
static void i3c_hci_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct i3c_hci *hci = platform_get_drvdata(pdev);
|
||||
|
||||
return i3c_master_unregister(&hci->master);
|
||||
i3c_master_unregister(&hci->master);
|
||||
}
|
||||
|
||||
static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
|
||||
@ -780,7 +780,7 @@ MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
|
||||
|
||||
static struct platform_driver i3c_hci_driver = {
|
||||
.probe = i3c_hci_probe,
|
||||
.remove = i3c_hci_remove,
|
||||
.remove_new = i3c_hci_remove,
|
||||
.driver = {
|
||||
.name = "mipi-i3c-hci",
|
||||
.of_match_table = of_match_ptr(i3c_hci_of_match),
|
||||
|
@ -1569,19 +1569,14 @@ err_disable_clks:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int svc_i3c_master_remove(struct platform_device *pdev)
|
||||
static void svc_i3c_master_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct svc_i3c_master *master = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = i3c_master_unregister(&master->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
i3c_master_unregister(&master->base);
|
||||
|
||||
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused svc_i3c_runtime_suspend(struct device *dev)
|
||||
@ -1619,7 +1614,7 @@ MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl);
|
||||
|
||||
static struct platform_driver svc_i3c_master = {
|
||||
.probe = svc_i3c_master_probe,
|
||||
.remove = svc_i3c_master_remove,
|
||||
.remove_new = svc_i3c_master_remove,
|
||||
.driver = {
|
||||
.name = "silvaco-i3c-master",
|
||||
.of_match_table = svc_i3c_master_of_match_tbl,
|
||||
|
@ -22,9 +22,10 @@
|
||||
#define I3C_BROADCAST_ADDR 0x7e
|
||||
#define I3C_MAX_ADDR GENMASK(6, 0)
|
||||
|
||||
struct i2c_client;
|
||||
|
||||
struct i3c_master_controller;
|
||||
struct i3c_bus;
|
||||
struct i2c_device;
|
||||
struct i3c_device;
|
||||
|
||||
/**
|
||||
@ -541,7 +542,7 @@ int i3c_master_register(struct i3c_master_controller *master,
|
||||
struct device *parent,
|
||||
const struct i3c_master_controller_ops *ops,
|
||||
bool secondary);
|
||||
int i3c_master_unregister(struct i3c_master_controller *master);
|
||||
void i3c_master_unregister(struct i3c_master_controller *master);
|
||||
|
||||
/**
|
||||
* i3c_dev_get_master_data() - get master private data attached to an I3C
|
||||
|
Loading…
Reference in New Issue
Block a user