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media: ti-vpe: cal: Reorder camerarx functions to prepare refactoring
To prepare for the camerarx refactoring, reorder functions without any functional change to ease review of the refactoring itself. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
cd2144603a
commit
e085ede10d
@ -481,6 +481,54 @@ static void cal_quickdump_regs(struct cal_dev *cal)
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* ------------------------------------------------------------------
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*/
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static int cal_camerarx_get_external_info(struct cal_camerarx *phy)
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{
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struct v4l2_ctrl *ctrl;
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if (!phy->sensor)
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return -ENODEV;
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ctrl = v4l2_ctrl_find(phy->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
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if (!ctrl) {
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phy_err(phy, "no pixel rate control in subdev: %s\n",
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phy->sensor->name);
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return -EPIPE;
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}
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phy->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
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phy_dbg(3, phy, "sensor Pixel Rate: %u\n", phy->external_rate);
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return 0;
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}
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static void cal_camerarx_lane_config(struct cal_camerarx *phy)
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{
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u32 val = reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance));
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u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;
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u32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;
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struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
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&phy->endpoint.bus.mipi_csi2;
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int lane;
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set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);
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set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);
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for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) {
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/*
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* Every lane are one nibble apart starting with the
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* clock followed by the data lanes so shift masks by 4.
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*/
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lane_mask <<= 4;
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polarity_mask <<= 4;
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set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);
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set_field(&val, mipi_csi2->lane_polarities[lane + 1],
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polarity_mask);
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}
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reg_write(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), val);
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phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n",
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phy->instance, val);
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}
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static void cal_camerarx_enable(struct cal_camerarx *phy)
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{
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u32 num_lanes = phy->cal->data->camerarx[phy->instance].num_lanes;
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@ -499,6 +547,244 @@ static void cal_camerarx_disable(struct cal_camerarx *phy)
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regmap_field_write(phy->fields[F_CTRLCLKEN], 0);
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}
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/*
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* TCLK values are OK at their reset values
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*/
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#define TCLK_TERM 0
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#define TCLK_MISS 1
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#define TCLK_SETTLE 14
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static void cal_camerarx_config(struct cal_camerarx *phy,
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const struct cal_fmt *fmt)
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{
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unsigned int reg0, reg1;
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unsigned int ths_term, ths_settle;
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unsigned int csi2_ddrclk_khz;
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struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
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&phy->endpoint.bus.mipi_csi2;
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u32 num_lanes = mipi_csi2->num_data_lanes;
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/* DPHY timing configuration */
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/* CSI-2 is DDR and we only count used lanes. */
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csi2_ddrclk_khz = phy->external_rate / 1000
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/ (2 * num_lanes) * fmt->bpp;
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phy_dbg(1, phy, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz);
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/* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */
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ths_term = 20 * csi2_ddrclk_khz / 1000000;
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phy_dbg(1, phy, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
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/* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */
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ths_settle = (105 * csi2_ddrclk_khz / 1000000) + 4;
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phy_dbg(1, phy, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
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reg0 = reg_read(phy, CAL_CSI2_PHY_REG0);
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set_field(®0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
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CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
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set_field(®0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
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set_field(®0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
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phy_dbg(1, phy, "CSI2_%d_REG0 = 0x%08x\n", phy->instance, reg0);
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reg_write(phy, CAL_CSI2_PHY_REG0, reg0);
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reg1 = reg_read(phy, CAL_CSI2_PHY_REG1);
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set_field(®1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
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set_field(®1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
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set_field(®1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
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set_field(®1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
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phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x\n", phy->instance, reg1);
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reg_write(phy, CAL_CSI2_PHY_REG1, reg1);
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}
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static void cal_camerarx_power(struct cal_camerarx *phy, bool enable)
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{
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u32 target_state;
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unsigned int i;
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target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON :
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CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF;
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reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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target_state, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
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for (i = 0; i < 10; i++) {
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u32 current_state;
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current_state = reg_read_field(phy->cal,
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CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
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if (current_state == target_state)
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break;
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usleep_range(1000, 1100);
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}
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if (i == 10)
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phy_err(phy, "Failed to power %s complexio\n",
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enable ? "up" : "down");
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}
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static void cal_camerarx_wait_reset(struct cal_camerarx *phy)
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{
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(750);
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while (time_before(jiffies, timeout)) {
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if (reg_read_field(phy->cal,
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CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
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CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
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break;
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usleep_range(500, 5000);
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}
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if (reg_read_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
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CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
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phy_err(phy, "Timeout waiting for Complex IO reset done\n");
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}
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static void cal_camerarx_wait_stop_state(struct cal_camerarx *phy)
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{
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(750);
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while (time_before(jiffies, timeout)) {
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if (reg_read_field(phy->cal,
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CAL_CSI2_TIMING(phy->instance),
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CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0)
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break;
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usleep_range(500, 5000);
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}
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if (reg_read_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
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CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0)
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phy_err(phy, "Timeout waiting for stop state\n");
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}
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static void cal_camerarx_wait_ready(struct cal_camerarx *phy)
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{
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/* Steps
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* 2. Wait for completion of reset
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* Note if the external sensor is not sending byte clock,
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* the reset will timeout
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* 4.Force FORCERXMODE
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* G. Wait for all enabled lane to reach stop state
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* H. Disable pull down using pad control
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*/
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/* 2. Wait for reset completion */
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cal_camerarx_wait_reset(phy);
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/* 4. G. Wait for all enabled lane to reach stop state */
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cal_camerarx_wait_stop_state(phy);
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phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x (Bit(31,28) should be set!)\n",
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phy->instance, reg_read(phy, CAL_CSI2_PHY_REG1));
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}
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static void cal_camerarx_init(struct cal_camerarx *phy,
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const struct cal_fmt *fmt)
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{
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u32 val;
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u32 sscounter;
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/* Steps
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* 1. Configure D-PHY mode and enable required lanes
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* 2. Reset complex IO - Wait for completion of reset
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* Note if the external sensor is not sending byte clock,
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* the reset will timeout
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* 3 Program Stop States
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* A. Program THS_TERM, THS_SETTLE, etc... Timings parameters
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* in terms of DDR clock periods
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* B. Enable stop state transition timeouts
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* 4.Force FORCERXMODE
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* D. Enable pull down using pad control
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* E. Power up PHY
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* F. Wait for power up completion
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* G. Wait for all enabled lane to reach stop state
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* H. Disable pull down using pad control
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*/
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/* 1. Configure D-PHY mode and enable required lanes */
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cal_camerarx_enable(phy);
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/* 2. Reset complex IO - Do not wait for reset completion */
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reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL,
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CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
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phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n",
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phy->instance,
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reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)));
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/* Dummy read to allow SCP reset to complete */
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reg_read(phy, CAL_CSI2_PHY_REG0);
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/* 3.A. Program Phy Timing Parameters */
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cal_camerarx_config(phy, fmt);
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/* 3.B. Program Stop States */
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/*
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* The stop-state-counter is based on fclk cycles, and we always use
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* the x16 and x4 settings, so stop-state-timeout =
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* fclk-cycle * 16 * 4 * counter.
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*
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* Stop-state-timeout must be more than 100us as per CSI2 spec, so we
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* calculate a timeout that's 100us (rounding up).
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*/
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sscounter = DIV_ROUND_UP(clk_get_rate(phy->cal->fclk), 10000 * 16 * 4);
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val = reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance));
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set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
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set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
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set_field(&val, sscounter, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);
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reg_write(phy->cal, CAL_CSI2_TIMING(phy->instance), val);
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phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n",
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phy->instance,
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reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
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/* 4. Force FORCERXMODE */
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reg_write_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
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1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
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phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n",
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phy->instance,
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reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
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/* E. Power up the PHY using the complex IO */
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cal_camerarx_power(phy, true);
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}
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static void cal_camerarx_deinit(struct cal_camerarx *phy)
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{
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unsigned int i;
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cal_camerarx_power(phy, false);
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/* Assert Comple IO Reset */
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reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL,
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CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
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/* Wait for power down completion */
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for (i = 0; i < 10; i++) {
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if (reg_read_field(phy->cal,
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CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
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CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING)
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break;
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usleep_range(1000, 1100);
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}
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phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset (%d) %s\n",
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phy->instance,
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reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)), i,
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(i >= 10) ? "(timeout)" : "");
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/* Disable the phy */
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cal_camerarx_disable(phy);
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}
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/*
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* Errata i913: CSI2 LDO Needs to be disabled when module is powered on
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*
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@ -584,272 +870,6 @@ static void cal_camerarx_disable_irqs(struct cal_camerarx *phy)
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reg_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0);
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}
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static void cal_camerarx_power(struct cal_camerarx *phy, bool enable)
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{
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u32 target_state;
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unsigned int i;
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target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON :
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CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF;
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reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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target_state, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
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for (i = 0; i < 10; i++) {
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u32 current_state;
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current_state = reg_read_field(phy->cal,
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CAL_CSI2_COMPLEXIO_CFG(phy->instance),
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CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
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if (current_state == target_state)
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break;
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usleep_range(1000, 1100);
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}
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if (i == 10)
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phy_err(phy, "Failed to power %s complexio\n",
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enable ? "up" : "down");
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}
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/*
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* TCLK values are OK at their reset values
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*/
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#define TCLK_TERM 0
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#define TCLK_MISS 1
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#define TCLK_SETTLE 14
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static void cal_camerarx_config(struct cal_camerarx *phy,
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const struct cal_fmt *fmt)
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{
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unsigned int reg0, reg1;
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unsigned int ths_term, ths_settle;
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unsigned int csi2_ddrclk_khz;
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struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
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&phy->endpoint.bus.mipi_csi2;
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u32 num_lanes = mipi_csi2->num_data_lanes;
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/* DPHY timing configuration */
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/* CSI-2 is DDR and we only count used lanes. */
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csi2_ddrclk_khz = phy->external_rate / 1000
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/ (2 * num_lanes) * fmt->bpp;
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phy_dbg(1, phy, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz);
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/* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */
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ths_term = 20 * csi2_ddrclk_khz / 1000000;
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phy_dbg(1, phy, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
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/* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */
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ths_settle = (105 * csi2_ddrclk_khz / 1000000) + 4;
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phy_dbg(1, phy, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
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reg0 = reg_read(phy, CAL_CSI2_PHY_REG0);
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set_field(®0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
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CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
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set_field(®0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
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set_field(®0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
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phy_dbg(1, phy, "CSI2_%d_REG0 = 0x%08x\n", phy->instance, reg0);
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reg_write(phy, CAL_CSI2_PHY_REG0, reg0);
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reg1 = reg_read(phy, CAL_CSI2_PHY_REG1);
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set_field(®1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
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set_field(®1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
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set_field(®1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
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set_field(®1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
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phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x\n", phy->instance, reg1);
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reg_write(phy, CAL_CSI2_PHY_REG1, reg1);
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}
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||||
static void cal_camerarx_init(struct cal_camerarx *phy,
|
||||
const struct cal_fmt *fmt)
|
||||
{
|
||||
u32 val;
|
||||
u32 sscounter;
|
||||
|
||||
/* Steps
|
||||
* 1. Configure D-PHY mode and enable required lanes
|
||||
* 2. Reset complex IO - Wait for completion of reset
|
||||
* Note if the external sensor is not sending byte clock,
|
||||
* the reset will timeout
|
||||
* 3 Program Stop States
|
||||
* A. Program THS_TERM, THS_SETTLE, etc... Timings parameters
|
||||
* in terms of DDR clock periods
|
||||
* B. Enable stop state transition timeouts
|
||||
* 4.Force FORCERXMODE
|
||||
* D. Enable pull down using pad control
|
||||
* E. Power up PHY
|
||||
* F. Wait for power up completion
|
||||
* G. Wait for all enabled lane to reach stop state
|
||||
* H. Disable pull down using pad control
|
||||
*/
|
||||
|
||||
/* 1. Configure D-PHY mode and enable required lanes */
|
||||
cal_camerarx_enable(phy);
|
||||
|
||||
/* 2. Reset complex IO - Do not wait for reset completion */
|
||||
reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL,
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
|
||||
phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n",
|
||||
phy->instance,
|
||||
reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)));
|
||||
|
||||
/* Dummy read to allow SCP reset to complete */
|
||||
reg_read(phy, CAL_CSI2_PHY_REG0);
|
||||
|
||||
/* 3.A. Program Phy Timing Parameters */
|
||||
cal_camerarx_config(phy, fmt);
|
||||
|
||||
/* 3.B. Program Stop States */
|
||||
/*
|
||||
* The stop-state-counter is based on fclk cycles, and we always use
|
||||
* the x16 and x4 settings, so stop-state-timeout =
|
||||
* fclk-cycle * 16 * 4 * counter.
|
||||
*
|
||||
* Stop-state-timeout must be more than 100us as per CSI2 spec, so we
|
||||
* calculate a timeout that's 100us (rounding up).
|
||||
*/
|
||||
sscounter = DIV_ROUND_UP(clk_get_rate(phy->cal->fclk), 10000 * 16 * 4);
|
||||
|
||||
val = reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance));
|
||||
set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
|
||||
set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
|
||||
set_field(&val, sscounter, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);
|
||||
reg_write(phy->cal, CAL_CSI2_TIMING(phy->instance), val);
|
||||
phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n",
|
||||
phy->instance,
|
||||
reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
|
||||
|
||||
/* 4. Force FORCERXMODE */
|
||||
reg_write_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
|
||||
1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
|
||||
phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n",
|
||||
phy->instance,
|
||||
reg_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
|
||||
|
||||
/* E. Power up the PHY using the complex IO */
|
||||
cal_camerarx_power(phy, true);
|
||||
}
|
||||
|
||||
static void cal_camerarx_wait_reset(struct cal_camerarx *phy)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(750);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
if (reg_read_field(phy->cal,
|
||||
CAL_CSI2_COMPLEXIO_CFG(phy->instance),
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
|
||||
break;
|
||||
usleep_range(500, 5000);
|
||||
}
|
||||
|
||||
if (reg_read_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
|
||||
phy_err(phy, "Timeout waiting for Complex IO reset done\n");
|
||||
}
|
||||
|
||||
static void cal_camerarx_wait_stop_state(struct cal_camerarx *phy)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(750);
|
||||
while (time_before(jiffies, timeout)) {
|
||||
if (reg_read_field(phy->cal,
|
||||
CAL_CSI2_TIMING(phy->instance),
|
||||
CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0)
|
||||
break;
|
||||
usleep_range(500, 5000);
|
||||
}
|
||||
|
||||
if (reg_read_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
|
||||
CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0)
|
||||
phy_err(phy, "Timeout waiting for stop state\n");
|
||||
}
|
||||
|
||||
static void cal_camerarx_wait_ready(struct cal_camerarx *phy)
|
||||
{
|
||||
/* Steps
|
||||
* 2. Wait for completion of reset
|
||||
* Note if the external sensor is not sending byte clock,
|
||||
* the reset will timeout
|
||||
* 4.Force FORCERXMODE
|
||||
* G. Wait for all enabled lane to reach stop state
|
||||
* H. Disable pull down using pad control
|
||||
*/
|
||||
|
||||
/* 2. Wait for reset completion */
|
||||
cal_camerarx_wait_reset(phy);
|
||||
|
||||
/* 4. G. Wait for all enabled lane to reach stop state */
|
||||
cal_camerarx_wait_stop_state(phy);
|
||||
|
||||
phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x (Bit(31,28) should be set!)\n",
|
||||
phy->instance, reg_read(phy, CAL_CSI2_PHY_REG1));
|
||||
}
|
||||
|
||||
static void cal_camerarx_deinit(struct cal_camerarx *phy)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
cal_camerarx_power(phy, false);
|
||||
|
||||
/* Assert Comple IO Reset */
|
||||
reg_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL,
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
|
||||
|
||||
/* Wait for power down completion */
|
||||
for (i = 0; i < 10; i++) {
|
||||
if (reg_read_field(phy->cal,
|
||||
CAL_CSI2_COMPLEXIO_CFG(phy->instance),
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
|
||||
CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING)
|
||||
break;
|
||||
usleep_range(1000, 1100);
|
||||
}
|
||||
phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset (%d) %s\n",
|
||||
phy->instance,
|
||||
reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)), i,
|
||||
(i >= 10) ? "(timeout)" : "");
|
||||
|
||||
/* Disable the phy */
|
||||
cal_camerarx_disable(phy);
|
||||
}
|
||||
|
||||
static void cal_camerarx_lane_config(struct cal_camerarx *phy)
|
||||
{
|
||||
u32 val = reg_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance));
|
||||
u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;
|
||||
u32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;
|
||||
struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
|
||||
&phy->endpoint.bus.mipi_csi2;
|
||||
int lane;
|
||||
|
||||
set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);
|
||||
set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);
|
||||
for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) {
|
||||
/*
|
||||
* Every lane are one nibble apart starting with the
|
||||
* clock followed by the data lanes so shift masks by 4.
|
||||
*/
|
||||
lane_mask <<= 4;
|
||||
polarity_mask <<= 4;
|
||||
set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);
|
||||
set_field(&val, mipi_csi2->lane_polarities[lane + 1],
|
||||
polarity_mask);
|
||||
}
|
||||
|
||||
reg_write(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), val);
|
||||
phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n",
|
||||
phy->instance, val);
|
||||
}
|
||||
|
||||
static void cal_camerarx_ppi_enable(struct cal_camerarx *phy)
|
||||
{
|
||||
reg_write(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), BIT(3));
|
||||
@ -863,26 +883,6 @@ static void cal_camerarx_ppi_disable(struct cal_camerarx *phy)
|
||||
0, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
|
||||
}
|
||||
|
||||
static int cal_camerarx_get_external_info(struct cal_camerarx *phy)
|
||||
{
|
||||
struct v4l2_ctrl *ctrl;
|
||||
|
||||
if (!phy->sensor)
|
||||
return -ENODEV;
|
||||
|
||||
ctrl = v4l2_ctrl_find(phy->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
|
||||
if (!ctrl) {
|
||||
phy_err(phy, "no pixel rate control in subdev: %s\n",
|
||||
phy->sensor->name);
|
||||
return -EPIPE;
|
||||
}
|
||||
|
||||
phy->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
|
||||
phy_dbg(3, phy, "sensor Pixel Rate: %u\n", phy->external_rate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cal_camerarx_regmap_init(struct cal_dev *cal,
|
||||
struct cal_camerarx *phy)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user