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RISC-V Devicetrees for v6.6-final
A single fix for the Starfive VisionFive 2 platform so that chip select for SPI matches the vendor documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZSvaJQAKCRB4tDGHoIJi 0sg6AQDQXrn1qqG+Gnq3uRl9on9KXf8xX16vcZrkzu+V8Qo2SgD/XnT8gJ5W3NwG y1XqbQ4HXIkhU1ETcanjL2zNL59IGgA= =IneL -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmUs8s8ACgkQYKtH/8kJ UidGMxAAu6zyC7SIxY8d3hAZmR4/3XgZIxCJtb71W/YJP8gpLBzQzrcbVPEcpFr+ u1ZbjX8bHSHyPJNfEHUVadeySBJ/xs7WLE5ko+Fj07rwXGOIW/90FqOTwI9z4OJ4 D80Li//jPCYTVxLnG6q9vFcv/GR+H7S1hjwxG8KRw/VS2z+4g6fRRFKXQzc0ZwJ6 WFcfHOso2U+Es4UWe12J0VHHQ5Gxv7NwUoqmOAFZqvtNQwPxeTSQAS9XJbeFBCor xYlAiA1lbytrKVVR/m/7p9fihv3J2b4X2xsE+pTL3nnM2IGaEmFIZhfKf5b2RuhA MEEjEVrkrp5SQ6oPYW1pbUnqwjYyij/1CxzO2zO/fg1EjnFxEqlLhJOg445RHcFv /kzKwcRs998F8cw6lwL8Ir9UNQ2L2vG8yEwmzT2m3v37ZXdYECDywFfK0MBnzHHO P2hxrax6By+kKMYt9VvLy8DgXN67IQA3sVKiBcbuV3hKaLhL0js+Ig0cx3TVBq1Q YkKb3wQSX8NKVj9hctZBYYreyh3hLWnyTeD6HsA1zekYpr3rk6Xsnj7a3gPUE56D 4i0OD4uYl0euwi50gq7CooB1gLPLpfsrHccS+BTaBIn/f9GwwqEfvOVMv6zkMyfB JU1hyHNhueC3PLapz+xhYG8a5TXK7h8yYmP1qpSzF03hE6MtyIw= =Vd1q -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.6-final A single fix for the Starfive VisionFive 2 platform so that chip select for SPI matches the vendor documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: visionfive 2: correct spi's ss pin riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order riscv: dts: starfive: visionfive 2: Enable usb0 riscv: dts: starfive: fix NOR flash reserved-data partition size Link: https://lore.kernel.org/r/20231015-outmatch-tragedy-228f91d396b5@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
e084a305aa
@ -262,7 +262,7 @@
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reg = <0x100000 0x400000>;
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};
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reserved-data@600000 {
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reg = <0x600000 0x1000000>;
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reg = <0x600000 0xa00000>;
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};
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};
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};
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@ -431,7 +431,7 @@
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};
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ss-pins {
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pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
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pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
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GPOEN_ENABLE,
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GPI_SYS_SPI0_FSS)>;
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bias-disable;
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@ -440,30 +440,6 @@
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};
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};
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uart0_pins: uart0-0 {
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tx-pins {
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pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
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GPOEN_ENABLE,
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GPI_NONE)>;
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bias-disable;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pinmux = <GPIOMUX(6, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_UART0_RX)>;
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bias-disable; /* external pull-up */
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drive-strength = <2>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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tdm_pins: tdm-0 {
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tx-pins {
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pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD,
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@ -497,6 +473,30 @@
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input-enable;
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};
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};
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uart0_pins: uart0-0 {
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tx-pins {
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pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
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GPOEN_ENABLE,
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GPI_NONE)>;
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bias-disable;
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drive-strength = <12>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pinmux = <GPIOMUX(6, GPOUT_LOW,
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GPOEN_DISABLE,
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GPI_SYS_UART0_RX)>;
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bias-disable; /* external pull-up */
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drive-strength = <2>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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};
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&tdm {
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@ -513,6 +513,7 @@
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&usb0 {
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dr_mode = "peripheral";
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status = "okay";
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};
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&U74_1 {
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