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drm/etnaviv: move gpu_va() to etnaviv mmu
The GPU virtual address for the command buffers differs depending on the IOMMU version. Move the calculation of the iova into etnaviv mmu, to enable proper dispatch. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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@ -117,11 +117,6 @@ static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
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VIVS_GL_PIPE_SELECT_PIPE(pipe));
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}
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static u32 gpu_va(struct etnaviv_gpu *gpu, struct etnaviv_cmdbuf *buf)
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{
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return buf->paddr - gpu->memory_base;
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}
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static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buf, u32 off, u32 len)
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{
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@ -129,7 +124,7 @@ static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
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u32 *ptr = buf->vaddr + off;
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dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
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ptr, gpu_va(gpu, buf) + off, size - len * 4 - off);
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ptr, etnaviv_iommu_get_cmdbuf_va(gpu, buf) + off, size - len * 4 - off);
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print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
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ptr, len * 4, 0);
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@ -162,7 +157,7 @@ static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
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if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)
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buffer->user_size = 0;
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return gpu_va(gpu, buffer) + buffer->user_size;
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return etnaviv_iommu_get_cmdbuf_va(gpu, buffer) + buffer->user_size;
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}
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u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
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@ -173,7 +168,8 @@ u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
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buffer->user_size = 0;
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CMD_WAIT(buffer);
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CMD_LINK(buffer, 2, gpu_va(gpu, buffer) + buffer->user_size - 4);
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CMD_LINK(buffer, 2, etnaviv_iommu_get_cmdbuf_va(gpu, buffer) +
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buffer->user_size - 4);
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return buffer->user_size / 8;
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}
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@ -231,7 +227,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
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if (drm_debug & DRM_UT_DRIVER)
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etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
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link_target = gpu_va(gpu, cmdbuf);
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link_target = etnaviv_iommu_get_cmdbuf_va(gpu, cmdbuf);
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link_dwords = cmdbuf->size / 8;
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/*
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@ -301,7 +297,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
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if (drm_debug & DRM_UT_DRIVER)
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pr_info("stream link to 0x%08x @ 0x%08x %p\n",
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return_target, gpu_va(gpu, cmdbuf), cmdbuf->vaddr);
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return_target, etnaviv_iommu_get_cmdbuf_va(gpu, cmdbuf), cmdbuf->vaddr);
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if (drm_debug & DRM_UT_DRIVER) {
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print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
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@ -574,7 +574,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
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gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
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gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS,
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gpu->buffer->paddr - gpu->memory_base);
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etnaviv_iommu_get_cmdbuf_va(gpu, gpu->buffer));
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gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
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VIVS_FE_COMMAND_CONTROL_ENABLE |
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VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
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@ -304,6 +304,12 @@ void etnaviv_iommu_restore(struct etnaviv_gpu *gpu)
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dev_err(gpu->dev, "IOMMUv2 restore not implemented\n");
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}
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u32 etnaviv_iommu_get_cmdbuf_va(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buf)
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{
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return buf->paddr - gpu->memory_base;
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}
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size_t etnaviv_iommu_dump_size(struct etnaviv_iommu *iommu)
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{
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struct etnaviv_iommu_ops *ops;
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@ -62,6 +62,9 @@ void etnaviv_iommu_unmap_gem(struct etnaviv_iommu *mmu,
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struct etnaviv_vram_mapping *mapping);
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void etnaviv_iommu_destroy(struct etnaviv_iommu *iommu);
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u32 etnaviv_iommu_get_cmdbuf_va(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buf);
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size_t etnaviv_iommu_dump_size(struct etnaviv_iommu *iommu);
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void etnaviv_iommu_dump(struct etnaviv_iommu *iommu, void *buf);
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