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Merge branch 'dsa-mv88e6xxx-ops-cosmetics'
Vivien Didelot says: ==================== net: dsa: mv88e6xxx: ops cosmetics This patchset brings no functional changes. It is a first step in a bigger cosmetics change to the driver. It simplifies print messages and polishes data types and chip operations. The next patchs will only prefix and document the port registers macros. Changes in v2: - KISS and simply use dev_* since chip->ds may not be initialized - add reviewers tags ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
e073782a41
@ -489,8 +489,7 @@ static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
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err = 0;
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restore_link:
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if (chip->info->ops->port_set_link(chip, port, link))
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netdev_err(chip->ds->ports[port].netdev,
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"failed to restore MAC's link\n");
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dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
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return err;
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}
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@ -514,7 +513,7 @@ static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
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mutex_unlock(&chip->reg_lock);
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if (err && err != -EOPNOTSUPP)
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netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
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dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
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}
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static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
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@ -916,32 +915,14 @@ static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
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u8 state)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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int stp_state;
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int err;
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switch (state) {
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case BR_STATE_DISABLED:
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stp_state = PORT_CONTROL_STATE_DISABLED;
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break;
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case BR_STATE_BLOCKING:
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case BR_STATE_LISTENING:
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stp_state = PORT_CONTROL_STATE_BLOCKING;
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break;
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case BR_STATE_LEARNING:
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stp_state = PORT_CONTROL_STATE_LEARNING;
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break;
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case BR_STATE_FORWARDING:
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default:
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stp_state = PORT_CONTROL_STATE_FORWARDING;
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break;
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}
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mutex_lock(&chip->reg_lock);
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err = mv88e6xxx_port_set_state(chip, port, stp_state);
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err = mv88e6xxx_port_set_state(chip, port, state);
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mutex_unlock(&chip->reg_lock);
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if (err)
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netdev_err(ds->ports[port].netdev, "failed to update state\n");
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dev_err(ds->dev, "p%d: failed to update state\n", port);
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}
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static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
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@ -1009,7 +990,7 @@ static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
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mutex_unlock(&chip->reg_lock);
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if (err)
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netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
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dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
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}
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static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
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@ -1214,10 +1195,9 @@ static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
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if (!ds->ports[i].bridge_dev)
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continue;
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netdev_warn(ds->ports[port].netdev,
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"hardware VLAN %d already used by %s\n",
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vlan.vid,
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netdev_name(ds->ports[i].bridge_dev));
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dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n",
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port, vlan.vid,
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netdev_name(ds->ports[i].bridge_dev));
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err = -EOPNOTSUPP;
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goto unlock;
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}
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@ -1311,13 +1291,12 @@ static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
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for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
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if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
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netdev_err(ds->ports[port].netdev,
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"failed to add VLAN %d%c\n",
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vid, untagged ? 'u' : 't');
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dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
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vid, untagged ? 'u' : 't');
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if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
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netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
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vlan->vid_end);
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dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
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vlan->vid_end);
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mutex_unlock(&chip->reg_lock);
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}
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@ -1451,7 +1430,8 @@ static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
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mutex_lock(&chip->reg_lock);
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if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
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GLOBAL_ATU_DATA_STATE_UC_STATIC))
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netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
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dev_err(ds->dev, "p%d: failed to load unicast MAC address\n",
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port);
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mutex_unlock(&chip->reg_lock);
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}
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@ -1696,8 +1676,7 @@ static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
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/* Set all ports to the Disabled state */
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for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
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err = mv88e6xxx_port_set_state(chip, i,
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PORT_CONTROL_STATE_DISABLED);
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err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
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if (err)
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return err;
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}
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@ -1724,8 +1703,8 @@ static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
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}
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static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
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enum mv88e6xxx_frame_mode frame, u16 egress,
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u16 etype)
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enum mv88e6xxx_frame_mode frame,
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enum mv88e6xxx_egress_mode egress, u16 etype)
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{
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int err;
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@ -1749,14 +1728,14 @@ static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
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static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
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{
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return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
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PORT_CONTROL_EGRESS_UNMODIFIED,
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MV88E6XXX_EGRESS_MODE_UNMODIFIED,
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PORT_ETH_TYPE_DEFAULT);
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}
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static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
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{
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return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
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PORT_CONTROL_EGRESS_UNMODIFIED,
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MV88E6XXX_EGRESS_MODE_UNMODIFIED,
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PORT_ETH_TYPE_DEFAULT);
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}
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@ -1764,7 +1743,8 @@ static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
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{
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return mv88e6xxx_set_port_mode(chip, port,
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MV88E6XXX_FRAME_MODE_ETHERTYPE,
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PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
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MV88E6XXX_EGRESS_MODE_ETHERTYPE,
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ETH_P_EDSA);
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}
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static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
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@ -1896,8 +1876,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
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if (err)
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return err;
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if (chip->info->ops->port_jumbo_config) {
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err = chip->info->ops->port_jumbo_config(chip, port);
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if (chip->info->ops->port_set_jumbo_size) {
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err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
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if (err)
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return err;
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}
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@ -1921,8 +1901,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
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if (err)
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return err;
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if (chip->info->ops->port_pause_config) {
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err = chip->info->ops->port_pause_config(chip, port);
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if (chip->info->ops->port_pause_limit) {
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err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
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if (err)
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return err;
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}
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@ -2035,14 +2015,14 @@ static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
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u32 upstream_port = dsa_upstream_port(ds);
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int err;
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if (chip->info->ops->g1_set_cpu_port) {
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err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
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if (chip->info->ops->set_cpu_port) {
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err = chip->info->ops->set_cpu_port(chip, upstream_port);
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if (err)
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return err;
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}
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if (chip->info->ops->g1_set_egress_port) {
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err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
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if (chip->info->ops->set_egress_port) {
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err = chip->info->ops->set_egress_port(chip, upstream_port);
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if (err)
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return err;
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}
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@ -2382,15 +2362,15 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
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.port_set_egress_floods = mv88e6352_port_set_egress_floods,
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.port_set_ether_type = mv88e6351_port_set_ether_type,
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.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
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.port_pause_config = mv88e6097_port_pause_config,
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.port_pause_limit = mv88e6097_port_pause_limit,
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.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
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.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
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.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
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.stats_get_sset_count = mv88e6095_stats_get_sset_count,
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.stats_get_strings = mv88e6095_stats_get_strings,
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.stats_get_stats = mv88e6095_stats_get_stats,
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.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6095_g1_set_egress_port,
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.set_cpu_port = mv88e6095_g1_set_cpu_port,
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.set_egress_port = mv88e6095_g1_set_egress_port,
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.watchdog_ops = &mv88e6097_watchdog_ops,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.ppu_enable = mv88e6185_g1_ppu_enable,
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@ -2435,17 +2415,17 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
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.port_set_frame_mode = mv88e6351_port_set_frame_mode,
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.port_set_egress_floods = mv88e6352_port_set_egress_floods,
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.port_set_ether_type = mv88e6351_port_set_ether_type,
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.port_jumbo_config = mv88e6165_port_jumbo_config,
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.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
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.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
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.port_pause_config = mv88e6097_port_pause_config,
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.port_pause_limit = mv88e6097_port_pause_limit,
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.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
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.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
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.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
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.stats_get_sset_count = mv88e6095_stats_get_sset_count,
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.stats_get_strings = mv88e6095_stats_get_strings,
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.stats_get_stats = mv88e6095_stats_get_stats,
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.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6095_g1_set_egress_port,
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.set_cpu_port = mv88e6095_g1_set_cpu_port,
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.set_egress_port = mv88e6095_g1_set_egress_port,
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.watchdog_ops = &mv88e6097_watchdog_ops,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.reset = mv88e6352_g1_reset,
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@ -2469,8 +2449,8 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
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.stats_get_sset_count = mv88e6095_stats_get_sset_count,
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.stats_get_strings = mv88e6095_stats_get_strings,
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.stats_get_stats = mv88e6095_stats_get_stats,
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.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6095_g1_set_egress_port,
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.set_cpu_port = mv88e6095_g1_set_cpu_port,
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.set_egress_port = mv88e6095_g1_set_egress_port,
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.watchdog_ops = &mv88e6097_watchdog_ops,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.reset = mv88e6352_g1_reset,
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@ -2491,15 +2471,15 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
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.port_set_egress_floods = mv88e6185_port_set_egress_floods,
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.port_set_ether_type = mv88e6351_port_set_ether_type,
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.port_set_upstream_port = mv88e6095_port_set_upstream_port,
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.port_jumbo_config = mv88e6165_port_jumbo_config,
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.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
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.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
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.port_pause_config = mv88e6097_port_pause_config,
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.port_pause_limit = mv88e6097_port_pause_limit,
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.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
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.stats_get_sset_count = mv88e6095_stats_get_sset_count,
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.stats_get_strings = mv88e6095_stats_get_strings,
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.stats_get_stats = mv88e6095_stats_get_stats,
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.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6095_g1_set_egress_port,
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.set_cpu_port = mv88e6095_g1_set_cpu_port,
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.set_egress_port = mv88e6095_g1_set_egress_port,
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.watchdog_ops = &mv88e6097_watchdog_ops,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.ppu_enable = mv88e6185_g1_ppu_enable,
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@ -2524,17 +2504,17 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
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.port_set_frame_mode = mv88e6351_port_set_frame_mode,
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.port_set_egress_floods = mv88e6352_port_set_egress_floods,
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.port_set_ether_type = mv88e6351_port_set_ether_type,
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.port_jumbo_config = mv88e6165_port_jumbo_config,
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.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
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.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
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.port_pause_config = mv88e6097_port_pause_config,
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.port_pause_limit = mv88e6097_port_pause_limit,
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.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
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.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
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.stats_snapshot = mv88e6390_g1_stats_snapshot,
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.stats_get_sset_count = mv88e6320_stats_get_sset_count,
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.stats_get_strings = mv88e6320_stats_get_strings,
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.stats_get_stats = mv88e6390_stats_get_stats,
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.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6390_g1_set_egress_port,
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.set_cpu_port = mv88e6390_g1_set_cpu_port,
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.set_egress_port = mv88e6390_g1_set_egress_port,
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.watchdog_ops = &mv88e6390_watchdog_ops,
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.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
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.reset = mv88e6352_g1_reset,
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@ -2554,17 +2534,17 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
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.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
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.port_set_egress_floods = mv88e6352_port_set_egress_floods,
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.port_set_ether_type = mv88e6351_port_set_ether_type,
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.port_jumbo_config = mv88e6165_port_jumbo_config,
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.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
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.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
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.port_pause_config = mv88e6097_port_pause_config,
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.port_pause_limit = mv88e6097_port_pause_limit,
|
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.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
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.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
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.stats_snapshot = mv88e6320_g1_stats_snapshot,
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.stats_get_sset_count = mv88e6095_stats_get_sset_count,
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.stats_get_strings = mv88e6095_stats_get_strings,
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.stats_get_stats = mv88e6095_stats_get_stats,
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.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
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.g1_set_egress_port = mv88e6095_g1_set_egress_port,
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.set_cpu_port = mv88e6095_g1_set_cpu_port,
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.set_egress_port = mv88e6095_g1_set_egress_port,
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.watchdog_ops = &mv88e6097_watchdog_ops,
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.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
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.reset = mv88e6352_g1_reset,
|
||||
@ -2586,8 +2566,8 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2608,17 +2588,17 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2641,17 +2621,17 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2673,17 +2653,17 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2706,17 +2686,17 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2741,8 +2721,8 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.ppu_enable = mv88e6185_g1_ppu_enable,
|
||||
@ -2767,7 +2747,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_pause_config = mv88e6390_port_pause_config,
|
||||
.port_pause_limit = mv88e6390_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6390_g1_stats_snapshot,
|
||||
@ -2775,8 +2755,8 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6390_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6390_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2800,7 +2780,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_pause_config = mv88e6390_port_pause_config,
|
||||
.port_pause_limit = mv88e6390_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6390_g1_stats_snapshot,
|
||||
@ -2808,8 +2788,8 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6390_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6390_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2833,7 +2813,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_pause_config = mv88e6390_port_pause_config,
|
||||
.port_pause_limit = mv88e6390_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6390_g1_stats_snapshot,
|
||||
@ -2841,8 +2821,8 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6390_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6390_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2866,17 +2846,17 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2900,7 +2880,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_pause_config = mv88e6390_port_pause_config,
|
||||
.port_pause_limit = mv88e6390_port_pause_limit,
|
||||
.port_set_cmode = mv88e6390x_port_set_cmode,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
@ -2909,8 +2889,8 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6390_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6390_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -2933,17 +2913,17 @@ static const struct mv88e6xxx_ops mv88e6320_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6320_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
.vtu_getnext = mv88e6185_g1_vtu_getnext,
|
||||
@ -2964,17 +2944,17 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6320_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
.vtu_getnext = mv88e6185_g1_vtu_getnext,
|
||||
.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
|
||||
@ -2995,17 +2975,17 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6390_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6390_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6390_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -3026,17 +3006,17 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -3057,17 +3037,17 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -3090,17 +3070,17 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6097_port_pause_config,
|
||||
.port_pause_limit = mv88e6097_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6320_g1_stats_snapshot,
|
||||
.stats_get_sset_count = mv88e6095_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6095_stats_get_strings,
|
||||
.stats_get_stats = mv88e6095_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6095_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6095_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6097_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -3124,9 +3104,9 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6390_port_pause_config,
|
||||
.port_pause_limit = mv88e6390_port_pause_limit,
|
||||
.port_set_cmode = mv88e6390x_port_set_cmode,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
@ -3135,8 +3115,8 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6390_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6390_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -3160,9 +3140,9 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
|
||||
.port_set_frame_mode = mv88e6351_port_set_frame_mode,
|
||||
.port_set_egress_floods = mv88e6352_port_set_egress_floods,
|
||||
.port_set_ether_type = mv88e6351_port_set_ether_type,
|
||||
.port_jumbo_config = mv88e6165_port_jumbo_config,
|
||||
.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
|
||||
.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
|
||||
.port_pause_config = mv88e6390_port_pause_config,
|
||||
.port_pause_limit = mv88e6390_port_pause_limit,
|
||||
.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
|
||||
.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
|
||||
.stats_snapshot = mv88e6390_g1_stats_snapshot,
|
||||
@ -3170,8 +3150,8 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
|
||||
.stats_get_sset_count = mv88e6320_stats_get_sset_count,
|
||||
.stats_get_strings = mv88e6320_stats_get_strings,
|
||||
.stats_get_stats = mv88e6390_stats_get_stats,
|
||||
.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.g1_set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.set_cpu_port = mv88e6390_g1_set_cpu_port,
|
||||
.set_egress_port = mv88e6390_g1_set_egress_port,
|
||||
.watchdog_ops = &mv88e6390_watchdog_ops,
|
||||
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
|
||||
.reset = mv88e6352_g1_reset,
|
||||
@ -3793,7 +3773,8 @@ static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
|
||||
mutex_lock(&chip->reg_lock);
|
||||
if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
|
||||
GLOBAL_ATU_DATA_STATE_MC_STATIC))
|
||||
netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
|
||||
dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
|
||||
port);
|
||||
mutex_unlock(&chip->reg_lock);
|
||||
}
|
||||
|
||||
|
||||
@ -39,6 +39,13 @@
|
||||
#define MV88E6XXX_MAX_PVT_SWITCHES 32
|
||||
#define MV88E6XXX_MAX_PVT_PORTS 16
|
||||
|
||||
enum mv88e6xxx_egress_mode {
|
||||
MV88E6XXX_EGRESS_MODE_UNMODIFIED,
|
||||
MV88E6XXX_EGRESS_MODE_UNTAGGED,
|
||||
MV88E6XXX_EGRESS_MODE_TAGGED,
|
||||
MV88E6XXX_EGRESS_MODE_ETHERTYPE,
|
||||
};
|
||||
|
||||
enum mv88e6xxx_frame_mode {
|
||||
MV88E6XXX_FRAME_MODE_NORMAL,
|
||||
MV88E6XXX_FRAME_MODE_DSA,
|
||||
@ -415,10 +422,12 @@ struct mv88e6xxx_ops {
|
||||
bool unicast, bool multicast);
|
||||
int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
|
||||
u16 etype);
|
||||
int (*port_jumbo_config)(struct mv88e6xxx_chip *chip, int port);
|
||||
int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
|
||||
size_t size);
|
||||
|
||||
int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
|
||||
int (*port_pause_config)(struct mv88e6xxx_chip *chip, int port);
|
||||
int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
|
||||
u8 out);
|
||||
int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
|
||||
int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
|
||||
|
||||
@ -449,8 +458,8 @@ struct mv88e6xxx_ops {
|
||||
void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
|
||||
void (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
|
||||
uint64_t *data);
|
||||
int (*g1_set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
|
||||
int (*g1_set_egress_port)(struct mv88e6xxx_chip *chip, int port);
|
||||
int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
|
||||
int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
|
||||
const struct mv88e6xxx_irq_ops *watchdog_ops;
|
||||
|
||||
/* Can be either in g1 or g2, so don't use a prefix */
|
||||
|
||||
@ -62,7 +62,7 @@ int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, int reg, u16 val)
|
||||
|
||||
static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
|
||||
{
|
||||
return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
|
||||
return mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page);
|
||||
}
|
||||
|
||||
static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
|
||||
@ -72,7 +72,8 @@ static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
|
||||
/* Restore PHY page Copper 0x0 for access via the registered
|
||||
* MDIO bus
|
||||
*/
|
||||
err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
|
||||
err = mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE,
|
||||
MV88E6XXX_PHY_PAGE_COPPER);
|
||||
if (unlikely(err)) {
|
||||
dev_err(chip->dev,
|
||||
"failed to restore PHY %d page Copper (%d)\n",
|
||||
@ -86,7 +87,7 @@ int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
|
||||
int err;
|
||||
|
||||
/* There is no paging for registers 22 */
|
||||
if (reg == PHY_PAGE)
|
||||
if (reg == MV88E6XXX_PHY_PAGE)
|
||||
return -EINVAL;
|
||||
|
||||
err = mv88e6xxx_phy_page_get(chip, phy, page);
|
||||
@ -104,12 +105,12 @@ int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
|
||||
int err;
|
||||
|
||||
/* There is no paging for registers 22 */
|
||||
if (reg == PHY_PAGE)
|
||||
if (reg == MV88E6XXX_PHY_PAGE)
|
||||
return -EINVAL;
|
||||
|
||||
err = mv88e6xxx_phy_page_get(chip, phy, page);
|
||||
if (!err) {
|
||||
err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
|
||||
err = mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page);
|
||||
mv88e6xxx_phy_page_put(chip, phy);
|
||||
}
|
||||
|
||||
|
||||
@ -14,8 +14,8 @@
|
||||
#ifndef _MV88E6XXX_PHY_H
|
||||
#define _MV88E6XXX_PHY_H
|
||||
|
||||
#define PHY_PAGE 0x16
|
||||
#define PHY_PAGE_COPPER 0x00
|
||||
#define MV88E6XXX_PHY_PAGE 0x16
|
||||
#define MV88E6XXX_PHY_PAGE_COPPER 0x00
|
||||
|
||||
/* PHY Registers accesses implementations */
|
||||
int mv88e6165_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/if_bridge.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include "chip.h"
|
||||
@ -76,9 +77,9 @@ static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "delay RXCLK %s, TXCLK %s\n",
|
||||
reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
|
||||
reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
|
||||
dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
|
||||
reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
|
||||
reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -130,9 +131,9 @@ int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "%s link %s\n",
|
||||
reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
|
||||
reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
|
||||
dev_dbg(chip->dev, "p%d: %s link %s\n", port,
|
||||
reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
|
||||
reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -166,9 +167,9 @@ int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "%s %s duplex\n",
|
||||
reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
|
||||
reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
|
||||
dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
|
||||
reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
|
||||
reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -226,10 +227,9 @@ static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
|
||||
return err;
|
||||
|
||||
if (speed)
|
||||
netdev_dbg(chip->ds->ports[port].netdev,
|
||||
"Speed set to %d Mbps\n", speed);
|
||||
dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
|
||||
else
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "Speed unforced\n");
|
||||
dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -376,22 +376,24 @@ int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
|
||||
* the remote end or the period of time that this port can pause the
|
||||
* remote end.
|
||||
*/
|
||||
int mv88e6097_port_pause_config(struct mv88e6xxx_chip *chip, int port)
|
||||
int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
|
||||
u8 out)
|
||||
{
|
||||
return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
|
||||
return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, out << 8 | in);
|
||||
}
|
||||
|
||||
int mv88e6390_port_pause_config(struct mv88e6xxx_chip *chip, int port)
|
||||
int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
|
||||
u8 out)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
|
||||
PORT_FLOW_CTRL_LIMIT_IN | 0);
|
||||
PORT_FLOW_CTRL_LIMIT_IN | in);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
|
||||
PORT_FLOW_CTRL_LIMIT_OUT | 0);
|
||||
PORT_FLOW_CTRL_LIMIT_OUT | out);
|
||||
}
|
||||
|
||||
/* Offset 0x04: Port Control Register */
|
||||
@ -413,20 +415,39 @@ int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
|
||||
return err;
|
||||
|
||||
reg &= ~PORT_CONTROL_STATE_MASK;
|
||||
|
||||
switch (state) {
|
||||
case BR_STATE_DISABLED:
|
||||
state = PORT_CONTROL_STATE_DISABLED;
|
||||
break;
|
||||
case BR_STATE_BLOCKING:
|
||||
case BR_STATE_LISTENING:
|
||||
state = PORT_CONTROL_STATE_BLOCKING;
|
||||
break;
|
||||
case BR_STATE_LEARNING:
|
||||
state = PORT_CONTROL_STATE_LEARNING;
|
||||
break;
|
||||
case BR_STATE_FORWARDING:
|
||||
state = PORT_CONTROL_STATE_FORWARDING;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg |= state;
|
||||
|
||||
err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "PortState set to %s\n",
|
||||
mv88e6xxx_port_state_names[state]);
|
||||
dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
|
||||
mv88e6xxx_port_state_names[state]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
|
||||
u16 mode)
|
||||
enum mv88e6xxx_egress_mode mode)
|
||||
{
|
||||
int err;
|
||||
u16 reg;
|
||||
@ -436,7 +457,23 @@ int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
|
||||
return err;
|
||||
|
||||
reg &= ~PORT_CONTROL_EGRESS_MASK;
|
||||
reg |= mode;
|
||||
|
||||
switch (mode) {
|
||||
case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
|
||||
reg |= PORT_CONTROL_EGRESS_UNMODIFIED;
|
||||
break;
|
||||
case MV88E6XXX_EGRESS_MODE_UNTAGGED:
|
||||
reg |= PORT_CONTROL_EGRESS_UNTAGGED;
|
||||
break;
|
||||
case MV88E6XXX_EGRESS_MODE_TAGGED:
|
||||
reg |= PORT_CONTROL_EGRESS_TAGGED;
|
||||
break;
|
||||
case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
|
||||
reg |= PORT_CONTROL_EGRESS_ADD_TAG;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
|
||||
}
|
||||
@ -580,8 +617,7 @@ int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "VLANTable set to %.3x\n",
|
||||
map);
|
||||
dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -646,7 +682,7 @@ int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
|
||||
return err;
|
||||
}
|
||||
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "FID set to %u\n", fid);
|
||||
dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -683,8 +719,7 @@ int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "DefaultVID set to %u\n",
|
||||
pvid);
|
||||
dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -761,8 +796,8 @@ int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
netdev_dbg(chip->ds->ports[port].netdev, "802.1QMode set to %s\n",
|
||||
mv88e6xxx_port_8021q_mode_names[mode]);
|
||||
dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
|
||||
mv88e6xxx_port_8021q_mode_names[mode]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -781,7 +816,8 @@ int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
|
||||
return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
|
||||
}
|
||||
|
||||
int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
|
||||
int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
|
||||
size_t size)
|
||||
{
|
||||
u16 reg;
|
||||
int err;
|
||||
@ -790,7 +826,16 @@ int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
reg |= PORT_CONTROL_2_JUMBO_10240;
|
||||
reg &= ~PORT_CONTROL_2_JUMBO_MASK;
|
||||
|
||||
if (size <= 1522)
|
||||
reg |= PORT_CONTROL_2_JUMBO_1522;
|
||||
else if (size <= 2048)
|
||||
reg |= PORT_CONTROL_2_JUMBO_2048;
|
||||
else if (size <= 10240)
|
||||
reg |= PORT_CONTROL_2_JUMBO_10240;
|
||||
else
|
||||
return -ERANGE;
|
||||
|
||||
return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
|
||||
}
|
||||
|
||||
@ -133,6 +133,7 @@
|
||||
#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
|
||||
#define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
|
||||
#define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
|
||||
#define PORT_CONTROL_2_JUMBO_MASK (0x03 << 12)
|
||||
#define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
|
||||
#define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
|
||||
#define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
|
||||
@ -212,7 +213,7 @@ int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
|
||||
int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
|
||||
int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
|
||||
int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
|
||||
u16 mode);
|
||||
enum mv88e6xxx_egress_mode mode);
|
||||
int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
|
||||
enum mv88e6xxx_frame_mode mode);
|
||||
int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
|
||||
@ -225,11 +226,14 @@ int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
|
||||
u16 etype);
|
||||
int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
|
||||
bool message_port);
|
||||
int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port);
|
||||
int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
|
||||
size_t size);
|
||||
int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
|
||||
int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
|
||||
int mv88e6097_port_pause_config(struct mv88e6xxx_chip *chip, int port);
|
||||
int mv88e6390_port_pause_config(struct mv88e6xxx_chip *chip, int port);
|
||||
int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
|
||||
u8 out);
|
||||
int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
|
||||
u8 out);
|
||||
int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
|
||||
phy_interface_t mode);
|
||||
int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user