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https://mirrors.bfsu.edu.cn/git/linux.git
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i.MX SoC changes for 3.14:
- Add the initial i.MX50 SoC support - Support device tree boot for i.MX35 - Move imx5 clock driver to use macros for clock ID - Some random updates and non-critical fixes on clock drivers - A few defconfig updates and minor cleanups -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJSwiPBAAoJEFBXWFqHsHzO3/AIALlP6m/7taIQW5wO4o4aqdwk GsN7IdsfWH/biG9VyxgpIoJKUqaOJckGA0eyLSeEG7p78xlf0n7cVPUNwzz9z1Vc zxLSaVNznVOa4fTIsbMK9U+gUP931hjXskxD3tH98MUFqlM0JLQYoofr/lXG7Esf N2p8B9aUND3WSxDa+d+CsW0B3FBj1piOQDMDgrdc3p7kjcAJs31KaKfUa06o7gzM a81OaD9Vk0ONf44wh1LGlg0hDRsatQOa4tUTimeV14CnESKqsKxT4qAJ6pZLdfOt KyRqSk4f4mkpimv4bGdhXTIsIko1CD9wg7G9fsSaolh3OEP0yyNf1savR1fmwCI= =Hhbl -----END PGP SIGNATURE----- Merge tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc From Shawn Guo: i.MX SoC changes for 3.14: - Add the initial i.MX50 SoC support - Support device tree boot for i.MX35 - Move imx5 clock driver to use macros for clock ID - Some random updates and non-critical fixes on clock drivers - A few defconfig updates and minor cleanups * tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6: (37 commits) ARM: imx: improve the comment of CCM lpm SW workaround ARM: imx: improve status check of clock gate ARM: imx: add necessary interface for pfd ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100 ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support ARM: imx: Add cpu frequency scaling support ARM i.MX35: Add devicetree support. ARM: imx: update imx_v6_v7_defconfig ARM: imx6sl: Add missing spba clock to clock tree ARM: imx6sl: Add missing pll4_audio_div to the clock tree ARM: imx6: Derive spdif clock from pll3_pfd3_454m ARM: imx: use __initconst for const init definition ARM i.MX5: fix obvious typo in ldb_di0_gate clk definition ARM i.MX5: set CAN peripheral clock to 24 MHz parent ARM: imx: pllv1: Fix PLL calculation for i.MX27 ARM i.MX5: fix "shift" value for lp_apm_sel on i.MX50 and i.MX53 ARM: imx: imx53: Add SATA PHY clock ARM: imx_v6_v7_defconfig: Enable STMPE touchscreen ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_END ARM: imx: select PINCTRL at sub-architecure level ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
e05f9ac42c
113
Documentation/devicetree/bindings/clock/imx35-clock.txt
Normal file
113
Documentation/devicetree/bindings/clock/imx35-clock.txt
Normal file
@ -0,0 +1,113 @@
|
||||
* Clock bindings for Freescale i.MX35
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||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx35-ccm"
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||||
- reg: Address and length of the register set
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||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX35
|
||||
clocks and IDs.
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||||
|
||||
Clock ID
|
||||
---------------------------
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||||
ckih 0
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||||
mpll 1
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||||
ppll 2
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||||
mpll_075 3
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||||
arm 4
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||||
hsp 5
|
||||
hsp_div 6
|
||||
hsp_sel 7
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||||
ahb 8
|
||||
ipg 9
|
||||
arm_per_div 10
|
||||
ahb_per_div 11
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||||
ipg_per 12
|
||||
uart_sel 13
|
||||
uart_div 14
|
||||
esdhc_sel 15
|
||||
esdhc1_div 16
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||||
esdhc2_div 17
|
||||
esdhc3_div 18
|
||||
spdif_sel 19
|
||||
spdif_div_pre 20
|
||||
spdif_div_post 21
|
||||
ssi_sel 22
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||||
ssi1_div_pre 23
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||||
ssi1_div_post 24
|
||||
ssi2_div_pre 25
|
||||
ssi2_div_post 26
|
||||
usb_sel 27
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||||
usb_div 28
|
||||
nfc_div 29
|
||||
asrc_gate 30
|
||||
pata_gate 31
|
||||
audmux_gate 32
|
||||
can1_gate 33
|
||||
can2_gate 34
|
||||
cspi1_gate 35
|
||||
cspi2_gate 36
|
||||
ect_gate 37
|
||||
edio_gate 38
|
||||
emi_gate 39
|
||||
epit1_gate 40
|
||||
epit2_gate 41
|
||||
esai_gate 42
|
||||
esdhc1_gate 43
|
||||
esdhc2_gate 44
|
||||
esdhc3_gate 45
|
||||
fec_gate 46
|
||||
gpio1_gate 47
|
||||
gpio2_gate 48
|
||||
gpio3_gate 49
|
||||
gpt_gate 50
|
||||
i2c1_gate 51
|
||||
i2c2_gate 52
|
||||
i2c3_gate 53
|
||||
iomuxc_gate 54
|
||||
ipu_gate 55
|
||||
kpp_gate 56
|
||||
mlb_gate 57
|
||||
mshc_gate 58
|
||||
owire_gate 59
|
||||
pwm_gate 60
|
||||
rngc_gate 61
|
||||
rtc_gate 62
|
||||
rtic_gate 63
|
||||
scc_gate 64
|
||||
sdma_gate 65
|
||||
spba_gate 66
|
||||
spdif_gate 67
|
||||
ssi1_gate 68
|
||||
ssi2_gate 69
|
||||
uart1_gate 70
|
||||
uart2_gate 71
|
||||
uart3_gate 72
|
||||
usbotg_gate 73
|
||||
wdog_gate 74
|
||||
max_gate 75
|
||||
admux_gate 76
|
||||
csi_gate 77
|
||||
csi_div 78
|
||||
csi_sel 79
|
||||
iim_gate 80
|
||||
gpu2d_gate 81
|
||||
|
||||
Examples:
|
||||
|
||||
clks: ccm@53f80000 {
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||||
compatible = "fsl,imx35-ccm";
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||||
reg = <0x53f80000 0x4000>;
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||||
interrupts = <31>;
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||||
#clock-cells = <1>;
|
||||
};
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||||
|
||||
esdhc1: esdhc@53fb4000 {
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||||
compatible = "fsl,imx35-esdhc";
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||||
reg = <0x53fb4000 0x4000>;
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||||
interrupts = <7>;
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||||
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
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clock-names = "ipg", "ahb", "per";
|
||||
};
|
||||
@ -7,197 +7,8 @@ Required properties:
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX5
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
ckil 1
|
||||
osc 2
|
||||
ckih1 3
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||||
ckih2 4
|
||||
ahb 5
|
||||
ipg 6
|
||||
axi_a 7
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||||
axi_b 8
|
||||
uart_pred 9
|
||||
uart_root 10
|
||||
esdhc_a_pred 11
|
||||
esdhc_b_pred 12
|
||||
esdhc_c_s 13
|
||||
esdhc_d_s 14
|
||||
emi_sel 15
|
||||
emi_slow_podf 16
|
||||
nfc_podf 17
|
||||
ecspi_pred 18
|
||||
ecspi_podf 19
|
||||
usboh3_pred 20
|
||||
usboh3_podf 21
|
||||
usb_phy_pred 22
|
||||
usb_phy_podf 23
|
||||
cpu_podf 24
|
||||
di_pred 25
|
||||
tve_s 27
|
||||
uart1_ipg_gate 28
|
||||
uart1_per_gate 29
|
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uart2_ipg_gate 30
|
||||
uart2_per_gate 31
|
||||
uart3_ipg_gate 32
|
||||
uart3_per_gate 33
|
||||
i2c1_gate 34
|
||||
i2c2_gate 35
|
||||
gpt_ipg_gate 36
|
||||
pwm1_ipg_gate 37
|
||||
pwm1_hf_gate 38
|
||||
pwm2_ipg_gate 39
|
||||
pwm2_hf_gate 40
|
||||
gpt_hf_gate 41
|
||||
fec_gate 42
|
||||
usboh3_per_gate 43
|
||||
esdhc1_ipg_gate 44
|
||||
esdhc2_ipg_gate 45
|
||||
esdhc3_ipg_gate 46
|
||||
esdhc4_ipg_gate 47
|
||||
ssi1_ipg_gate 48
|
||||
ssi2_ipg_gate 49
|
||||
ssi3_ipg_gate 50
|
||||
ecspi1_ipg_gate 51
|
||||
ecspi1_per_gate 52
|
||||
ecspi2_ipg_gate 53
|
||||
ecspi2_per_gate 54
|
||||
cspi_ipg_gate 55
|
||||
sdma_gate 56
|
||||
emi_slow_gate 57
|
||||
ipu_s 58
|
||||
ipu_gate 59
|
||||
nfc_gate 60
|
||||
ipu_di1_gate 61
|
||||
vpu_s 62
|
||||
vpu_gate 63
|
||||
vpu_reference_gate 64
|
||||
uart4_ipg_gate 65
|
||||
uart4_per_gate 66
|
||||
uart5_ipg_gate 67
|
||||
uart5_per_gate 68
|
||||
tve_gate 69
|
||||
tve_pred 70
|
||||
esdhc1_per_gate 71
|
||||
esdhc2_per_gate 72
|
||||
esdhc3_per_gate 73
|
||||
esdhc4_per_gate 74
|
||||
usb_phy_gate 75
|
||||
hsi2c_gate 76
|
||||
mipi_hsc1_gate 77
|
||||
mipi_hsc2_gate 78
|
||||
mipi_esc_gate 79
|
||||
mipi_hsp_gate 80
|
||||
ldb_di1_div_3_5 81
|
||||
ldb_di1_div 82
|
||||
ldb_di0_div_3_5 83
|
||||
ldb_di0_div 84
|
||||
ldb_di1_gate 85
|
||||
can2_serial_gate 86
|
||||
can2_ipg_gate 87
|
||||
i2c3_gate 88
|
||||
lp_apm 89
|
||||
periph_apm 90
|
||||
main_bus 91
|
||||
ahb_max 92
|
||||
aips_tz1 93
|
||||
aips_tz2 94
|
||||
tmax1 95
|
||||
tmax2 96
|
||||
tmax3 97
|
||||
spba 98
|
||||
uart_sel 99
|
||||
esdhc_a_sel 100
|
||||
esdhc_b_sel 101
|
||||
esdhc_a_podf 102
|
||||
esdhc_b_podf 103
|
||||
ecspi_sel 104
|
||||
usboh3_sel 105
|
||||
usb_phy_sel 106
|
||||
iim_gate 107
|
||||
usboh3_gate 108
|
||||
emi_fast_gate 109
|
||||
ipu_di0_gate 110
|
||||
gpc_dvfs 111
|
||||
pll1_sw 112
|
||||
pll2_sw 113
|
||||
pll3_sw 114
|
||||
ipu_di0_sel 115
|
||||
ipu_di1_sel 116
|
||||
tve_ext_sel 117
|
||||
mx51_mipi 118
|
||||
pll4_sw 119
|
||||
ldb_di1_sel 120
|
||||
di_pll4_podf 121
|
||||
ldb_di0_sel 122
|
||||
ldb_di0_gate 123
|
||||
usb_phy1_gate 124
|
||||
usb_phy2_gate 125
|
||||
per_lp_apm 126
|
||||
per_pred1 127
|
||||
per_pred2 128
|
||||
per_podf 129
|
||||
per_root 130
|
||||
ssi_apm 131
|
||||
ssi1_root_sel 132
|
||||
ssi2_root_sel 133
|
||||
ssi3_root_sel 134
|
||||
ssi_ext1_sel 135
|
||||
ssi_ext2_sel 136
|
||||
ssi_ext1_com_sel 137
|
||||
ssi_ext2_com_sel 138
|
||||
ssi1_root_pred 139
|
||||
ssi1_root_podf 140
|
||||
ssi2_root_pred 141
|
||||
ssi2_root_podf 142
|
||||
ssi_ext1_pred 143
|
||||
ssi_ext1_podf 144
|
||||
ssi_ext2_pred 145
|
||||
ssi_ext2_podf 146
|
||||
ssi1_root_gate 147
|
||||
ssi2_root_gate 148
|
||||
ssi3_root_gate 149
|
||||
ssi_ext1_gate 150
|
||||
ssi_ext2_gate 151
|
||||
epit1_ipg_gate 152
|
||||
epit1_hf_gate 153
|
||||
epit2_ipg_gate 154
|
||||
epit2_hf_gate 155
|
||||
can_sel 156
|
||||
can1_serial_gate 157
|
||||
can1_ipg_gate 158
|
||||
owire_gate 159
|
||||
gpu3d_s 160
|
||||
gpu2d_s 161
|
||||
gpu3d_gate 162
|
||||
gpu2d_gate 163
|
||||
garb_gate 164
|
||||
cko1_sel 165
|
||||
cko1_podf 166
|
||||
cko1 167
|
||||
cko2_sel 168
|
||||
cko2_podf 169
|
||||
cko2 170
|
||||
srtc_gate 171
|
||||
pata_gate 172
|
||||
sata_gate 173
|
||||
spdif_xtal_sel 174
|
||||
spdif0_sel 175
|
||||
spdif1_sel 176
|
||||
spdif0_pred 177
|
||||
spdif0_podf 178
|
||||
spdif1_pred 179
|
||||
spdif1_podf 180
|
||||
spdif0_com_sel 181
|
||||
spdif1_com_sel 182
|
||||
spdif0_gate 183
|
||||
spdif1_gate 184
|
||||
spdif_ipg_gate 185
|
||||
ocram 186
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
|
||||
for the full list of i.MX5 clock IDs.
|
||||
|
||||
Examples (for mx53):
|
||||
|
||||
@ -212,7 +23,7 @@ can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks 158>, <&clks 157>;
|
||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -263,6 +263,13 @@ choice
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX35.
|
||||
|
||||
config DEBUG_IMX50_UART
|
||||
bool "i.MX50 Debug UART"
|
||||
depends on SOC_IMX50
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on i.MX50.
|
||||
|
||||
config DEBUG_IMX51_UART
|
||||
bool "i.MX51 Debug UART"
|
||||
depends on SOC_IMX51
|
||||
@ -905,6 +912,7 @@ config DEBUG_IMX_UART_PORT
|
||||
DEBUG_IMX21_IMX27_UART || \
|
||||
DEBUG_IMX31_UART || \
|
||||
DEBUG_IMX35_UART || \
|
||||
DEBUG_IMX50_UART || \
|
||||
DEBUG_IMX51_UART || \
|
||||
DEBUG_IMX53_UART || \
|
||||
DEBUG_IMX6Q_UART || \
|
||||
@ -939,6 +947,7 @@ config DEBUG_LL_INCLUDE
|
||||
DEBUG_IMX21_IMX27_UART || \
|
||||
DEBUG_IMX31_UART || \
|
||||
DEBUG_IMX35_UART || \
|
||||
DEBUG_IMX50_UART || \
|
||||
DEBUG_IMX51_UART || \
|
||||
DEBUG_IMX53_UART ||\
|
||||
DEBUG_IMX6Q_UART || \
|
||||
|
||||
@ -91,6 +91,7 @@ CONFIG_SMSC911X=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_KEYBOARD_IMX=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
@ -118,6 +119,7 @@ CONFIG_IMX2_WDT=y
|
||||
CONFIG_MFD_MC13XXX_SPI=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_MC13783=y
|
||||
CONFIG_REGULATOR_MC13892=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
|
||||
@ -28,11 +28,13 @@ CONFIG_MACH_QONG=y
|
||||
CONFIG_MACH_ARMADILLO5X0=y
|
||||
CONFIG_MACH_KZM_ARM11_01=y
|
||||
CONFIG_MACH_IMX31_DT=y
|
||||
CONFIG_MACH_IMX35_DT=y
|
||||
CONFIG_MACH_PCM043=y
|
||||
CONFIG_MACH_MX35_3DS=y
|
||||
CONFIG_MACH_VPR200=y
|
||||
CONFIG_MACH_IMX51_DT=y
|
||||
CONFIG_MACH_EUKREA_CPUIMX51SD=y
|
||||
CONFIG_SOC_IMX50=y
|
||||
CONFIG_SOC_IMX53=y
|
||||
CONFIG_SOC_IMX6Q=y
|
||||
CONFIG_SOC_IMX6SL=y
|
||||
@ -41,7 +43,7 @@ CONFIG_SMP=y
|
||||
CONFIG_VMSPLIT_2G=y
|
||||
CONFIG_PREEMPT_VOLUNTARY=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
@ -89,7 +91,6 @@ CONFIG_MTD_UBI=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EEPROM_AT25=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
@ -118,6 +119,7 @@ CONFIG_SMC91X=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
CONFIG_AT803X_PHY=y
|
||||
CONFIG_BRCMFMAC=m
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
@ -129,6 +131,8 @@ CONFIG_MOUSE_PS2_ELANTECH=y
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_EGALAX=y
|
||||
CONFIG_TOUCHSCREEN_MC13783=y
|
||||
CONFIG_TOUCHSCREEN_TSC2007=y
|
||||
CONFIG_TOUCHSCREEN_STMPE=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_MMA8450=y
|
||||
CONFIG_SERIO_SERPORT=m
|
||||
@ -156,14 +160,19 @@ CONFIG_IMX2_WDT=y
|
||||
CONFIG_MFD_DA9052_I2C=y
|
||||
CONFIG_MFD_MC13XXX_SPI=y
|
||||
CONFIG_MFD_MC13XXX_I2C=y
|
||||
CONFIG_MFD_STMPE=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_ANATOP=y
|
||||
CONFIG_REGULATOR_DA9052=y
|
||||
CONFIG_REGULATOR_MC13783=y
|
||||
CONFIG_REGULATOR_MC13892=y
|
||||
CONFIG_REGULATOR_PFUZE100=y
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||
CONFIG_MEDIA_RC_SUPPORT=y
|
||||
CONFIG_RC_DEVICES=y
|
||||
CONFIG_IR_GPIO_CIR=y
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_SOC_CAMERA=y
|
||||
CONFIG_VIDEO_MX3=y
|
||||
|
||||
@ -43,6 +43,14 @@
|
||||
#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
|
||||
#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
|
||||
|
||||
#define IMX50_UART1_BASE_ADDR 0x53fbc000
|
||||
#define IMX50_UART2_BASE_ADDR 0x53fc0000
|
||||
#define IMX50_UART3_BASE_ADDR 0x5000c000
|
||||
#define IMX50_UART4_BASE_ADDR 0x53ff0000
|
||||
#define IMX50_UART5_BASE_ADDR 0x63f90000
|
||||
#define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR
|
||||
#define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n)
|
||||
|
||||
#define IMX51_UART1_BASE_ADDR 0x73fbc000
|
||||
#define IMX51_UART2_BASE_ADDR 0x73fc0000
|
||||
#define IMX51_UART3_BASE_ADDR 0x7000c000
|
||||
@ -85,6 +93,8 @@
|
||||
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
|
||||
#elif defined(CONFIG_DEBUG_IMX35_UART)
|
||||
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
|
||||
#elif defined(CONFIG_DEBUG_IMX50_UART)
|
||||
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX50)
|
||||
#elif defined(CONFIG_DEBUG_IMX51_UART)
|
||||
#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
|
||||
#elif defined(CONFIG_DEBUG_IMX53_UART)
|
||||
|
||||
@ -11,6 +11,7 @@ config ARCH_MXC
|
||||
select GENERIC_IRQ_CHIP
|
||||
select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
|
||||
select MULTI_IRQ_HANDLER
|
||||
select PINCTRL
|
||||
select SOC_BUS
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
@ -20,16 +21,6 @@ config ARCH_MXC
|
||||
menu "Freescale i.MX support"
|
||||
depends on ARCH_MXC
|
||||
|
||||
config MXC_IRQ_PRIOR
|
||||
bool "Use IRQ priority"
|
||||
help
|
||||
Select this if you want to use prioritized IRQ handling.
|
||||
This feature prevents higher priority ISR to be interrupted
|
||||
by lower priority IRQ.
|
||||
This may be useful in embedded applications, where are strong
|
||||
requirements for timing.
|
||||
Say N here, unless you have a specialized requirement.
|
||||
|
||||
config MXC_TZIC
|
||||
bool
|
||||
|
||||
@ -109,6 +100,7 @@ config SOC_IMX25
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select CPU_ARM926T
|
||||
select MXC_AVIC
|
||||
select PINCTRL_IMX25
|
||||
|
||||
config SOC_IMX27
|
||||
bool
|
||||
@ -118,6 +110,7 @@ config SOC_IMX27
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MACH_MX27
|
||||
select MXC_AVIC
|
||||
select PINCTRL_IMX27
|
||||
|
||||
config SOC_IMX31
|
||||
bool
|
||||
@ -133,6 +126,7 @@ config SOC_IMX35
|
||||
select HAVE_EPIT
|
||||
select MXC_AVIC
|
||||
select SMP_ON_UP if SMP
|
||||
select PINCTRL
|
||||
|
||||
config SOC_IMX5
|
||||
bool
|
||||
@ -145,7 +139,6 @@ config SOC_IMX5
|
||||
config SOC_IMX51
|
||||
bool
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX51
|
||||
select SOC_IMX5
|
||||
|
||||
@ -619,6 +612,13 @@ config MACH_IMX31_DT
|
||||
|
||||
comment "MX35 platforms:"
|
||||
|
||||
config MACH_IMX35_DT
|
||||
bool "Support i.MX35 platforms from device tree"
|
||||
select SOC_IMX35
|
||||
help
|
||||
Include support for Freescale i.MX35 based platforms
|
||||
using the device tree for discovery.
|
||||
|
||||
config MACH_PCM043
|
||||
bool "Support Phytec pcm043 (i.MX35) platforms"
|
||||
select IMX_HAVE_PLATFORM_FLEXCAN
|
||||
@ -766,11 +766,19 @@ endchoice
|
||||
|
||||
comment "Device tree only"
|
||||
|
||||
config SOC_IMX50
|
||||
bool "i.MX50 support"
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL_IMX50
|
||||
select SOC_IMX5
|
||||
|
||||
help
|
||||
This enables support for Freescale i.MX50 processor.
|
||||
|
||||
config SOC_IMX53
|
||||
bool "i.MX53 support"
|
||||
select HAVE_IMX_SRC
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX53
|
||||
select SOC_IMX5
|
||||
|
||||
@ -796,7 +804,6 @@ config SOC_IMX6Q
|
||||
select MFD_SYSCON
|
||||
select MIGHT_HAVE_PCI
|
||||
select PCI_DOMAINS if PCI
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX6Q
|
||||
select PL310_ERRATA_588369 if CACHE_PL310
|
||||
select PL310_ERRATA_727915 if CACHE_PL310
|
||||
@ -817,7 +824,6 @@ config SOC_IMX6SL
|
||||
select HAVE_IMX_MMDC
|
||||
select HAVE_IMX_SRC
|
||||
select MFD_SYSCON
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX6SL
|
||||
select PL310_ERRATA_588369 if CACHE_PL310
|
||||
select PL310_ERRATA_727915 if CACHE_PL310
|
||||
@ -831,7 +837,6 @@ config SOC_VF610
|
||||
select CPU_V7
|
||||
select ARM_GIC
|
||||
select CLKSRC_OF
|
||||
select PINCTRL
|
||||
select PINCTRL_VF610
|
||||
select VF_PIT_TIMER
|
||||
select PL310_ERRATA_588369 if CACHE_PL310
|
||||
|
||||
@ -89,6 +89,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
|
||||
obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
|
||||
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
|
||||
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
|
||||
obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
|
||||
|
||||
obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
|
||||
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
|
||||
@ -112,6 +113,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
|
||||
obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
|
||||
|
||||
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
|
||||
obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
|
||||
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
|
||||
|
||||
obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
|
||||
|
||||
@ -54,28 +54,6 @@
|
||||
static void __iomem *avic_base;
|
||||
static struct irq_domain *domain;
|
||||
|
||||
#ifdef CONFIG_MXC_IRQ_PRIOR
|
||||
static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
|
||||
{
|
||||
struct irq_data *d = irq_get_irq_data(irq);
|
||||
unsigned int temp;
|
||||
unsigned int mask = 0x0F << irq % 8 * 4;
|
||||
|
||||
irq = d->hwirq;
|
||||
|
||||
if (irq >= AVIC_NUM_IRQS)
|
||||
return -EINVAL;
|
||||
|
||||
temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
|
||||
temp &= ~mask;
|
||||
temp |= prio & mask;
|
||||
|
||||
__raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FIQ
|
||||
static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
|
||||
{
|
||||
@ -102,9 +80,6 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
|
||||
|
||||
|
||||
static struct mxc_extra_irq avic_extra_irq = {
|
||||
#ifdef CONFIG_MXC_IRQ_PRIOR
|
||||
.set_priority = avic_irq_set_priority,
|
||||
#endif
|
||||
#ifdef CONFIG_FIQ
|
||||
.set_irq_fiq = avic_set_irq_fiq,
|
||||
#endif
|
||||
|
||||
@ -72,7 +72,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
|
||||
|
||||
reg = readl(gate->reg);
|
||||
|
||||
if (((reg >> gate->bit_idx) & 3) == 3)
|
||||
if (((reg >> gate->bit_idx) & 1) == 1)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
|
||||
@ -45,6 +45,8 @@ static struct arm_ahb_div clk_consumer[] = {
|
||||
static char hsp_div_532[] = { 4, 8, 3, 0 };
|
||||
static char hsp_div_400[] = { 3, 6, 3, 0 };
|
||||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static const char *std_sel[] = {"ppll", "arm"};
|
||||
static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
|
||||
|
||||
@ -286,3 +288,15 @@ int __init mx35_clocks_init(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init mx35_clocks_init_dt(struct device_node *ccm_node)
|
||||
{
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx35_clocks_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
|
||||
|
||||
@ -12,11 +12,11 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
|
||||
#include "crm-regs-imx5.h"
|
||||
#include "clk.h"
|
||||
@ -83,50 +83,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_
|
||||
static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
|
||||
static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
|
||||
|
||||
|
||||
enum imx5_clks {
|
||||
dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
|
||||
uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
|
||||
emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
|
||||
usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
|
||||
tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
|
||||
uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
|
||||
gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
|
||||
gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
|
||||
esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
|
||||
ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
|
||||
ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
|
||||
ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
|
||||
vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
|
||||
uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
|
||||
esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
|
||||
mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
|
||||
ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
|
||||
ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
|
||||
periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
|
||||
tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
|
||||
esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
|
||||
usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
|
||||
pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
|
||||
ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
|
||||
usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
|
||||
ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
|
||||
ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
|
||||
ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
|
||||
ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
|
||||
ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
|
||||
epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
|
||||
can_sel, can1_serial_gate, can1_ipg_gate,
|
||||
owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
|
||||
cko1_sel, cko1_podf, cko1,
|
||||
cko2_sel, cko2_podf, cko2,
|
||||
srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
|
||||
spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
|
||||
spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
|
||||
ocram, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static struct clk *clk[IMX5_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
||||
@ -135,236 +92,296 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
||||
{
|
||||
int i;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
|
||||
clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
|
||||
clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
|
||||
clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
|
||||
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil);
|
||||
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc);
|
||||
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
|
||||
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
|
||||
|
||||
clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
|
||||
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
|
||||
clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
|
||||
main_bus_sel, ARRAY_SIZE(main_bus_sel));
|
||||
clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
|
||||
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
|
||||
clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
|
||||
clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
|
||||
clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
|
||||
clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
|
||||
per_root_sel, ARRAY_SIZE(per_root_sel));
|
||||
clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
|
||||
clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
|
||||
clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
|
||||
clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
|
||||
clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
|
||||
clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
|
||||
clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
|
||||
clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
|
||||
clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
|
||||
clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
|
||||
clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
|
||||
clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
|
||||
clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
|
||||
clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
|
||||
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
|
||||
clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
|
||||
main_bus_sel, ARRAY_SIZE(main_bus_sel));
|
||||
clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
|
||||
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
|
||||
clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
|
||||
clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
|
||||
clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
|
||||
clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
|
||||
per_root_sel, ARRAY_SIZE(per_root_sel));
|
||||
clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
|
||||
clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
|
||||
clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
|
||||
clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
|
||||
clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
|
||||
clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
|
||||
clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
|
||||
clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
|
||||
clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
|
||||
clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
|
||||
clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
|
||||
clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
|
||||
clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
|
||||
|
||||
clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
|
||||
clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
|
||||
clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
|
||||
clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
|
||||
clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
|
||||
clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
|
||||
clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
|
||||
clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
|
||||
clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
|
||||
clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
|
||||
clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
|
||||
clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
|
||||
|
||||
clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
|
||||
emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
|
||||
clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
|
||||
clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
|
||||
clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
|
||||
clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
|
||||
clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
|
||||
clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
|
||||
clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
|
||||
clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
|
||||
clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
|
||||
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
|
||||
clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
|
||||
clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
|
||||
clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
|
||||
clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
|
||||
clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
|
||||
clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
|
||||
clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
|
||||
clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
|
||||
clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
|
||||
clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
|
||||
clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
|
||||
clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
|
||||
clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
|
||||
clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
|
||||
clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
|
||||
clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
|
||||
clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
|
||||
clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
|
||||
clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
|
||||
clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
|
||||
clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
|
||||
clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
|
||||
clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
|
||||
clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
|
||||
clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
|
||||
clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
|
||||
clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
|
||||
clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
|
||||
clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
|
||||
clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
|
||||
clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
|
||||
clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
|
||||
clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
|
||||
clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
|
||||
clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
|
||||
clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
|
||||
clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
|
||||
clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
|
||||
clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
|
||||
clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
|
||||
clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
|
||||
clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
|
||||
clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
|
||||
clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
|
||||
clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
|
||||
clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
|
||||
clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
|
||||
clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
|
||||
clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
|
||||
clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
|
||||
clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
|
||||
clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
|
||||
clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
|
||||
clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
|
||||
emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
|
||||
clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
|
||||
clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
|
||||
clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
|
||||
clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
|
||||
clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
|
||||
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
|
||||
clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
|
||||
clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
|
||||
clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
|
||||
clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
|
||||
clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
|
||||
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
|
||||
clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
|
||||
clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
|
||||
clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
|
||||
clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
|
||||
clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
|
||||
clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
|
||||
clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
|
||||
clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
|
||||
clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
|
||||
clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
|
||||
clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
|
||||
clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
|
||||
clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
|
||||
clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
|
||||
clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
|
||||
clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
|
||||
clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
|
||||
clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
|
||||
clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
|
||||
clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
|
||||
clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
|
||||
clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
|
||||
clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
|
||||
clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
|
||||
clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
|
||||
clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
|
||||
clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
|
||||
clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
|
||||
clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
|
||||
clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
|
||||
clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
|
||||
clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
|
||||
clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
|
||||
clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
|
||||
clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
|
||||
clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
|
||||
clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
|
||||
clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
|
||||
clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
|
||||
clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
|
||||
clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
|
||||
clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
|
||||
clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
|
||||
clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
|
||||
clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
|
||||
clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
|
||||
clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
|
||||
clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
|
||||
clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
|
||||
clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
|
||||
clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
|
||||
clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
|
||||
clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
|
||||
|
||||
clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
|
||||
clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
|
||||
clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
|
||||
clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
|
||||
clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
|
||||
clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
|
||||
clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
|
||||
clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
|
||||
clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
|
||||
clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
|
||||
clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
|
||||
clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
|
||||
clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
|
||||
clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
|
||||
clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
|
||||
clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
|
||||
clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
|
||||
clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
|
||||
clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
|
||||
clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
|
||||
clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
|
||||
clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
|
||||
clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
|
||||
clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
|
||||
clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
|
||||
clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
|
||||
clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
|
||||
clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
|
||||
clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
|
||||
clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
|
||||
clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
|
||||
clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
|
||||
spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
|
||||
clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
|
||||
clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
|
||||
clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
|
||||
clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
|
||||
clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
|
||||
clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
|
||||
clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
|
||||
clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
|
||||
clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
|
||||
clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
|
||||
clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
|
||||
clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
|
||||
clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
|
||||
clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
|
||||
clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
|
||||
clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
|
||||
clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
|
||||
clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
|
||||
clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
|
||||
clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
|
||||
clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
|
||||
clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
|
||||
clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
|
||||
clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
|
||||
clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
|
||||
clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
|
||||
clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
|
||||
clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
|
||||
clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
|
||||
clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
|
||||
clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
|
||||
clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
|
||||
clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
|
||||
clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
|
||||
spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
|
||||
clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
|
||||
clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
|
||||
clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
|
||||
clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX5 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
|
||||
clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
|
||||
clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
|
||||
clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
|
||||
clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
|
||||
clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
|
||||
clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
|
||||
clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
|
||||
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
|
||||
clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
|
||||
clk_register_clkdev(clk[cpu_podf], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[iim_gate], "iim", NULL);
|
||||
clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
|
||||
clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
|
||||
clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
|
||||
clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
|
||||
clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
|
||||
clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
|
||||
clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
|
||||
clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
|
||||
|
||||
/* Set SDHC parents to be PLL2 */
|
||||
clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
|
||||
clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
||||
/* move usb phy clk to 24MHz */
|
||||
clk_set_parent(clk[usb_phy_sel], clk[osc]);
|
||||
clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
|
||||
|
||||
clk_prepare_enable(clk[gpc_dvfs]);
|
||||
clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
|
||||
clk_prepare_enable(clk[aips_tz1]);
|
||||
clk_prepare_enable(clk[aips_tz2]); /* fec */
|
||||
clk_prepare_enable(clk[spba]);
|
||||
clk_prepare_enable(clk[emi_fast_gate]); /* fec */
|
||||
clk_prepare_enable(clk[emi_slow_gate]); /* eim */
|
||||
clk_prepare_enable(clk[mipi_hsc1_gate]);
|
||||
clk_prepare_enable(clk[mipi_hsc2_gate]);
|
||||
clk_prepare_enable(clk[mipi_esc_gate]);
|
||||
clk_prepare_enable(clk[mipi_hsp_gate]);
|
||||
clk_prepare_enable(clk[tmax1]);
|
||||
clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
|
||||
clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
|
||||
clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
|
||||
clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
|
||||
clk_prepare_enable(clk[IMX5_CLK_SPBA]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
|
||||
clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
|
||||
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
|
||||
clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
|
||||
}
|
||||
|
||||
static void __init mx50_clocks_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *base;
|
||||
unsigned long r;
|
||||
int i, irq;
|
||||
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
|
||||
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
|
||||
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
|
||||
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
|
||||
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
|
||||
clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
|
||||
clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
|
||||
clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
|
||||
|
||||
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
|
||||
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
|
||||
clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
|
||||
clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
|
||||
|
||||
clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
|
||||
mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
|
||||
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
|
||||
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX50 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(0, 0, 0, 0);
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
|
||||
|
||||
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
|
||||
imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
|
||||
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
|
||||
|
||||
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
|
||||
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
mxc_timer_init(base, irq);
|
||||
}
|
||||
CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
|
||||
|
||||
int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
||||
unsigned long rate_ckih1, unsigned long rate_ckih2)
|
||||
{
|
||||
@ -372,38 +389,40 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
||||
u32 val;
|
||||
struct device_node *np;
|
||||
|
||||
clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
|
||||
clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
|
||||
clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
|
||||
clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
|
||||
mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
|
||||
clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
|
||||
mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
|
||||
clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
|
||||
mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
|
||||
clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
|
||||
mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
|
||||
clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
|
||||
clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
|
||||
clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
|
||||
clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
|
||||
clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
|
||||
clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
|
||||
clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
|
||||
clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
|
||||
clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
|
||||
clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
|
||||
clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
|
||||
clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
|
||||
clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
|
||||
mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
|
||||
clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
|
||||
spdif_sel, ARRAY_SIZE(spdif_sel));
|
||||
clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
|
||||
clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
|
||||
clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
|
||||
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
|
||||
clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
|
||||
mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
|
||||
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
|
||||
mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
|
||||
clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
|
||||
mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
|
||||
clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
|
||||
mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
|
||||
clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
|
||||
clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
|
||||
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
|
||||
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
|
||||
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
|
||||
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
|
||||
clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
|
||||
clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
|
||||
clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
|
||||
clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
|
||||
clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
|
||||
clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
|
||||
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
|
||||
mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
|
||||
clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
|
||||
spdif_sel, ARRAY_SIZE(spdif_sel));
|
||||
clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
|
||||
clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
|
||||
clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
|
||||
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
|
||||
clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
@ -417,37 +436,37 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
||||
|
||||
mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
|
||||
|
||||
clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
|
||||
clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
|
||||
clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
|
||||
clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
|
||||
|
||||
/* set the usboh3 parent to pll2_sw */
|
||||
clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
|
||||
clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
||||
/* set SDHC root clock to 166.25MHZ*/
|
||||
clk_set_rate(clk[esdhc_a_podf], 166250000);
|
||||
clk_set_rate(clk[esdhc_b_podf], 166250000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
|
||||
|
||||
/* System timer */
|
||||
mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
|
||||
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
|
||||
imx_print_silicon_rev("i.MX51", mx51_revision());
|
||||
clk_disable_unprepare(clk[iim_gate]);
|
||||
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
|
||||
|
||||
/*
|
||||
* Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
|
||||
@ -479,57 +498,59 @@ static void __init mx53_clocks_init(struct device_node *np)
|
||||
unsigned long r;
|
||||
void __iomem *base;
|
||||
|
||||
clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
|
||||
clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
|
||||
clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
|
||||
clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
|
||||
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
|
||||
|
||||
clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
|
||||
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
|
||||
mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
|
||||
clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
|
||||
clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
|
||||
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
|
||||
mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
|
||||
clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
|
||||
clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
|
||||
clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
|
||||
mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
|
||||
clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
|
||||
mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
|
||||
clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
|
||||
mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
|
||||
clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
|
||||
clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
|
||||
clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
|
||||
clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
|
||||
clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
|
||||
clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
|
||||
clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
|
||||
clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
|
||||
clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
|
||||
mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
|
||||
clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
|
||||
clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
|
||||
clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
|
||||
clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
|
||||
clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
|
||||
clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
|
||||
clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
|
||||
clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
|
||||
mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
|
||||
clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
|
||||
clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
|
||||
clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
|
||||
mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
|
||||
clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
|
||||
clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
|
||||
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
|
||||
mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
|
||||
clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
|
||||
mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
|
||||
clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
|
||||
mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
|
||||
clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
|
||||
clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
|
||||
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
|
||||
clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
|
||||
clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
|
||||
clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
|
||||
clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
|
||||
clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
|
||||
clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
|
||||
mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
|
||||
clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
|
||||
clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
|
||||
clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
|
||||
clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
|
||||
clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
|
||||
clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
|
||||
clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
|
||||
|
||||
clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
|
||||
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
|
||||
clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
|
||||
clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
|
||||
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
|
||||
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
|
||||
clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
|
||||
clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
|
||||
|
||||
clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
|
||||
mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
|
||||
clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
|
||||
clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
|
||||
clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
|
||||
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
|
||||
clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
|
||||
mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
|
||||
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
|
||||
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
|
||||
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
|
||||
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
@ -542,33 +563,36 @@ static void __init mx53_clocks_init(struct device_node *np)
|
||||
|
||||
mx5_clocks_common_init(0, 0, 0, 0);
|
||||
|
||||
clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
|
||||
clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
|
||||
clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[esdhc_a_podf], 200000000);
|
||||
clk_set_rate(clk[esdhc_b_podf], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
|
||||
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
/* move can bus clk to 24MHz */
|
||||
clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
|
||||
|
||||
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
|
||||
imx_print_silicon_rev("i.MX53", mx53_revision());
|
||||
clk_disable_unprepare(clk[iim_gate]);
|
||||
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
|
||||
|
||||
r = clk_round_rate(clk[usboh3_per_gate], 54000000);
|
||||
clk_set_rate(clk[usboh3_per_gate], r);
|
||||
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
|
||||
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
|
||||
base = of_iomap(np, 0);
|
||||
|
||||
@ -114,7 +114,7 @@ static struct clk *clk[clk_max];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static enum mx6q_clks const clks_init_on[] __initconst = {
|
||||
mmdc_ch0_axi, rom, pll1_sys,
|
||||
mmdc_ch0_axi, rom, arm,
|
||||
};
|
||||
|
||||
static struct clk_div_table clk_enet_ref_table[] = {
|
||||
@ -475,6 +475,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||
if (ret)
|
||||
pr_warn("failed to set up CLKO: %d\n", ret);
|
||||
|
||||
/* Audio-related clocks configuration */
|
||||
clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
|
||||
|
||||
/* All existing boards with PCIe use LVDS1 */
|
||||
if (IS_ENABLED(CONFIG_PCI_IMX6))
|
||||
clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
|
||||
|
||||
@ -29,14 +29,14 @@ static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf"
|
||||
static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
|
||||
static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
|
||||
static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
|
||||
static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
|
||||
static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
|
||||
static const char const *perclk_sels[] = { "ipg", "osc", };
|
||||
static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
|
||||
static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
|
||||
static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
|
||||
static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
|
||||
static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
|
||||
static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
|
||||
static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
|
||||
static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
|
||||
static const char const *uart_sels[] = { "pll3_80m", "osc", };
|
||||
|
||||
@ -63,7 +63,7 @@ static struct clk_div_table video_div_table[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct clk *clks[IMX6SL_CLK_CLK_END];
|
||||
static struct clk *clks[IMX6SL_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
||||
@ -104,6 +104,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
||||
|
||||
/* dev name parent_name flags reg shift width div: flags, div_table lock */
|
||||
clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
|
||||
clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
|
||||
@ -232,6 +233,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
|
||||
clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
|
||||
clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
|
||||
clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
|
||||
clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
|
||||
clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
|
||||
@ -261,6 +263,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
||||
clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
|
||||
}
|
||||
|
||||
/* Audio-related clocks configuration */
|
||||
clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
||||
@ -109,12 +109,23 @@ static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pfd_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pfd *pfd = to_clk_pfd(hw);
|
||||
|
||||
if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1)))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_pfd_ops = {
|
||||
.enable = clk_pfd_enable,
|
||||
.disable = clk_pfd_disable,
|
||||
.recalc_rate = clk_pfd_recalc_rate,
|
||||
.round_rate = clk_pfd_round_rate,
|
||||
.set_rate = clk_pfd_set_rate,
|
||||
.is_enabled = clk_pfd_is_enabled,
|
||||
};
|
||||
|
||||
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
|
||||
|
||||
@ -18,6 +18,11 @@
|
||||
*
|
||||
* PLL clock version 1, found on i.MX1/21/25/27/31/35
|
||||
*/
|
||||
|
||||
#define MFN_BITS (10)
|
||||
#define MFN_SIGN (BIT(MFN_BITS - 1))
|
||||
#define MFN_MASK (MFN_SIGN - 1)
|
||||
|
||||
struct clk_pllv1 {
|
||||
struct clk_hw hw;
|
||||
void __iomem *base;
|
||||
@ -25,6 +30,11 @@ struct clk_pllv1 {
|
||||
|
||||
#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
|
||||
|
||||
static inline bool mfn_is_negative(unsigned int mfn)
|
||||
{
|
||||
return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
|
||||
}
|
||||
|
||||
static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
|
||||
|
||||
/*
|
||||
* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
|
||||
* 2's complements number
|
||||
* 2's complements number.
|
||||
* On i.MX27 the bit 9 is the sign bit.
|
||||
*/
|
||||
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
|
||||
mfn_abs = 0x400 - mfn;
|
||||
if (mfn_is_negative(mfn)) {
|
||||
if (cpu_is_mx27())
|
||||
mfn_abs = mfn & MFN_MASK;
|
||||
else
|
||||
mfn_abs = BIT(MFN_BITS) - mfn;
|
||||
}
|
||||
|
||||
rate = parent_rate * 2;
|
||||
rate /= pd + 1;
|
||||
@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
|
||||
|
||||
do_div(ll, mfd + 1);
|
||||
|
||||
if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
|
||||
if (mfn_is_negative(mfn))
|
||||
ll = -ll;
|
||||
|
||||
ll = (rate * mfi) + ll;
|
||||
|
||||
@ -298,6 +298,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
||||
clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
|
||||
clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
|
||||
|
||||
clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
|
||||
clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
|
||||
clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
|
||||
clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
|
||||
|
||||
clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
|
||||
clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
|
||||
clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
|
||||
|
||||
@ -108,6 +108,7 @@ void tzic_handle_irq(struct pt_regs *);
|
||||
#define imx27_handle_irq avic_handle_irq
|
||||
#define imx31_handle_irq avic_handle_irq
|
||||
#define imx35_handle_irq avic_handle_irq
|
||||
#define imx50_handle_irq tzic_handle_irq
|
||||
#define imx51_handle_irq tzic_handle_irq
|
||||
#define imx53_handle_irq tzic_handle_irq
|
||||
|
||||
|
||||
@ -25,7 +25,7 @@ static void __init imx31_dt_init(void)
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *imx31_dt_board_compat[] __initdata = {
|
||||
static const char *imx31_dt_board_compat[] __initconst = {
|
||||
"fsl,imx31",
|
||||
NULL
|
||||
};
|
||||
|
||||
50
arch/arm/mach-imx/imx35-dt.c
Normal file
50
arch/arm/mach-imx/imx35-dt.c
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright 2012 Steffen Trumtrar, Pengutronix
|
||||
*
|
||||
* based on imx27-dt.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include "common.h"
|
||||
#include "mx35.h"
|
||||
|
||||
static void __init imx35_dt_init(void)
|
||||
{
|
||||
mxc_arch_reset_init_dt();
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
NULL, NULL);
|
||||
}
|
||||
|
||||
static void __init imx35_irq_init(void)
|
||||
{
|
||||
imx_init_l2cache();
|
||||
mx35_init_irq();
|
||||
}
|
||||
|
||||
static const char *imx35_dt_board_compat[] __initconst = {
|
||||
"fsl,imx35",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
|
||||
.map_io = mx35_map_io,
|
||||
.init_early = imx35_init_early,
|
||||
.init_irq = imx35_irq_init,
|
||||
.handle_irq = imx35_handle_irq,
|
||||
.init_machine = imx35_dt_init,
|
||||
.dt_compat = imx35_dt_board_compat,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
@ -29,7 +29,7 @@ static void __init imx51_dt_init(void)
|
||||
platform_device_register_full(&devinfo);
|
||||
}
|
||||
|
||||
static const char *imx51_dt_board_compat[] __initdata = {
|
||||
static const char *imx51_dt_board_compat[] __initconst = {
|
||||
"fsl,imx51",
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -24,7 +24,6 @@
|
||||
|
||||
struct mxc_extra_irq
|
||||
{
|
||||
int (*set_priority)(unsigned char irq, unsigned char prio);
|
||||
int (*set_irq_fiq)(unsigned int irq, unsigned int type);
|
||||
};
|
||||
|
||||
|
||||
38
arch/arm/mach-imx/mach-imx50.c
Normal file
38
arch/arm/mach-imx/mach-imx50.c
Normal file
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright 2013 Greg Ungerer <gerg@uclinux.org>
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static void __init imx50_dt_init(void)
|
||||
{
|
||||
mxc_arch_reset_init_dt();
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *imx50_dt_board_compat[] __initconst = {
|
||||
"fsl,imx50",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
|
||||
.map_io = mx53_map_io,
|
||||
.init_irq = mx53_init_irq,
|
||||
.handle_irq = imx50_handle_irq,
|
||||
.init_machine = imx50_dt_init,
|
||||
.dt_compat = imx50_dt_board_compat,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
@ -31,7 +31,7 @@ static void __init imx53_dt_init(void)
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *imx53_dt_board_compat[] __initdata = {
|
||||
static const char *imx53_dt_board_compat[] __initconst = {
|
||||
"fsl,imx53",
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
@ -23,6 +24,7 @@
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/regmap.h>
|
||||
@ -78,6 +80,34 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
|
||||
* as they are used for slots1-7 PERST#
|
||||
*/
|
||||
static void ventana_pciesw_early_fixup(struct pci_dev *dev)
|
||||
{
|
||||
u32 dw;
|
||||
|
||||
if (!of_machine_is_compatible("gw,ventana"))
|
||||
return;
|
||||
|
||||
if (dev->devfn != 0)
|
||||
return;
|
||||
|
||||
pci_read_config_dword(dev, 0x62c, &dw);
|
||||
dw |= 0xaaa8; // GPIO1-7 outputs
|
||||
pci_write_config_dword(dev, 0x62c, dw);
|
||||
|
||||
pci_read_config_dword(dev, 0x644, &dw);
|
||||
dw |= 0xfe; // GPIO1-7 output high
|
||||
pci_write_config_dword(dev, 0x644, dw);
|
||||
|
||||
msleep(100);
|
||||
}
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
|
||||
|
||||
static int ar8031_phy_fixup(struct phy_device *dev)
|
||||
{
|
||||
u16 val;
|
||||
@ -243,7 +273,7 @@ static void __init imx6q_init_irq(void)
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
static const char *imx6q_dt_compat[] __initdata = {
|
||||
static const char *imx6q_dt_compat[] __initconst = {
|
||||
"fsl,imx6dl",
|
||||
"fsl,imx6q",
|
||||
NULL,
|
||||
|
||||
@ -34,6 +34,13 @@ static void __init imx6sl_fec_init(void)
|
||||
}
|
||||
}
|
||||
|
||||
static void __init imx6sl_init_late(void)
|
||||
{
|
||||
/* imx6sl reuses imx6q cpufreq driver */
|
||||
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
|
||||
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
|
||||
}
|
||||
|
||||
static void __init imx6sl_init_machine(void)
|
||||
{
|
||||
struct device *parent;
|
||||
@ -61,7 +68,7 @@ static void __init imx6sl_init_irq(void)
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
static const char *imx6sl_dt_compat[] __initdata = {
|
||||
static const char *imx6sl_dt_compat[] __initconst = {
|
||||
"fsl,imx6sl",
|
||||
NULL,
|
||||
};
|
||||
@ -70,6 +77,7 @@ DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
|
||||
.map_io = debug_ll_io_init,
|
||||
.init_irq = imx6sl_init_irq,
|
||||
.init_machine = imx6sl_init_machine,
|
||||
.init_late = imx6sl_init_late,
|
||||
.dt_compat = imx6sl_dt_compat,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
|
||||
@ -26,7 +26,7 @@ static void __init vf610_init_irq(void)
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
static const char *vf610_dt_compat[] __initdata = {
|
||||
static const char *vf610_dt_compat[] __initconst = {
|
||||
"fsl,vf610",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@ -89,15 +89,7 @@ void __init imx51_init_early(void)
|
||||
|
||||
void __init imx53_init_early(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *base;
|
||||
|
||||
mxc_set_cpu_type(MXC_CPU_MX53);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
mxc_iomux_v3_init(base);
|
||||
imx_src_init();
|
||||
}
|
||||
|
||||
|
||||
@ -156,10 +156,16 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
|
||||
}
|
||||
|
||||
/*
|
||||
* Unmask the always pending IOMUXC interrupt #32 as wakeup source to
|
||||
* deassert dsm_request signal, so that we can ensure dsm_request
|
||||
* is not asserted when we're going to write CLPCR register to set LPM.
|
||||
* After setting up LPM bits, we need to mask this wakeup source.
|
||||
* ERR007265: CCM: When improper low-power sequence is used,
|
||||
* the SoC enters low power mode before the ARM core executes WFI.
|
||||
*
|
||||
* Software workaround:
|
||||
* 1) Software should trigger IRQ #32 (IOMUX) to be always pending
|
||||
* by setting IOMUX_GPR1_GINT.
|
||||
* 2) Software should then unmask IRQ #32 in GPC before setting CCM
|
||||
* Low-Power mode.
|
||||
* 3) Software should mask IRQ #32 right after CCM Low-Power mode
|
||||
* is set (set bits 0-1 of CCM_CLPCR).
|
||||
*/
|
||||
iomuxc_irq_desc = irq_to_desc(32);
|
||||
imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
|
||||
@ -219,6 +225,8 @@ void __init imx6q_pm_init(void)
|
||||
WARN_ON(!ccm_base);
|
||||
|
||||
/*
|
||||
* This is for SW workaround step #1 of ERR007265, see comments
|
||||
* in imx6q_set_lpm for details of this errata.
|
||||
* Force IOMUXC irq pending, so that the interrupt to GPC can be
|
||||
* used to deassert dsm_request signal when the signal gets
|
||||
* asserted unexpectedly.
|
||||
|
||||
203
include/dt-bindings/clock/imx5-clock.h
Normal file
203
include/dt-bindings/clock/imx5-clock.h
Normal file
@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX5_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX5_H
|
||||
|
||||
#define IMX5_CLK_DUMMY 0
|
||||
#define IMX5_CLK_CKIL 1
|
||||
#define IMX5_CLK_OSC 2
|
||||
#define IMX5_CLK_CKIH1 3
|
||||
#define IMX5_CLK_CKIH2 4
|
||||
#define IMX5_CLK_AHB 5
|
||||
#define IMX5_CLK_IPG 6
|
||||
#define IMX5_CLK_AXI_A 7
|
||||
#define IMX5_CLK_AXI_B 8
|
||||
#define IMX5_CLK_UART_PRED 9
|
||||
#define IMX5_CLK_UART_ROOT 10
|
||||
#define IMX5_CLK_ESDHC_A_PRED 11
|
||||
#define IMX5_CLK_ESDHC_B_PRED 12
|
||||
#define IMX5_CLK_ESDHC_C_SEL 13
|
||||
#define IMX5_CLK_ESDHC_D_SEL 14
|
||||
#define IMX5_CLK_EMI_SEL 15
|
||||
#define IMX5_CLK_EMI_SLOW_PODF 16
|
||||
#define IMX5_CLK_NFC_PODF 17
|
||||
#define IMX5_CLK_ECSPI_PRED 18
|
||||
#define IMX5_CLK_ECSPI_PODF 19
|
||||
#define IMX5_CLK_USBOH3_PRED 20
|
||||
#define IMX5_CLK_USBOH3_PODF 21
|
||||
#define IMX5_CLK_USB_PHY_PRED 22
|
||||
#define IMX5_CLK_USB_PHY_PODF 23
|
||||
#define IMX5_CLK_CPU_PODF 24
|
||||
#define IMX5_CLK_DI_PRED 25
|
||||
#define IMX5_CLK_TVE_SEL 27
|
||||
#define IMX5_CLK_UART1_IPG_GATE 28
|
||||
#define IMX5_CLK_UART1_PER_GATE 29
|
||||
#define IMX5_CLK_UART2_IPG_GATE 30
|
||||
#define IMX5_CLK_UART2_PER_GATE 31
|
||||
#define IMX5_CLK_UART3_IPG_GATE 32
|
||||
#define IMX5_CLK_UART3_PER_GATE 33
|
||||
#define IMX5_CLK_I2C1_GATE 34
|
||||
#define IMX5_CLK_I2C2_GATE 35
|
||||
#define IMX5_CLK_GPT_IPG_GATE 36
|
||||
#define IMX5_CLK_PWM1_IPG_GATE 37
|
||||
#define IMX5_CLK_PWM1_HF_GATE 38
|
||||
#define IMX5_CLK_PWM2_IPG_GATE 39
|
||||
#define IMX5_CLK_PWM2_HF_GATE 40
|
||||
#define IMX5_CLK_GPT_HF_GATE 41
|
||||
#define IMX5_CLK_FEC_GATE 42
|
||||
#define IMX5_CLK_USBOH3_PER_GATE 43
|
||||
#define IMX5_CLK_ESDHC1_IPG_GATE 44
|
||||
#define IMX5_CLK_ESDHC2_IPG_GATE 45
|
||||
#define IMX5_CLK_ESDHC3_IPG_GATE 46
|
||||
#define IMX5_CLK_ESDHC4_IPG_GATE 47
|
||||
#define IMX5_CLK_SSI1_IPG_GATE 48
|
||||
#define IMX5_CLK_SSI2_IPG_GATE 49
|
||||
#define IMX5_CLK_SSI3_IPG_GATE 50
|
||||
#define IMX5_CLK_ECSPI1_IPG_GATE 51
|
||||
#define IMX5_CLK_ECSPI1_PER_GATE 52
|
||||
#define IMX5_CLK_ECSPI2_IPG_GATE 53
|
||||
#define IMX5_CLK_ECSPI2_PER_GATE 54
|
||||
#define IMX5_CLK_CSPI_IPG_GATE 55
|
||||
#define IMX5_CLK_SDMA_GATE 56
|
||||
#define IMX5_CLK_EMI_SLOW_GATE 57
|
||||
#define IMX5_CLK_IPU_SEL 58
|
||||
#define IMX5_CLK_IPU_GATE 59
|
||||
#define IMX5_CLK_NFC_GATE 60
|
||||
#define IMX5_CLK_IPU_DI1_GATE 61
|
||||
#define IMX5_CLK_VPU_SEL 62
|
||||
#define IMX5_CLK_VPU_GATE 63
|
||||
#define IMX5_CLK_VPU_REFERENCE_GATE 64
|
||||
#define IMX5_CLK_UART4_IPG_GATE 65
|
||||
#define IMX5_CLK_UART4_PER_GATE 66
|
||||
#define IMX5_CLK_UART5_IPG_GATE 67
|
||||
#define IMX5_CLK_UART5_PER_GATE 68
|
||||
#define IMX5_CLK_TVE_GATE 69
|
||||
#define IMX5_CLK_TVE_PRED 70
|
||||
#define IMX5_CLK_ESDHC1_PER_GATE 71
|
||||
#define IMX5_CLK_ESDHC2_PER_GATE 72
|
||||
#define IMX5_CLK_ESDHC3_PER_GATE 73
|
||||
#define IMX5_CLK_ESDHC4_PER_GATE 74
|
||||
#define IMX5_CLK_USB_PHY_GATE 75
|
||||
#define IMX5_CLK_HSI2C_GATE 76
|
||||
#define IMX5_CLK_MIPI_HSC1_GATE 77
|
||||
#define IMX5_CLK_MIPI_HSC2_GATE 78
|
||||
#define IMX5_CLK_MIPI_ESC_GATE 79
|
||||
#define IMX5_CLK_MIPI_HSP_GATE 80
|
||||
#define IMX5_CLK_LDB_DI1_DIV_3_5 81
|
||||
#define IMX5_CLK_LDB_DI1_DIV 82
|
||||
#define IMX5_CLK_LDB_DI0_DIV_3_5 83
|
||||
#define IMX5_CLK_LDB_DI0_DIV 84
|
||||
#define IMX5_CLK_LDB_DI1_GATE 85
|
||||
#define IMX5_CLK_CAN2_SERIAL_GATE 86
|
||||
#define IMX5_CLK_CAN2_IPG_GATE 87
|
||||
#define IMX5_CLK_I2C3_GATE 88
|
||||
#define IMX5_CLK_LP_APM 89
|
||||
#define IMX5_CLK_PERIPH_APM 90
|
||||
#define IMX5_CLK_MAIN_BUS 91
|
||||
#define IMX5_CLK_AHB_MAX 92
|
||||
#define IMX5_CLK_AIPS_TZ1 93
|
||||
#define IMX5_CLK_AIPS_TZ2 94
|
||||
#define IMX5_CLK_TMAX1 95
|
||||
#define IMX5_CLK_TMAX2 96
|
||||
#define IMX5_CLK_TMAX3 97
|
||||
#define IMX5_CLK_SPBA 98
|
||||
#define IMX5_CLK_UART_SEL 99
|
||||
#define IMX5_CLK_ESDHC_A_SEL 100
|
||||
#define IMX5_CLK_ESDHC_B_SEL 101
|
||||
#define IMX5_CLK_ESDHC_A_PODF 102
|
||||
#define IMX5_CLK_ESDHC_B_PODF 103
|
||||
#define IMX5_CLK_ECSPI_SEL 104
|
||||
#define IMX5_CLK_USBOH3_SEL 105
|
||||
#define IMX5_CLK_USB_PHY_SEL 106
|
||||
#define IMX5_CLK_IIM_GATE 107
|
||||
#define IMX5_CLK_USBOH3_GATE 108
|
||||
#define IMX5_CLK_EMI_FAST_GATE 109
|
||||
#define IMX5_CLK_IPU_DI0_GATE 110
|
||||
#define IMX5_CLK_GPC_DVFS 111
|
||||
#define IMX5_CLK_PLL1_SW 112
|
||||
#define IMX5_CLK_PLL2_SW 113
|
||||
#define IMX5_CLK_PLL3_SW 114
|
||||
#define IMX5_CLK_IPU_DI0_SEL 115
|
||||
#define IMX5_CLK_IPU_DI1_SEL 116
|
||||
#define IMX5_CLK_TVE_EXT_SEL 117
|
||||
#define IMX5_CLK_MX51_MIPI 118
|
||||
#define IMX5_CLK_PLL4_SW 119
|
||||
#define IMX5_CLK_LDB_DI1_SEL 120
|
||||
#define IMX5_CLK_DI_PLL4_PODF 121
|
||||
#define IMX5_CLK_LDB_DI0_SEL 122
|
||||
#define IMX5_CLK_LDB_DI0_GATE 123
|
||||
#define IMX5_CLK_USB_PHY1_GATE 124
|
||||
#define IMX5_CLK_USB_PHY2_GATE 125
|
||||
#define IMX5_CLK_PER_LP_APM 126
|
||||
#define IMX5_CLK_PER_PRED1 127
|
||||
#define IMX5_CLK_PER_PRED2 128
|
||||
#define IMX5_CLK_PER_PODF 129
|
||||
#define IMX5_CLK_PER_ROOT 130
|
||||
#define IMX5_CLK_SSI_APM 131
|
||||
#define IMX5_CLK_SSI1_ROOT_SEL 132
|
||||
#define IMX5_CLK_SSI2_ROOT_SEL 133
|
||||
#define IMX5_CLK_SSI3_ROOT_SEL 134
|
||||
#define IMX5_CLK_SSI_EXT1_SEL 135
|
||||
#define IMX5_CLK_SSI_EXT2_SEL 136
|
||||
#define IMX5_CLK_SSI_EXT1_COM_SEL 137
|
||||
#define IMX5_CLK_SSI_EXT2_COM_SEL 138
|
||||
#define IMX5_CLK_SSI1_ROOT_PRED 139
|
||||
#define IMX5_CLK_SSI1_ROOT_PODF 140
|
||||
#define IMX5_CLK_SSI2_ROOT_PRED 141
|
||||
#define IMX5_CLK_SSI2_ROOT_PODF 142
|
||||
#define IMX5_CLK_SSI_EXT1_PRED 143
|
||||
#define IMX5_CLK_SSI_EXT1_PODF 144
|
||||
#define IMX5_CLK_SSI_EXT2_PRED 145
|
||||
#define IMX5_CLK_SSI_EXT2_PODF 146
|
||||
#define IMX5_CLK_SSI1_ROOT_GATE 147
|
||||
#define IMX5_CLK_SSI2_ROOT_GATE 148
|
||||
#define IMX5_CLK_SSI3_ROOT_GATE 149
|
||||
#define IMX5_CLK_SSI_EXT1_GATE 150
|
||||
#define IMX5_CLK_SSI_EXT2_GATE 151
|
||||
#define IMX5_CLK_EPIT1_IPG_GATE 152
|
||||
#define IMX5_CLK_EPIT1_HF_GATE 153
|
||||
#define IMX5_CLK_EPIT2_IPG_GATE 154
|
||||
#define IMX5_CLK_EPIT2_HF_GATE 155
|
||||
#define IMX5_CLK_CAN_SEL 156
|
||||
#define IMX5_CLK_CAN1_SERIAL_GATE 157
|
||||
#define IMX5_CLK_CAN1_IPG_GATE 158
|
||||
#define IMX5_CLK_OWIRE_GATE 159
|
||||
#define IMX5_CLK_GPU3D_SEL 160
|
||||
#define IMX5_CLK_GPU2D_SEL 161
|
||||
#define IMX5_CLK_GPU3D_GATE 162
|
||||
#define IMX5_CLK_GPU2D_GATE 163
|
||||
#define IMX5_CLK_GARB_GATE 164
|
||||
#define IMX5_CLK_CKO1_SEL 165
|
||||
#define IMX5_CLK_CKO1_PODF 166
|
||||
#define IMX5_CLK_CKO1 167
|
||||
#define IMX5_CLK_CKO2_SEL 168
|
||||
#define IMX5_CLK_CKO2_PODF 169
|
||||
#define IMX5_CLK_CKO2 170
|
||||
#define IMX5_CLK_SRTC_GATE 171
|
||||
#define IMX5_CLK_PATA_GATE 172
|
||||
#define IMX5_CLK_SATA_GATE 173
|
||||
#define IMX5_CLK_SPDIF_XTAL_SEL 174
|
||||
#define IMX5_CLK_SPDIF0_SEL 175
|
||||
#define IMX5_CLK_SPDIF1_SEL 176
|
||||
#define IMX5_CLK_SPDIF0_PRED 177
|
||||
#define IMX5_CLK_SPDIF0_PODF 178
|
||||
#define IMX5_CLK_SPDIF1_PRED 179
|
||||
#define IMX5_CLK_SPDIF1_PODF 180
|
||||
#define IMX5_CLK_SPDIF0_COM_SEL 181
|
||||
#define IMX5_CLK_SPDIF1_COM_SEL 182
|
||||
#define IMX5_CLK_SPDIF0_GATE 183
|
||||
#define IMX5_CLK_SPDIF1_GATE 184
|
||||
#define IMX5_CLK_SPDIF_IPG_GATE 185
|
||||
#define IMX5_CLK_OCRAM 186
|
||||
#define IMX5_CLK_SAHARA_IPG_GATE 187
|
||||
#define IMX5_CLK_SATA_REF 188
|
||||
#define IMX5_CLK_END 189
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
|
||||
@ -143,6 +143,8 @@
|
||||
#define IMX6SL_CLK_USDHC2 130
|
||||
#define IMX6SL_CLK_USDHC3 131
|
||||
#define IMX6SL_CLK_USDHC4 132
|
||||
#define IMX6SL_CLK_CLK_END 133
|
||||
#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
|
||||
#define IMX6SL_CLK_SPBA 134
|
||||
#define IMX6SL_CLK_END 135
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
|
||||
|
||||
@ -160,6 +160,10 @@
|
||||
#define VF610_CLK_GPU2D 147
|
||||
#define VF610_CLK_ENET0 148
|
||||
#define VF610_CLK_ENET1 149
|
||||
#define VF610_CLK_END 150
|
||||
#define VF610_CLK_DMAMUX0 150
|
||||
#define VF610_CLK_DMAMUX1 151
|
||||
#define VF610_CLK_DMAMUX2 152
|
||||
#define VF610_CLK_DMAMUX3 153
|
||||
#define VF610_CLK_END 154
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user