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ARM: LPC32xx: DTS files for device tree conversion
This patch adds the dts files for the reference machine of LPC32xx: * arch/arm/boot/dts/lpc32xx.dtsi: Include for devices based on LPC32xx * arch/arm/boot/dts/phy3250.dts: Board support for PHYTEC phyCORE-LPC3250 Signed-off-by: Roland Stigge <stigge@antcom.de>
This commit is contained in:
Roland Stigge
parent
b78dd16690
commit
e04920d9ef
292
arch/arm/boot/dts/lpc32xx.dtsi
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292
arch/arm/boot/dts/lpc32xx.dtsi
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/*
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* NXP LPC32xx SoC
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*
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* Copyright 2012 Roland Stigge <stigge@antcom.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "nxp,lpc3220";
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interrupt-parent = <&mic>;
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cpus {
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cpu@0 {
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compatible = "arm,arm926ejs";
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};
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};
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x20000000 0x20000000 0x30000000>;
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/*
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* Enable either SLC or MLC
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*/
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slc: flash@20020000 {
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compatible = "nxp,lpc3220-slc";
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reg = <0x20020000 0x1000>;
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status = "disable";
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};
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mlc: flash@200B0000 {
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compatible = "nxp,lpc3220-mlc";
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reg = <0x200B0000 0x1000>;
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status = "disable";
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};
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dma@31000000 {
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compatible = "arm,pl080", "arm,primecell";
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reg = <0x31000000 0x1000>;
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interrupts = <0x1c 0>;
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};
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/*
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* Enable either ohci or usbd (gadget)!
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*/
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ohci@31020000 {
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compatible = "nxp,ohci-nxp", "usb-ohci";
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reg = <0x31020000 0x300>;
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interrupts = <0x3b 0>;
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status = "disable";
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};
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usbd@31020000 {
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compatible = "nxp,lpc3220-udc";
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reg = <0x31020000 0x300>;
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interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
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status = "disable";
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};
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clcd@31040000 {
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compatible = "arm,pl110", "arm,primecell";
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reg = <0x31040000 0x1000>;
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interrupts = <0x0e 0>;
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status = "disable";
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};
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mac: ethernet@31060000 {
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compatible = "nxp,lpc-eth";
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reg = <0x31060000 0x1000>;
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interrupts = <0x1d 0>;
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x20000000 0x20000000 0x30000000>;
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ssp0: ssp@20084000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x20084000 0x1000>;
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interrupts = <0x14 0>;
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};
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spi1: spi@20088000 {
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compatible = "nxp,lpc3220-spi";
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reg = <0x20088000 0x1000>;
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};
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ssp1: ssp@2008c000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x2008c000 0x1000>;
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interrupts = <0x15 0>;
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};
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spi2: spi@20090000 {
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compatible = "nxp,lpc3220-spi";
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reg = <0x20090000 0x1000>;
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};
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i2s0: i2s@20094000 {
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compatible = "nxp,lpc3220-i2s";
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reg = <0x20094000 0x1000>;
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};
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sd@20098000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x20098000 0x1000>;
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interrupts = <0x0f 0>, <0x0d 0>;
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};
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i2s1: i2s@2009C000 {
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compatible = "nxp,lpc3220-i2s";
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reg = <0x2009C000 0x1000>;
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};
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uart3: serial@40080000 {
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compatible = "nxp,serial";
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reg = <0x40080000 0x1000>;
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};
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uart4: serial@40088000 {
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compatible = "nxp,serial";
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reg = <0x40088000 0x1000>;
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};
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uart5: serial@40090000 {
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compatible = "nxp,serial";
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reg = <0x40090000 0x1000>;
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};
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uart6: serial@40098000 {
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compatible = "nxp,serial";
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reg = <0x40098000 0x1000>;
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};
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i2c1: i2c@400A0000 {
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compatible = "nxp,pnx-i2c";
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reg = <0x400A0000 0x100>;
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interrupts = <0x33 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pnx,timeout = <0x64>;
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};
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i2c2: i2c@400A8000 {
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compatible = "nxp,pnx-i2c";
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reg = <0x400A8000 0x100>;
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interrupts = <0x32 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pnx,timeout = <0x64>;
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};
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i2cusb: i2c@31020300 {
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compatible = "nxp,pnx-i2c";
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reg = <0x31020300 0x100>;
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interrupts = <0x3f 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pnx,timeout = <0x64>;
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};
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};
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fab {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x20000000 0x20000000 0x30000000>;
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/*
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* MIC Interrupt controller includes:
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* MIC @40008000
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* SIC1 @4000C000
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* SIC2 @40010000
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*/
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mic: interrupt-controller@40008000 {
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compatible = "nxp,lpc3220-mic";
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interrupt-controller;
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reg = <0x40008000 0xC000>;
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#interrupt-cells = <2>;
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};
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uart1: serial@40014000 {
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compatible = "nxp,serial";
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reg = <0x40014000 0x1000>;
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};
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uart2: serial@40018000 {
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compatible = "nxp,serial";
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reg = <0x40018000 0x1000>;
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};
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uart7: serial@4001C000 {
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compatible = "nxp,serial";
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reg = <0x4001C000 0x1000>;
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};
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rtc@40024000 {
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compatible = "nxp,lpc3220-rtc";
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reg = <0x40024000 0x1000>;
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interrupts = <0x34 0>;
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};
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gpio: gpio@40028000 {
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compatible = "nxp,lpc3220-gpio";
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reg = <0x40028000 0x1000>;
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/* create a private address space for enumeration */
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#address-cells = <1>;
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#size-cells = <0>;
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gpio_p0: gpio-bank@0 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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};
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gpio_p1: gpio-bank@1 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <1>;
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};
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gpio_p2: gpio-bank@2 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <2>;
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};
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gpio_p3: gpio-bank@3 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <3>;
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};
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gpi_p3: gpio-bank@4 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <4>;
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};
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gpo_p3: gpio-bank@5 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <5>;
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};
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};
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watchdog@4003C000 {
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compatible = "nxp,pnx4008-wdt";
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reg = <0x4003C000 0x1000>;
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};
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/*
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* TSC vs. ADC: Since those two share the same
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* hardware, you need to choose from one of the
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* following two and do 'status = "okay";' for one of
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* them
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*/
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adc@40048000 {
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compatible = "nxp,lpc3220-adc";
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reg = <0x40048000 0x1000>;
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interrupts = <0x27 0>;
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status = "disable";
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};
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tsc@40048000 {
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compatible = "nxp,lpc3220-tsc";
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reg = <0x40048000 0x1000>;
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interrupts = <0x27 0>;
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status = "disable";
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};
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key@40050000 {
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compatible = "nxp,lpc3220-key";
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reg = <0x40050000 0x1000>;
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};
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};
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};
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};
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145
arch/arm/boot/dts/phy3250.dts
Normal file
145
arch/arm/boot/dts/phy3250.dts
Normal file
@ -0,0 +1,145 @@
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/*
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* PHYTEC phyCORE-LPC3250 board
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*
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* Copyright 2012 Roland Stigge <stigge@antcom.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "lpc32xx.dtsi"
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/ {
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model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
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compatible = "phytec,phy3250", "nxp,lpc3250";
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#address-cells = <1>;
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#size-cells = <1>;
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memory {
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device_type = "memory";
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reg = <0 0x4000000>;
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};
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ahb {
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mac: ethernet@31060000 {
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phy-mode = "rmii";
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use-iram;
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};
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/* Here, choose exactly one from: ohci, usbd */
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ohci@31020000 {
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transceiver = <&isp1301>;
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status = "okay";
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};
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/*
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usbd@31020000 {
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transceiver = <&isp1301>;
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status = "okay";
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};
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*/
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clcd@31040000 {
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status = "okay";
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};
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/* 64MB Flash via SLC NAND controller */
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slc: flash@20020000 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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mtd0@00000000 {
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label = "phy3250-boot";
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reg = <0x00000000 0x00064000>;
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read-only;
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};
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mtd1@00064000 {
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label = "phy3250-uboot";
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reg = <0x00064000 0x00190000>;
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read-only;
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};
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mtd2@001f4000 {
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label = "phy3250-ubt-prms";
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reg = <0x001f4000 0x00010000>;
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};
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mtd3@00204000 {
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label = "phy3250-kernel";
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reg = <0x00204000 0x00400000>;
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};
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mtd4@00604000 {
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label = "phy3250-rootfs";
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reg = <0x00604000 0x039fc000>;
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};
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};
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apb {
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i2c1: i2c@400A0000 {
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clock-frequency = <100000>;
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pcf8563: rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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uda1380: uda1380@18 {
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compatible = "nxp,uda1380";
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reg = <0x18>;
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power-gpio = <&gpio 0x59 0>;
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reset-gpio = <&gpio 0x51 0>;
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dac-clk = "wspll";
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};
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};
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i2c2: i2c@400A8000 {
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clock-frequency = <100000>;
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};
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i2cusb: i2c@31020300 {
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clock-frequency = <100000>;
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isp1301: usb-transceiver@2c {
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compatible = "nxp,isp1301";
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reg = <0x2c>;
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};
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};
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ssp0: ssp@20084000 {
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eeprom: at25@0 {
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compatible = "atmel,at25";
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};
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};
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};
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fab {
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tsc@40048000 {
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status = "okay";
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led0 {
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gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */
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linux,default-trigger = "heartbeat";
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default-state = "off";
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};
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led1 {
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gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */
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linux,default-trigger = "timer";
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default-state = "off";
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};
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};
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};
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