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ath9k: fix few register offsets for AR9330
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -625,11 +625,11 @@
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#define AR_PHY_65NM_CH2_RXTX1 0x16900
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#define AR_PHY_65NM_CH2_RXTX2 0x16904
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#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
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#define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : 0x16284)
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#define AR_CH0_TOP2_XPABIASLVL 0xf000
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#define AR_CH0_TOP2_XPABIASLVL_S 12
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#define AR_CH0_XTAL (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
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#define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : 0x16290)
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#define AR_CH0_XTAL_CAPINDAC 0x7f000000
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#define AR_CH0_XTAL_CAPINDAC_S 24
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#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
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