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clk: qcom: add parent map for regmap mux
Currently the driver assumes the register configuration value is identical to its index in the parent map. This patch adds the parent map field in regmap mux clock node which contains the mapping of parent index with actual register configuration value. If regmap node contains this parent map then the configuration value will be taken from this parent map instead of simply writing the index value. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -25,16 +25,6 @@ struct freq_tbl {
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u16 n;
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};
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/**
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* struct parent_map - map table for PLL source select configuration values
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* @src: source PLL
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* @cfg: configuration value
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*/
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struct parent_map {
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u8 src;
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u8 cfg;
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};
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/**
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* struct mn - M/N:D counter
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* @mnctr_en_bit: bit to enable mn counter
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@ -35,6 +35,9 @@ static u8 mux_get_parent(struct clk_hw *hw)
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val >>= mux->shift;
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val &= mask;
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if (mux->parent_map)
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return qcom_find_src_index(hw, mux->parent_map, val);
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return val;
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}
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@ -45,6 +48,9 @@ static int mux_set_parent(struct clk_hw *hw, u8 index)
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unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
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unsigned int val;
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if (mux->parent_map)
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index = mux->parent_map[index].cfg;
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val = index;
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val <<= mux->shift;
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@ -16,11 +16,13 @@
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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#include "common.h"
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struct clk_regmap_mux {
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u32 reg;
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u32 shift;
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u32 width;
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const struct parent_map *parent_map;
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struct clk_regmap clkr;
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};
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@ -20,7 +20,6 @@ struct qcom_reset_map;
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struct regmap;
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struct freq_tbl;
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struct clk_hw;
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struct parent_map;
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#define PLL_LOCK_COUNT_SHIFT 8
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#define PLL_LOCK_COUNT_MASK 0x3f
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@ -39,6 +38,16 @@ struct qcom_cc_desc {
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size_t num_gdscs;
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};
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/**
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* struct parent_map - map table for source select configuration values
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* @src: source
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* @cfg: configuration value
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*/
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struct parent_map {
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u8 src;
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u8 cfg;
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};
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extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
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unsigned long rate);
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extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
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