korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-16 16:54:20 +08:00
Code Issues Packages Projects Releases Wiki Activity

[SCSI] bfa: fix chip and memory initialization

Browse Source 
Clear PSS memory reset that is set as part of power-on-reset (pci reset).
Complete PMM memory reset before BISTR start. Clear EDRAM BISTR start bit
after fixed delay. BISTR DONE bit status is not getting set. Use a fixed
1ms delay for BISTR now. Expose PMM IT memory definitions to host.

Signed-off-by: Jing Huang <huangj@brocade.com>
Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
Jing Huang 2010-07-08 19:54:39 -07:00 committed by James Bottomley
parent 9aeb6802dd
commit df2a52a6c8
2 changed files with 28 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/scsi/bfa/bfa_ioc_ct.c
View File

@ -376,10 +376,35 @@ bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc)
bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
__APP_PLL_425_ENABLE);
/**
* PSS memory reset is asserted at power-on-reset. Need to clear
* this before running EDRAM BISTR
*/
if (ioc->cna) {
bfa_reg_write((rb + PMM_1T_RESET_REG_P0), __PMM_1T_RESET_P);
bfa_reg_write((rb + PMM_1T_RESET_REG_P1), __PMM_1T_RESET_P);
}
r32 = bfa_reg_read((rb + PSS_CTL_REG));
r32 &= ~__PSS_LMEM_RESET;
bfa_reg_write((rb + PSS_CTL_REG), r32);
bfa_os_udelay(1000);
if (ioc->cna) {
bfa_reg_write((rb + PMM_1T_RESET_REG_P0), 0);
bfa_reg_write((rb + PMM_1T_RESET_REG_P1), 0);
}
bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START);
bfa_os_udelay(1000);
r32 = bfa_reg_read((rb + MBIST_STAT_REG));
bfa_trc(ioc, r32);
/**
* Clear BISTR
*/
bfa_reg_write((rb + MBIST_CTL_REG), 0);
/*
* release semaphore.
*/

3
drivers/scsi/bfa/include/bfi/bfi_ctreg.h
View File

@ -455,6 +455,9 @@ enum {
#define __PSS_LPU0_RAM_ERR 0x00000001
#define ERR_SET_REG 0x00018818
#define __PSS_ERR_STATUS_SET 0x003fffff
#define PMM_1T_RESET_REG_P0 0x0002381c
#define __PMM_1T_RESET_P 0x00000001
#define PMM_1T_RESET_REG_P1 0x00023c1c
#define HQM_QSET0_RXQ_DRBL_P0 0x00038000
#define __RXQ0_ADD_VECTORS_P 0x80000000
#define __RXQ0_STOP_P 0x40000000