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iommu/arm-smmu: Report IOMMU_CAP_CACHE_COHERENCY better
Assuming that any SMMU can enforce coherency for any device is clearly nonsense. Although technically even a single SMMU instance can be wired up to only be capable of emitting coherent traffic for some of the devices it translates, it's a fairly realistic approximation that if the SMMU's pagetable walker is wired up to a coherent interconnect then all its translation units probably are too, and conversely that lack of coherent table walks implies a non-coherent system in general. Either way it's still less inaccurate than what we've been claiming so far. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/106c9741415f0b6358c72d53ae9c78c553a2b45c.1660574547.git.robin.murphy@arm.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -1994,9 +1994,12 @@ static const struct iommu_flush_ops arm_smmu_flush_ops = {
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/* IOMMU API */
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static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap)
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{
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struct arm_smmu_master *master = dev_iommu_priv_get(dev);
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switch (cap) {
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case IOMMU_CAP_CACHE_COHERENCY:
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return true;
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/* Assume that a coherent TCU implies coherent TBUs */
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return master->smmu->features & ARM_SMMU_FEAT_COHERENCY;
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case IOMMU_CAP_NOEXEC:
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return true;
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default:
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@ -1332,13 +1332,12 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
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static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap)
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{
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struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev);
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switch (cap) {
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case IOMMU_CAP_CACHE_COHERENCY:
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/*
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* Return true here as the SMMU can always send out coherent
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* requests.
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*/
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return true;
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/* Assume that a coherent TCU implies coherent TBUs */
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return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK;
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case IOMMU_CAP_NOEXEC:
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return true;
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default:
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