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clk: tegra: Add Tegra210 CSI TPG clock gate

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Tegra210 CSI hardware internally uses PLLD for internal test pattern
generator logic.

PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD
out to CSI during TPG mode.

This patch adds this CSI TPG clock gate to Tegra210 clock driver
to allow Tegra video driver to ungate CSI TPG clock during TPG mode
and gate during non TPG mode.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sowjanya Komatineni 2020-05-04 19:31:55 -07:00 committed by Thierry Reding
parent 4232985441
commit dec396322d
1 changed files with 7 additions and 0 deletions
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7
drivers/clk/tegra/clk-tegra210.c
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@ -3076,6 +3076,13 @@ static __init void tegra210_periph_clk_init(struct device_node *np,
periph_clk_enb_refcnt);
clks[TEGRA210_CLK_DSIB] = clk;
/* csi_tpg */
clk = clk_register_gate(NULL, "csi_tpg", "pll_d",
CLK_SET_RATE_PARENT, clk_base + PLLD_BASE,
23, 0, &pll_d_lock);
clk_register_clkdev(clk, "csi_tpg", NULL);
clks[TEGRA210_CLK_CSI_TPG] = clk;
/* la */
clk = tegra_clk_register_periph("la", la_parents,
ARRAY_SIZE(la_parents), &tegra210_la, clk_base,