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Samsung cpufreq driver updates for v4.3
- remove exynos4 SoCs and exynos5250 specific cpufreq driver support and unselectable rule for arm-exynos-cpufreq.o because of supporting generic cpufreq driver for the exynos SoCs * Note this is depending on tags/samsung-clk-driver, tags/samsung-soc and tags/samsung-late-dt -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJVzOBxAAoJEA0Cl+kVi2xq0N4P/2PhL646YQWMUfGIl6PRZhMX Ju5VfxvCniM8+8ya5gMKANDZcq118R4KSn0NOUrCIFt0tJVdLgDcuxIzgIvXd4EN zmncOTXFJZRplvAoy2EY4vNoCyTg03ogSiQkjaD/ZpfCkpjRNZwiUmIilATFEiBp fbAB7Lm8cNmxm0UiWTUAMyIzI7b0olvKzY+kPXfKRfIJ/1HPXy63zmfHpzfDmvSQ RNmbqKFaXW96jt6lQyPyR70kPDKAzP3atyx5io6I1KZjsB86JbSQAdQ/9nGKe0ij 4+BDNSoKcSSubgpA3pfr8Aotu876e0yJ1hdbkEPEs8lvOp3sNgPAMAXPd2ZfY8Jw Uc+VxWi+ZyGqP6/dsQS1pGxx+aW93a0xtQ7+JVsfNsB84JQpinZ2LKTCNEPL8/5z G8IX2mAMSRI7hHvzpAkxmSybPlI1h6gpHG8qnIB+vpJJAgIDspG+iO8z1I1XAQSK dFPRa1PlzeDBTVMHQHdIE6UKiKY2UGqztrnmEgVRriV/c5FICPxUfAKBrxoGI4/4 Xcjhxdv+PoJTmpEyshjxkRe2Ehjl2ypM3AgF9IHEQ+g7CgcEblpsYfAVsY6waQuY 6KKaV1+iiJ+cVvWIDSXEZFUl6nJxpFCXpwz9xhWWSm64UAMKY5qjeMij5znX/Kb4 SOB77brJudjg71Luf4Io =myzK -----END PGP SIGNATURE----- Merge tag 'samsung-late-cpufreq-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/late Samsung cpufreq driver updates for v4.3 - remove exynos4 SoCs and exynos5250 specific cpufreq driver support and unselectable rule for arm-exynos-cpufreq.o because of supporting generic cpufreq driver for the exynos SoCs * Note this is depending on tags/samsung-clk-driver, tags/samsung-soc and tags/samsung-late-dt * tag 'samsung-late-cpufreq-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: cpufreq: exynos: Remove unselectable rule for arm-exynos-cpufreq.o cpufreq: exynos: remove Exynos4x12 specific cpufreq driver support cpufreq: exynos: remove exynos5250 specific cpufreq driver support Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
deb14362a5
@ -24,55 +24,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
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This add the CPUfreq driver support for Versatile Express
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big.LITTLE platforms using SPC for power management.
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config ARM_EXYNOS_CPUFREQ
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tristate "SAMSUNG EXYNOS CPUfreq Driver"
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depends on CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412 || SOC_EXYNOS5250
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depends on THERMAL
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help
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This adds the CPUFreq driver for Samsung EXYNOS platforms.
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Supported SoC versions are:
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Exynos4210, Exynos4212, Exynos4412, and Exynos5250.
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If in doubt, say N.
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config ARM_EXYNOS4X12_CPUFREQ
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bool "SAMSUNG EXYNOS4x12"
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depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
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depends on ARM_EXYNOS_CPUFREQ
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default y
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help
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This adds the CPUFreq driver for Samsung EXYNOS4X12
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SoC (EXYNOS4212 or EXYNOS4412).
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If in doubt, say N.
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config ARM_EXYNOS5250_CPUFREQ
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bool "SAMSUNG EXYNOS5250"
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depends on SOC_EXYNOS5250
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depends on ARM_EXYNOS_CPUFREQ
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default y
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help
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This adds the CPUFreq driver for Samsung EXYNOS5250
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SoC.
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If in doubt, say N.
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config ARM_EXYNOS_CPU_FREQ_BOOST_SW
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bool "EXYNOS Frequency Overclocking - Software"
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depends on ARM_EXYNOS_CPUFREQ && THERMAL
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select CPU_FREQ_BOOST_SW
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select EXYNOS_THERMAL
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help
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This driver supports software managed overclocking (BOOST).
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It allows usage of special frequencies for Samsung Exynos
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processors if thermal conditions are appropriate.
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It requires, for safe operation, thermal framework with properly
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defined trip points.
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If in doubt, say N.
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config ARM_EXYNOS5440_CPUFREQ
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tristate "SAMSUNG EXYNOS5440"
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depends on SOC_EXYNOS5440
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@ -52,10 +52,6 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o
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obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
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obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += arm-exynos-cpufreq.o
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arm-exynos-cpufreq-y := exynos-cpufreq.o
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arm-exynos-cpufreq-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
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arm-exynos-cpufreq-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
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obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
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obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ) += hisi-acpu-cpufreq.o
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@ -1,237 +0,0 @@
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/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - CPU frequency scaling support for EXYNOS series
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/regulator/consumer.h>
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#include <linux/cpufreq.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/cpu_cooling.h>
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#include <linux/cpu.h>
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#include "exynos-cpufreq.h"
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static struct exynos_dvfs_info *exynos_info;
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static struct thermal_cooling_device *cdev;
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static struct regulator *arm_regulator;
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static unsigned int locking_frequency;
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static int exynos_cpufreq_get_index(unsigned int freq)
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{
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struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
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struct cpufreq_frequency_table *pos;
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cpufreq_for_each_entry(pos, freq_table)
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if (pos->frequency == freq)
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break;
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if (pos->frequency == CPUFREQ_TABLE_END)
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return -EINVAL;
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return pos - freq_table;
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}
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static int exynos_cpufreq_scale(unsigned int target_freq)
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{
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struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
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unsigned int *volt_table = exynos_info->volt_table;
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struct cpufreq_policy *policy = cpufreq_cpu_get(0);
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unsigned int arm_volt, safe_arm_volt = 0;
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unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
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struct device *dev = exynos_info->dev;
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unsigned int old_freq;
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int index, old_index;
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int ret = 0;
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old_freq = policy->cur;
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/*
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* The policy max have been changed so that we cannot get proper
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* old_index with cpufreq_frequency_table_target(). Thus, ignore
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* policy and get the index from the raw frequency table.
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*/
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old_index = exynos_cpufreq_get_index(old_freq);
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if (old_index < 0) {
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ret = old_index;
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goto out;
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}
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index = exynos_cpufreq_get_index(target_freq);
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if (index < 0) {
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ret = index;
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goto out;
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}
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/*
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* ARM clock source will be changed APLL to MPLL temporary
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* To support this level, need to control regulator for
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* required voltage level
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*/
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if (exynos_info->need_apll_change != NULL) {
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if (exynos_info->need_apll_change(old_index, index) &&
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(freq_table[index].frequency < mpll_freq_khz) &&
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(freq_table[old_index].frequency < mpll_freq_khz))
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safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
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}
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arm_volt = volt_table[index];
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/* When the new frequency is higher than current frequency */
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if ((target_freq > old_freq) && !safe_arm_volt) {
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/* Firstly, voltage up to increase frequency */
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ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
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if (ret) {
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dev_err(dev, "failed to set cpu voltage to %d\n",
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arm_volt);
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return ret;
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}
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}
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if (safe_arm_volt) {
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ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
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safe_arm_volt);
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if (ret) {
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dev_err(dev, "failed to set cpu voltage to %d\n",
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safe_arm_volt);
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return ret;
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}
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}
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exynos_info->set_freq(old_index, index);
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/* When the new frequency is lower than current frequency */
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if ((target_freq < old_freq) ||
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((target_freq > old_freq) && safe_arm_volt)) {
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/* down the voltage after frequency change */
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ret = regulator_set_voltage(arm_regulator, arm_volt,
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arm_volt);
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if (ret) {
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dev_err(dev, "failed to set cpu voltage to %d\n",
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arm_volt);
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goto out;
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}
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}
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out:
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cpufreq_cpu_put(policy);
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return ret;
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}
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static int exynos_target(struct cpufreq_policy *policy, unsigned int index)
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{
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return exynos_cpufreq_scale(exynos_info->freq_table[index].frequency);
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}
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static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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policy->clk = exynos_info->cpu_clk;
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policy->suspend_freq = locking_frequency;
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return cpufreq_generic_init(policy, exynos_info->freq_table, 100000);
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}
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static struct cpufreq_driver exynos_driver = {
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.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = exynos_target,
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.get = cpufreq_generic_get,
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.init = exynos_cpufreq_cpu_init,
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.name = "exynos_cpufreq",
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.attr = cpufreq_generic_attr,
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#ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW
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.boost_supported = true,
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#endif
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#ifdef CONFIG_PM
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.suspend = cpufreq_generic_suspend,
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#endif
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};
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static int exynos_cpufreq_probe(struct platform_device *pdev)
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{
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struct device_node *cpu0;
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int ret = -EINVAL;
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exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL);
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if (!exynos_info)
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return -ENOMEM;
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exynos_info->dev = &pdev->dev;
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if (of_machine_is_compatible("samsung,exynos4212")) {
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exynos_info->type = EXYNOS_SOC_4212;
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ret = exynos4x12_cpufreq_init(exynos_info);
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} else if (of_machine_is_compatible("samsung,exynos4412")) {
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exynos_info->type = EXYNOS_SOC_4412;
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ret = exynos4x12_cpufreq_init(exynos_info);
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} else if (of_machine_is_compatible("samsung,exynos5250")) {
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exynos_info->type = EXYNOS_SOC_5250;
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ret = exynos5250_cpufreq_init(exynos_info);
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} else {
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pr_err("%s: Unknown SoC type\n", __func__);
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return -ENODEV;
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}
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if (ret)
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goto err_vdd_arm;
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if (exynos_info->set_freq == NULL) {
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dev_err(&pdev->dev, "No set_freq function (ERR)\n");
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goto err_vdd_arm;
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}
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arm_regulator = regulator_get(NULL, "vdd_arm");
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if (IS_ERR(arm_regulator)) {
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dev_err(&pdev->dev, "failed to get resource vdd_arm\n");
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goto err_vdd_arm;
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}
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/* Done here as we want to capture boot frequency */
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locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000;
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ret = cpufreq_register_driver(&exynos_driver);
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if (ret)
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goto err_cpufreq_reg;
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cpu0 = of_get_cpu_node(0, NULL);
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if (!cpu0) {
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pr_err("failed to find cpu0 node\n");
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return 0;
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}
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if (of_find_property(cpu0, "#cooling-cells", NULL)) {
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cdev = of_cpufreq_cooling_register(cpu0,
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cpu_present_mask);
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if (IS_ERR(cdev))
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pr_err("running cpufreq without cooling device: %ld\n",
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PTR_ERR(cdev));
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}
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return 0;
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err_cpufreq_reg:
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dev_err(&pdev->dev, "failed to register cpufreq driver\n");
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regulator_put(arm_regulator);
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err_vdd_arm:
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kfree(exynos_info);
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return -EINVAL;
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}
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static struct platform_driver exynos_cpufreq_platdrv = {
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.driver = {
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.name = "exynos-cpufreq",
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},
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.probe = exynos_cpufreq_probe,
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};
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module_platform_driver(exynos_cpufreq_platdrv);
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@ -1,89 +0,0 @@
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/*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - CPUFreq support
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
|
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*/
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enum cpufreq_level_index {
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L0, L1, L2, L3, L4,
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L5, L6, L7, L8, L9,
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L10, L11, L12, L13, L14,
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L15, L16, L17, L18, L19,
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L20,
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};
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enum exynos_soc_type {
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EXYNOS_SOC_4212,
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EXYNOS_SOC_4412,
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EXYNOS_SOC_5250,
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};
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#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
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{ \
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.freq = (f) * 1000, \
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.clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \
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(a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \
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.clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
|
||||
.mps = ((m) << 16 | (p) << 8 | (s)), \
|
||||
}
|
||||
|
||||
struct apll_freq {
|
||||
unsigned int freq;
|
||||
u32 clk_div_cpu0;
|
||||
u32 clk_div_cpu1;
|
||||
u32 mps;
|
||||
};
|
||||
|
||||
struct exynos_dvfs_info {
|
||||
enum exynos_soc_type type;
|
||||
struct device *dev;
|
||||
unsigned long mpll_freq_khz;
|
||||
unsigned int pll_safe_idx;
|
||||
struct clk *cpu_clk;
|
||||
unsigned int *volt_table;
|
||||
struct cpufreq_frequency_table *freq_table;
|
||||
void (*set_freq)(unsigned int, unsigned int);
|
||||
bool (*need_apll_change)(unsigned int, unsigned int);
|
||||
void __iomem *cmu_regs;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARM_EXYNOS4X12_CPUFREQ
|
||||
extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
|
||||
#else
|
||||
static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ
|
||||
extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
|
||||
#else
|
||||
static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
#endif
|
||||
|
||||
#define EXYNOS4_CLKSRC_CPU 0x14200
|
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#define EXYNOS4_CLKMUX_STATCPU 0x14400
|
||||
|
||||
#define EXYNOS4_CLKDIV_CPU 0x14500
|
||||
#define EXYNOS4_CLKDIV_CPU1 0x14504
|
||||
#define EXYNOS4_CLKDIV_STATCPU 0x14600
|
||||
#define EXYNOS4_CLKDIV_STATCPU1 0x14604
|
||||
|
||||
#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
|
||||
#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
|
||||
|
||||
#define EXYNOS5_APLL_LOCK 0x00000
|
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#define EXYNOS5_APLL_CON0 0x00100
|
||||
#define EXYNOS5_CLKMUX_STATCPU 0x00400
|
||||
#define EXYNOS5_CLKDIV_CPU0 0x00500
|
||||
#define EXYNOS5_CLKDIV_CPU1 0x00504
|
||||
#define EXYNOS5_CLKDIV_STATCPU0 0x00600
|
||||
#define EXYNOS5_CLKDIV_STATCPU1 0x00604
|
||||
@ -1,236 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4X12 - CPU frequency scaling support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "exynos-cpufreq.h"
|
||||
|
||||
static struct clk *cpu_clk;
|
||||
static struct clk *moutcore;
|
||||
static struct clk *mout_mpll;
|
||||
static struct clk *mout_apll;
|
||||
static struct exynos_dvfs_info *cpufreq;
|
||||
|
||||
static unsigned int exynos4x12_volt_table[] = {
|
||||
1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
|
||||
1000000, 987500, 975000, 950000, 925000, 900000, 900000
|
||||
};
|
||||
|
||||
static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
|
||||
{CPUFREQ_BOOST_FREQ, L0, 1500 * 1000},
|
||||
{0, L1, 1400 * 1000},
|
||||
{0, L2, 1300 * 1000},
|
||||
{0, L3, 1200 * 1000},
|
||||
{0, L4, 1100 * 1000},
|
||||
{0, L5, 1000 * 1000},
|
||||
{0, L6, 900 * 1000},
|
||||
{0, L7, 800 * 1000},
|
||||
{0, L8, 700 * 1000},
|
||||
{0, L9, 600 * 1000},
|
||||
{0, L10, 500 * 1000},
|
||||
{0, L11, 400 * 1000},
|
||||
{0, L12, 300 * 1000},
|
||||
{0, L13, 200 * 1000},
|
||||
{0, 0, CPUFREQ_TABLE_END},
|
||||
};
|
||||
|
||||
static struct apll_freq *apll_freq_4x12;
|
||||
|
||||
static struct apll_freq apll_freq_4212[] = {
|
||||
/*
|
||||
* values:
|
||||
* freq
|
||||
* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
|
||||
* clock divider for COPY, HPM, RESERVED
|
||||
* PLL M, P, S
|
||||
*/
|
||||
APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
|
||||
APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
|
||||
APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
|
||||
APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
|
||||
APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
|
||||
APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
|
||||
APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
|
||||
APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
|
||||
APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
|
||||
APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
|
||||
APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
|
||||
APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
|
||||
APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
|
||||
APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
|
||||
};
|
||||
|
||||
static struct apll_freq apll_freq_4412[] = {
|
||||
/*
|
||||
* values:
|
||||
* freq
|
||||
* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
|
||||
* clock divider for COPY, HPM, CORES
|
||||
* PLL M, P, S
|
||||
*/
|
||||
APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
|
||||
APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
|
||||
APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
|
||||
APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
|
||||
APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
|
||||
APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
|
||||
APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
|
||||
APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
|
||||
APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
|
||||
APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
|
||||
APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
|
||||
APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
|
||||
APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
|
||||
APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
|
||||
};
|
||||
|
||||
static void exynos4x12_set_clkdiv(unsigned int div_index)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
/* Change Divider - CPU0 */
|
||||
|
||||
tmp = apll_freq_4x12[div_index].clk_div_cpu0;
|
||||
|
||||
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
|
||||
|
||||
while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
|
||||
& 0x11111111)
|
||||
cpu_relax();
|
||||
|
||||
/* Change Divider - CPU1 */
|
||||
tmp = apll_freq_4x12[div_index].clk_div_cpu1;
|
||||
|
||||
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
|
||||
|
||||
do {
|
||||
cpu_relax();
|
||||
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
|
||||
} while (tmp != 0x0);
|
||||
}
|
||||
|
||||
static void exynos4x12_set_apll(unsigned int index)
|
||||
{
|
||||
unsigned int tmp, freq = apll_freq_4x12[index].freq;
|
||||
|
||||
/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
|
||||
clk_set_parent(moutcore, mout_mpll);
|
||||
|
||||
do {
|
||||
cpu_relax();
|
||||
tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
|
||||
>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
|
||||
tmp &= 0x7;
|
||||
} while (tmp != 0x2);
|
||||
|
||||
clk_set_rate(mout_apll, freq * 1000);
|
||||
|
||||
/* MUX_CORE_SEL = APLL */
|
||||
clk_set_parent(moutcore, mout_apll);
|
||||
|
||||
do {
|
||||
cpu_relax();
|
||||
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
|
||||
tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
|
||||
} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
|
||||
}
|
||||
|
||||
static void exynos4x12_set_frequency(unsigned int old_index,
|
||||
unsigned int new_index)
|
||||
{
|
||||
if (old_index > new_index) {
|
||||
exynos4x12_set_clkdiv(new_index);
|
||||
exynos4x12_set_apll(new_index);
|
||||
} else if (old_index < new_index) {
|
||||
exynos4x12_set_apll(new_index);
|
||||
exynos4x12_set_clkdiv(new_index);
|
||||
}
|
||||
}
|
||||
|
||||
int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned long rate;
|
||||
|
||||
/*
|
||||
* HACK: This is a temporary workaround to get access to clock
|
||||
* controller registers directly and remove static mappings and
|
||||
* dependencies on platform headers. It is necessary to enable
|
||||
* Exynos multi-platform support and will be removed together with
|
||||
* this whole driver as soon as Exynos gets migrated to use
|
||||
* cpufreq-dt driver.
|
||||
*/
|
||||
np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
|
||||
if (!np) {
|
||||
pr_err("%s: failed to find clock controller DT node\n",
|
||||
__func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
info->cmu_regs = of_iomap(np, 0);
|
||||
if (!info->cmu_regs) {
|
||||
pr_err("%s: failed to map CMU registers\n", __func__);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
cpu_clk = clk_get(NULL, "armclk");
|
||||
if (IS_ERR(cpu_clk))
|
||||
return PTR_ERR(cpu_clk);
|
||||
|
||||
moutcore = clk_get(NULL, "moutcore");
|
||||
if (IS_ERR(moutcore))
|
||||
goto err_moutcore;
|
||||
|
||||
mout_mpll = clk_get(NULL, "mout_mpll");
|
||||
if (IS_ERR(mout_mpll))
|
||||
goto err_mout_mpll;
|
||||
|
||||
rate = clk_get_rate(mout_mpll) / 1000;
|
||||
|
||||
mout_apll = clk_get(NULL, "mout_apll");
|
||||
if (IS_ERR(mout_apll))
|
||||
goto err_mout_apll;
|
||||
|
||||
if (info->type == EXYNOS_SOC_4212)
|
||||
apll_freq_4x12 = apll_freq_4212;
|
||||
else
|
||||
apll_freq_4x12 = apll_freq_4412;
|
||||
|
||||
info->mpll_freq_khz = rate;
|
||||
/* 800Mhz */
|
||||
info->pll_safe_idx = L7;
|
||||
info->cpu_clk = cpu_clk;
|
||||
info->volt_table = exynos4x12_volt_table;
|
||||
info->freq_table = exynos4x12_freq_table;
|
||||
info->set_freq = exynos4x12_set_frequency;
|
||||
|
||||
cpufreq = info;
|
||||
|
||||
return 0;
|
||||
|
||||
err_mout_apll:
|
||||
clk_put(mout_mpll);
|
||||
err_mout_mpll:
|
||||
clk_put(moutcore);
|
||||
err_moutcore:
|
||||
clk_put(cpu_clk);
|
||||
|
||||
pr_debug("%s: failed initialization\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -1,210 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS5250 - CPU frequency scaling support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "exynos-cpufreq.h"
|
||||
|
||||
static struct clk *cpu_clk;
|
||||
static struct clk *moutcore;
|
||||
static struct clk *mout_mpll;
|
||||
static struct clk *mout_apll;
|
||||
static struct exynos_dvfs_info *cpufreq;
|
||||
|
||||
static unsigned int exynos5250_volt_table[] = {
|
||||
1300000, 1250000, 1225000, 1200000, 1150000,
|
||||
1125000, 1100000, 1075000, 1050000, 1025000,
|
||||
1012500, 1000000, 975000, 950000, 937500,
|
||||
925000
|
||||
};
|
||||
|
||||
static struct cpufreq_frequency_table exynos5250_freq_table[] = {
|
||||
{0, L0, 1700 * 1000},
|
||||
{0, L1, 1600 * 1000},
|
||||
{0, L2, 1500 * 1000},
|
||||
{0, L3, 1400 * 1000},
|
||||
{0, L4, 1300 * 1000},
|
||||
{0, L5, 1200 * 1000},
|
||||
{0, L6, 1100 * 1000},
|
||||
{0, L7, 1000 * 1000},
|
||||
{0, L8, 900 * 1000},
|
||||
{0, L9, 800 * 1000},
|
||||
{0, L10, 700 * 1000},
|
||||
{0, L11, 600 * 1000},
|
||||
{0, L12, 500 * 1000},
|
||||
{0, L13, 400 * 1000},
|
||||
{0, L14, 300 * 1000},
|
||||
{0, L15, 200 * 1000},
|
||||
{0, 0, CPUFREQ_TABLE_END},
|
||||
};
|
||||
|
||||
static struct apll_freq apll_freq_5250[] = {
|
||||
/*
|
||||
* values:
|
||||
* freq
|
||||
* clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
|
||||
* clock divider for COPY, HPM, RESERVED
|
||||
* PLL M, P, S
|
||||
*/
|
||||
APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
|
||||
APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
|
||||
APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
|
||||
APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
|
||||
APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
|
||||
APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
|
||||
APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
|
||||
APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
|
||||
APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
|
||||
APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
|
||||
APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
|
||||
APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
|
||||
APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
|
||||
APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
|
||||
APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
|
||||
APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
|
||||
};
|
||||
|
||||
static void set_clkdiv(unsigned int div_index)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
/* Change Divider - CPU0 */
|
||||
|
||||
tmp = apll_freq_5250[div_index].clk_div_cpu0;
|
||||
|
||||
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0);
|
||||
|
||||
while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0)
|
||||
& 0x11111111)
|
||||
cpu_relax();
|
||||
|
||||
/* Change Divider - CPU1 */
|
||||
tmp = apll_freq_5250[div_index].clk_div_cpu1;
|
||||
|
||||
__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1);
|
||||
|
||||
while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
static void set_apll(unsigned int index)
|
||||
{
|
||||
unsigned int tmp;
|
||||
unsigned int freq = apll_freq_5250[index].freq;
|
||||
|
||||
/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
|
||||
clk_set_parent(moutcore, mout_mpll);
|
||||
|
||||
do {
|
||||
cpu_relax();
|
||||
tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU)
|
||||
>> 16);
|
||||
tmp &= 0x7;
|
||||
} while (tmp != 0x2);
|
||||
|
||||
clk_set_rate(mout_apll, freq * 1000);
|
||||
|
||||
/* MUX_CORE_SEL = APLL */
|
||||
clk_set_parent(moutcore, mout_apll);
|
||||
|
||||
do {
|
||||
cpu_relax();
|
||||
tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU);
|
||||
tmp &= (0x7 << 16);
|
||||
} while (tmp != (0x1 << 16));
|
||||
}
|
||||
|
||||
static void exynos5250_set_frequency(unsigned int old_index,
|
||||
unsigned int new_index)
|
||||
{
|
||||
if (old_index > new_index) {
|
||||
set_clkdiv(new_index);
|
||||
set_apll(new_index);
|
||||
} else if (old_index < new_index) {
|
||||
set_apll(new_index);
|
||||
set_clkdiv(new_index);
|
||||
}
|
||||
}
|
||||
|
||||
int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned long rate;
|
||||
|
||||
/*
|
||||
* HACK: This is a temporary workaround to get access to clock
|
||||
* controller registers directly and remove static mappings and
|
||||
* dependencies on platform headers. It is necessary to enable
|
||||
* Exynos multi-platform support and will be removed together with
|
||||
* this whole driver as soon as Exynos gets migrated to use
|
||||
* cpufreq-dt driver.
|
||||
*/
|
||||
np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock");
|
||||
if (!np) {
|
||||
pr_err("%s: failed to find clock controller DT node\n",
|
||||
__func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
info->cmu_regs = of_iomap(np, 0);
|
||||
if (!info->cmu_regs) {
|
||||
pr_err("%s: failed to map CMU registers\n", __func__);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
cpu_clk = clk_get(NULL, "armclk");
|
||||
if (IS_ERR(cpu_clk))
|
||||
return PTR_ERR(cpu_clk);
|
||||
|
||||
moutcore = clk_get(NULL, "mout_cpu");
|
||||
if (IS_ERR(moutcore))
|
||||
goto err_moutcore;
|
||||
|
||||
mout_mpll = clk_get(NULL, "mout_mpll");
|
||||
if (IS_ERR(mout_mpll))
|
||||
goto err_mout_mpll;
|
||||
|
||||
rate = clk_get_rate(mout_mpll) / 1000;
|
||||
|
||||
mout_apll = clk_get(NULL, "mout_apll");
|
||||
if (IS_ERR(mout_apll))
|
||||
goto err_mout_apll;
|
||||
|
||||
info->mpll_freq_khz = rate;
|
||||
/* 800Mhz */
|
||||
info->pll_safe_idx = L9;
|
||||
info->cpu_clk = cpu_clk;
|
||||
info->volt_table = exynos5250_volt_table;
|
||||
info->freq_table = exynos5250_freq_table;
|
||||
info->set_freq = exynos5250_set_frequency;
|
||||
|
||||
cpufreq = info;
|
||||
|
||||
return 0;
|
||||
|
||||
err_mout_apll:
|
||||
clk_put(mout_mpll);
|
||||
err_mout_mpll:
|
||||
clk_put(moutcore);
|
||||
err_moutcore:
|
||||
clk_put(cpu_clk);
|
||||
|
||||
pr_err("%s: failed initialization\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user