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Merge branch 'net-stmmac-Some-improvements-and-a-fix'
Jose Abreu says: ==================== net: stmmac: Some improvements and a fix Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
de90573e30
@ -3,6 +3,7 @@ config STMMAC_ETH
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tristate "STMicroelectronics Multi-Gigabit Ethernet driver"
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depends on HAS_IOMEM && HAS_DMA
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select MII
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select PAGE_POOL
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select PHYLINK
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select CRC32
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imply PTP_1588_CLOCK
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@ -252,6 +252,7 @@ struct stmmac_safety_stats {
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#define STMMAC_MAX_COAL_TX_TICK 100000
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#define STMMAC_TX_MAX_FRAMES 256
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#define STMMAC_TX_FRAMES 1
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#define STMMAC_RX_FRAMES 25
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/* Packets types */
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enum packets_types {
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@ -289,18 +289,18 @@ static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
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static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_rx_phy, u32 chan)
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dma_addr_t dma_rx_phy, u32 chan)
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{
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/* Write RX descriptors address */
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writel(dma_rx_phy, ioaddr + EMAC_RX_DESC_LIST);
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writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);
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}
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static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx_phy, u32 chan)
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dma_addr_t dma_tx_phy, u32 chan)
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{
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/* Write TX descriptors address */
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writel(dma_tx_phy, ioaddr + EMAC_TX_DESC_LIST);
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writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST);
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}
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/* sun8i_dwmac_dump_regs() - Dump EMAC address space
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@ -112,18 +112,18 @@ static void dwmac1000_dma_init(void __iomem *ioaddr,
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static void dwmac1000_dma_init_rx(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_rx_phy, u32 chan)
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dma_addr_t dma_rx_phy, u32 chan)
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{
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/* RX descriptor base address list must be written into DMA CSR3 */
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writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR);
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
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}
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static void dwmac1000_dma_init_tx(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx_phy, u32 chan)
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dma_addr_t dma_tx_phy, u32 chan)
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{
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/* TX descriptor base address list must be written into DMA CSR4 */
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writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR);
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
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}
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static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
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@ -31,18 +31,18 @@ static void dwmac100_dma_init(void __iomem *ioaddr,
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static void dwmac100_dma_init_rx(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_rx_phy, u32 chan)
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dma_addr_t dma_rx_phy, u32 chan)
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{
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/* RX descriptor base addr lists must be written into DMA CSR3 */
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writel(dma_rx_phy, ioaddr + DMA_RCV_BASE_ADDR);
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR);
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}
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static void dwmac100_dma_init_tx(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx_phy, u32 chan)
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dma_addr_t dma_tx_phy, u32 chan)
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{
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/* TX descriptor base addr lists must be written into DMA CSR4 */
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writel(dma_tx_phy, ioaddr + DMA_TX_BASE_ADDR);
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR);
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}
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/* Store and Forward capability is not used at all.
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@ -70,7 +70,7 @@ static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_rx_phy, u32 chan)
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dma_addr_t dma_rx_phy, u32 chan)
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{
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u32 value;
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u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
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@ -79,12 +79,12 @@ static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
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value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
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writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
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writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
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}
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static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx_phy, u32 chan)
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dma_addr_t dma_tx_phy, u32 chan)
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{
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u32 value;
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u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
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@ -97,7 +97,7 @@ static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
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writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
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writel(dma_tx_phy, ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
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}
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static void dwmac4_dma_init_channel(void __iomem *ioaddr,
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@ -199,7 +199,9 @@
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#define XGMAC_RxPBL GENMASK(21, 16)
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#define XGMAC_RxPBL_SHIFT 16
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#define XGMAC_RXST BIT(0)
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#define XGMAC_DMA_CH_TxDESC_HADDR(x) (0x00003110 + (0x80 * (x)))
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#define XGMAC_DMA_CH_TxDESC_LADDR(x) (0x00003114 + (0x80 * (x)))
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#define XGMAC_DMA_CH_RxDESC_HADDR(x) (0x00003118 + (0x80 * (x)))
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#define XGMAC_DMA_CH_RxDESC_LADDR(x) (0x0000311c + (0x80 * (x)))
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#define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(x) (0x00003124 + (0x80 * (x)))
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#define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(x) (0x0000312c + (0x80 * (x)))
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@ -44,7 +44,7 @@ static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
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static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_rx_phy, u32 chan)
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dma_addr_t phy, u32 chan)
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{
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u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
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u32 value;
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@ -54,12 +54,13 @@ static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
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value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
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writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
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writel(dma_rx_phy, ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
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writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
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writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
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}
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static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx_phy, u32 chan)
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dma_addr_t phy, u32 chan)
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{
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u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
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u32 value;
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@ -70,7 +71,8 @@ static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
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value |= XGMAC_OSP;
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writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
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writel(dma_tx_phy, ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
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writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
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writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
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}
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static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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@ -150,10 +150,10 @@ struct stmmac_dma_ops {
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struct stmmac_dma_cfg *dma_cfg, u32 chan);
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void (*init_rx_chan)(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_rx_phy, u32 chan);
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dma_addr_t phy, u32 chan);
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void (*init_tx_chan)(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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u32 dma_tx_phy, u32 chan);
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dma_addr_t phy, u32 chan);
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/* Configure the AXI Bus Mode Register */
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void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
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/* Dump DMA registers */
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@ -20,6 +20,7 @@
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#include <linux/ptp_clock_kernel.h>
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#include <linux/net_tstamp.h>
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#include <linux/reset.h>
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#include <net/page_pool.h>
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struct stmmac_resources {
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void __iomem *addr;
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@ -54,13 +55,19 @@ struct stmmac_tx_queue {
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u32 mss;
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};
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struct stmmac_rx_buffer {
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struct page *page;
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dma_addr_t addr;
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};
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struct stmmac_rx_queue {
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u32 rx_count_frames;
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u32 queue_index;
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struct page_pool *page_pool;
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struct stmmac_rx_buffer *buf_pool;
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struct stmmac_priv *priv_data;
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struct dma_extended_desc *dma_erx;
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struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
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struct sk_buff **rx_skbuff;
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dma_addr_t *rx_skbuff_dma;
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unsigned int cur_rx;
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unsigned int dirty_rx;
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u32 rx_zeroc_thresh;
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@ -110,6 +117,7 @@ struct stmmac_priv {
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/* Frequently used values are kept adjacent for cache effect */
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u32 tx_coal_frames;
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u32 tx_coal_timer;
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u32 rx_coal_frames;
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int tx_coalesce;
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int hwts_tx_en;
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@ -701,8 +701,10 @@ static int stmmac_get_coalesce(struct net_device *dev,
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ec->tx_coalesce_usecs = priv->tx_coal_timer;
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ec->tx_max_coalesced_frames = priv->tx_coal_frames;
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if (priv->use_riwt)
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if (priv->use_riwt) {
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ec->rx_max_coalesced_frames = priv->rx_coal_frames;
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ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv);
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}
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return 0;
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}
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@ -715,7 +717,7 @@ static int stmmac_set_coalesce(struct net_device *dev,
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unsigned int rx_riwt;
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/* Check not supported parameters */
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if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) ||
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if ((ec->rx_coalesce_usecs_irq) ||
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(ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) ||
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(ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) ||
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(ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
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@ -749,6 +751,7 @@ static int stmmac_set_coalesce(struct net_device *dev,
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/* Only copy relevant parameters, ignore all others. */
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priv->tx_coal_frames = ec->tx_max_coalesced_frames;
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priv->tx_coal_timer = ec->tx_coalesce_usecs;
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priv->rx_coal_frames = ec->rx_max_coalesced_frames;
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priv->rx_riwt = rx_riwt;
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stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
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@ -1197,26 +1197,14 @@ static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
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int i, gfp_t flags, u32 queue)
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{
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struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
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struct sk_buff *skb;
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struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
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skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
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if (!skb) {
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netdev_err(priv->dev,
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"%s: Rx init fails; skb is NULL\n", __func__);
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buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
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if (!buf->page)
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return -ENOMEM;
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}
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rx_q->rx_skbuff[i] = skb;
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rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
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priv->dma_buf_sz,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
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netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
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dev_kfree_skb_any(skb);
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return -EINVAL;
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}
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stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
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buf->addr = page_pool_get_dma_addr(buf->page);
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stmmac_set_desc_addr(priv, p, buf->addr);
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if (priv->dma_buf_sz == BUF_SIZE_16KiB)
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stmmac_init_desc3(priv, p);
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@ -1232,13 +1220,11 @@ static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
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static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
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{
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struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
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struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
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if (rx_q->rx_skbuff[i]) {
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dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
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priv->dma_buf_sz, DMA_FROM_DEVICE);
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dev_kfree_skb_any(rx_q->rx_skbuff[i]);
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}
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rx_q->rx_skbuff[i] = NULL;
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if (buf->page)
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page_pool_put_page(rx_q->page_pool, buf->page, false);
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buf->page = NULL;
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}
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/**
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@ -1321,10 +1307,6 @@ static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
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queue);
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if (ret)
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goto err_init_rx_buffers;
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netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
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rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
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(unsigned int)rx_q->rx_skbuff_dma[i]);
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}
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rx_q->cur_rx = 0;
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@ -1498,8 +1480,11 @@ static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
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sizeof(struct dma_extended_desc),
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rx_q->dma_erx, rx_q->dma_rx_phy);
|
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kfree(rx_q->rx_skbuff_dma);
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kfree(rx_q->rx_skbuff);
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kfree(rx_q->buf_pool);
|
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if (rx_q->page_pool) {
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page_pool_request_shutdown(rx_q->page_pool);
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page_pool_destroy(rx_q->page_pool);
|
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}
|
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}
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}
|
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@ -1551,20 +1536,29 @@ static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
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/* RX queues buffers and DMA */
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for (queue = 0; queue < rx_count; queue++) {
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struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
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struct page_pool_params pp_params = { 0 };
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rx_q->queue_index = queue;
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rx_q->priv_data = priv;
|
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rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
|
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sizeof(dma_addr_t),
|
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GFP_KERNEL);
|
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if (!rx_q->rx_skbuff_dma)
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goto err_dma;
|
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pp_params.flags = PP_FLAG_DMA_MAP;
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pp_params.pool_size = DMA_RX_SIZE;
|
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pp_params.order = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
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pp_params.nid = dev_to_node(priv->device);
|
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pp_params.dev = priv->device;
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pp_params.dma_dir = DMA_FROM_DEVICE;
|
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rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
|
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sizeof(struct sk_buff *),
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GFP_KERNEL);
|
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if (!rx_q->rx_skbuff)
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rx_q->page_pool = page_pool_create(&pp_params);
|
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if (IS_ERR(rx_q->page_pool)) {
|
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ret = PTR_ERR(rx_q->page_pool);
|
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rx_q->page_pool = NULL;
|
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goto err_dma;
|
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}
|
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|
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rx_q->buf_pool = kmalloc_array(DMA_RX_SIZE,
|
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sizeof(*rx_q->buf_pool),
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GFP_KERNEL);
|
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if (!rx_q->buf_pool)
|
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goto err_dma;
|
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|
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if (priv->extend_desc) {
|
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@ -2268,20 +2262,21 @@ static void stmmac_tx_timer(struct timer_list *t)
|
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}
|
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/**
|
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* stmmac_init_tx_coalesce - init tx mitigation options.
|
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* stmmac_init_coalesce - init mitigation options.
|
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* @priv: driver private structure
|
||||
* Description:
|
||||
* This inits the transmit coalesce parameters: i.e. timer rate,
|
||||
* This inits the coalesce parameters: i.e. timer rate,
|
||||
* timer handler and default threshold used for enabling the
|
||||
* interrupt on completion bit.
|
||||
*/
|
||||
static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
|
||||
static void stmmac_init_coalesce(struct stmmac_priv *priv)
|
||||
{
|
||||
u32 tx_channel_count = priv->plat->tx_queues_to_use;
|
||||
u32 chan;
|
||||
|
||||
priv->tx_coal_frames = STMMAC_TX_FRAMES;
|
||||
priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
|
||||
priv->rx_coal_frames = STMMAC_RX_FRAMES;
|
||||
|
||||
for (chan = 0; chan < tx_channel_count; chan++) {
|
||||
struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
|
||||
@ -2651,7 +2646,7 @@ static int stmmac_open(struct net_device *dev)
|
||||
goto init_error;
|
||||
}
|
||||
|
||||
stmmac_init_tx_coalesce(priv);
|
||||
stmmac_init_coalesce(priv);
|
||||
|
||||
phylink_start(priv->phylink);
|
||||
|
||||
@ -3285,55 +3280,32 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
|
||||
int dirty = stmmac_rx_dirty(priv, queue);
|
||||
unsigned int entry = rx_q->dirty_rx;
|
||||
|
||||
int bfsize = priv->dma_buf_sz;
|
||||
|
||||
while (dirty-- > 0) {
|
||||
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
|
||||
struct dma_desc *p;
|
||||
bool use_rx_wd;
|
||||
|
||||
if (priv->extend_desc)
|
||||
p = (struct dma_desc *)(rx_q->dma_erx + entry);
|
||||
else
|
||||
p = rx_q->dma_rx + entry;
|
||||
|
||||
if (likely(!rx_q->rx_skbuff[entry])) {
|
||||
struct sk_buff *skb;
|
||||
|
||||
skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
|
||||
if (unlikely(!skb)) {
|
||||
/* so for a while no zero-copy! */
|
||||
rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
|
||||
if (unlikely(net_ratelimit()))
|
||||
dev_err(priv->device,
|
||||
"fail to alloc skb entry %d\n",
|
||||
entry);
|
||||
if (!buf->page) {
|
||||
buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
if (!buf->page)
|
||||
break;
|
||||
}
|
||||
|
||||
rx_q->rx_skbuff[entry] = skb;
|
||||
rx_q->rx_skbuff_dma[entry] =
|
||||
dma_map_single(priv->device, skb->data, bfsize,
|
||||
DMA_FROM_DEVICE);
|
||||
if (dma_mapping_error(priv->device,
|
||||
rx_q->rx_skbuff_dma[entry])) {
|
||||
netdev_err(priv->dev, "Rx DMA map failed\n");
|
||||
dev_kfree_skb(skb);
|
||||
break;
|
||||
}
|
||||
|
||||
stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
|
||||
stmmac_refill_desc3(priv, rx_q, p);
|
||||
|
||||
if (rx_q->rx_zeroc_thresh > 0)
|
||||
rx_q->rx_zeroc_thresh--;
|
||||
|
||||
netif_dbg(priv, rx_status, priv->dev,
|
||||
"refill entry #%d\n", entry);
|
||||
}
|
||||
dma_wmb();
|
||||
|
||||
stmmac_set_rx_owner(priv, p, priv->use_riwt);
|
||||
buf->addr = page_pool_get_dma_addr(buf->page);
|
||||
stmmac_set_desc_addr(priv, p, buf->addr);
|
||||
stmmac_refill_desc3(priv, rx_q, p);
|
||||
|
||||
rx_q->rx_count_frames++;
|
||||
rx_q->rx_count_frames %= priv->rx_coal_frames;
|
||||
use_rx_wd = priv->use_riwt && rx_q->rx_count_frames;
|
||||
|
||||
dma_wmb();
|
||||
stmmac_set_rx_owner(priv, p, use_rx_wd);
|
||||
|
||||
entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
|
||||
}
|
||||
@ -3358,9 +3330,6 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
||||
unsigned int next_entry = rx_q->cur_rx;
|
||||
int coe = priv->hw->rx_csum;
|
||||
unsigned int count = 0;
|
||||
bool xmac;
|
||||
|
||||
xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
|
||||
|
||||
if (netif_msg_rx_status(priv)) {
|
||||
void *rx_head;
|
||||
@ -3374,11 +3343,12 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
||||
stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
|
||||
}
|
||||
while (count < limit) {
|
||||
struct stmmac_rx_buffer *buf;
|
||||
struct dma_desc *np, *p;
|
||||
int entry, status;
|
||||
struct dma_desc *p;
|
||||
struct dma_desc *np;
|
||||
|
||||
entry = next_entry;
|
||||
buf = &rx_q->buf_pool[entry];
|
||||
|
||||
if (priv->extend_desc)
|
||||
p = (struct dma_desc *)(rx_q->dma_erx + entry);
|
||||
@ -3408,20 +3378,9 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
||||
stmmac_rx_extended_status(priv, &priv->dev->stats,
|
||||
&priv->xstats, rx_q->dma_erx + entry);
|
||||
if (unlikely(status == discard_frame)) {
|
||||
page_pool_recycle_direct(rx_q->page_pool, buf->page);
|
||||
priv->dev->stats.rx_errors++;
|
||||
if (priv->hwts_rx_en && !priv->extend_desc) {
|
||||
/* DESC2 & DESC3 will be overwritten by device
|
||||
* with timestamp value, hence reinitialize
|
||||
* them in stmmac_rx_refill() function so that
|
||||
* device can reuse it.
|
||||
*/
|
||||
dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
|
||||
rx_q->rx_skbuff[entry] = NULL;
|
||||
dma_unmap_single(priv->device,
|
||||
rx_q->rx_skbuff_dma[entry],
|
||||
priv->dma_buf_sz,
|
||||
DMA_FROM_DEVICE);
|
||||
}
|
||||
buf->page = NULL;
|
||||
} else {
|
||||
struct sk_buff *skb;
|
||||
int frame_len;
|
||||
@ -3461,58 +3420,20 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
||||
frame_len, status);
|
||||
}
|
||||
|
||||
/* The zero-copy is always used for all the sizes
|
||||
* in case of GMAC4 because it needs
|
||||
* to refill the used descriptors, always.
|
||||
*/
|
||||
if (unlikely(!xmac &&
|
||||
((frame_len < priv->rx_copybreak) ||
|
||||
stmmac_rx_threshold_count(rx_q)))) {
|
||||
skb = netdev_alloc_skb_ip_align(priv->dev,
|
||||
frame_len);
|
||||
if (unlikely(!skb)) {
|
||||
if (net_ratelimit())
|
||||
dev_warn(priv->device,
|
||||
"packet dropped\n");
|
||||
priv->dev->stats.rx_dropped++;
|
||||
continue;
|
||||
}
|
||||
|
||||
dma_sync_single_for_cpu(priv->device,
|
||||
rx_q->rx_skbuff_dma
|
||||
[entry], frame_len,
|
||||
DMA_FROM_DEVICE);
|
||||
skb_copy_to_linear_data(skb,
|
||||
rx_q->
|
||||
rx_skbuff[entry]->data,
|
||||
frame_len);
|
||||
|
||||
skb_put(skb, frame_len);
|
||||
dma_sync_single_for_device(priv->device,
|
||||
rx_q->rx_skbuff_dma
|
||||
[entry], frame_len,
|
||||
DMA_FROM_DEVICE);
|
||||
} else {
|
||||
skb = rx_q->rx_skbuff[entry];
|
||||
if (unlikely(!skb)) {
|
||||
if (net_ratelimit())
|
||||
netdev_err(priv->dev,
|
||||
"%s: Inconsistent Rx chain\n",
|
||||
priv->dev->name);
|
||||
priv->dev->stats.rx_dropped++;
|
||||
continue;
|
||||
}
|
||||
prefetch(skb->data - NET_IP_ALIGN);
|
||||
rx_q->rx_skbuff[entry] = NULL;
|
||||
rx_q->rx_zeroc_thresh++;
|
||||
|
||||
skb_put(skb, frame_len);
|
||||
dma_unmap_single(priv->device,
|
||||
rx_q->rx_skbuff_dma[entry],
|
||||
priv->dma_buf_sz,
|
||||
DMA_FROM_DEVICE);
|
||||
skb = netdev_alloc_skb_ip_align(priv->dev, frame_len);
|
||||
if (unlikely(!skb)) {
|
||||
priv->dev->stats.rx_dropped++;
|
||||
continue;
|
||||
}
|
||||
|
||||
dma_sync_single_for_cpu(priv->device, buf->addr,
|
||||
frame_len, DMA_FROM_DEVICE);
|
||||
skb_copy_to_linear_data(skb, page_address(buf->page),
|
||||
frame_len);
|
||||
skb_put(skb, frame_len);
|
||||
dma_sync_single_for_device(priv->device, buf->addr,
|
||||
frame_len, DMA_FROM_DEVICE);
|
||||
|
||||
if (netif_msg_pktdata(priv)) {
|
||||
netdev_dbg(priv->dev, "frame received (%dbytes)",
|
||||
frame_len);
|
||||
@ -3532,6 +3453,10 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
|
||||
|
||||
napi_gro_receive(&ch->rx_napi, skb);
|
||||
|
||||
/* Data payload copied into SKB, page ready for recycle */
|
||||
page_pool_recycle_direct(rx_q->page_pool, buf->page);
|
||||
buf->page = NULL;
|
||||
|
||||
priv->dev->stats.rx_packets++;
|
||||
priv->dev->stats.rx_bytes += frame_len;
|
||||
}
|
||||
@ -4631,7 +4556,7 @@ int stmmac_resume(struct device *dev)
|
||||
stmmac_clear_descriptors(priv);
|
||||
|
||||
stmmac_hw_setup(ndev, false);
|
||||
stmmac_init_tx_coalesce(priv);
|
||||
stmmac_init_coalesce(priv);
|
||||
stmmac_set_rx_mode(ndev);
|
||||
|
||||
stmmac_enable_all_queues(priv);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user