mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-30 07:34:12 +08:00
dmaengine: stm32-mdma: Use bitfield helpers
Use the FIELD_{GET,PREP}() helpers, instead of defining custom macros
implementing the same operations.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/36ceab242a594233dc7dc6f1dddb4ac32d1e846f.1637593297.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Geert Uytterhoeven
Vinod Koul
parent
d697e83125
commit
de8f2c0575
@ -10,6 +10,7 @@
|
||||
* Inspired by stm32-dma.c and dma-jz4780.c
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dmaengine.h>
|
||||
@ -32,13 +33,6 @@
|
||||
|
||||
#include "virt-dma.h"
|
||||
|
||||
/* MDMA Generic getter/setter */
|
||||
#define STM32_MDMA_SHIFT(n) (ffs(n) - 1)
|
||||
#define STM32_MDMA_SET(n, mask) (((n) << STM32_MDMA_SHIFT(mask)) & \
|
||||
(mask))
|
||||
#define STM32_MDMA_GET(n, mask) (((n) & (mask)) >> \
|
||||
STM32_MDMA_SHIFT(mask))
|
||||
|
||||
#define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */
|
||||
#define STM32_MDMA_GISR1 0x0004 /* MDMA Int Status Reg 2 */
|
||||
|
||||
@ -80,8 +74,7 @@
|
||||
#define STM32_MDMA_CCR_HEX BIT(13)
|
||||
#define STM32_MDMA_CCR_BEX BIT(12)
|
||||
#define STM32_MDMA_CCR_PL_MASK GENMASK(7, 6)
|
||||
#define STM32_MDMA_CCR_PL(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CCR_PL_MASK)
|
||||
#define STM32_MDMA_CCR_PL(n) FIELD_PREP(STM32_MDMA_CCR_PL_MASK, (n))
|
||||
#define STM32_MDMA_CCR_TCIE BIT(5)
|
||||
#define STM32_MDMA_CCR_BTIE BIT(4)
|
||||
#define STM32_MDMA_CCR_BRTIE BIT(3)
|
||||
@ -99,48 +92,33 @@
|
||||
#define STM32_MDMA_CTCR_BWM BIT(31)
|
||||
#define STM32_MDMA_CTCR_SWRM BIT(30)
|
||||
#define STM32_MDMA_CTCR_TRGM_MSK GENMASK(29, 28)
|
||||
#define STM32_MDMA_CTCR_TRGM(n) STM32_MDMA_SET((n), \
|
||||
STM32_MDMA_CTCR_TRGM_MSK)
|
||||
#define STM32_MDMA_CTCR_TRGM_GET(n) STM32_MDMA_GET((n), \
|
||||
STM32_MDMA_CTCR_TRGM_MSK)
|
||||
#define STM32_MDMA_CTCR_TRGM(n) FIELD_PREP(STM32_MDMA_CTCR_TRGM_MSK, (n))
|
||||
#define STM32_MDMA_CTCR_TRGM_GET(n) FIELD_GET(STM32_MDMA_CTCR_TRGM_MSK, (n))
|
||||
#define STM32_MDMA_CTCR_PAM_MASK GENMASK(27, 26)
|
||||
#define STM32_MDMA_CTCR_PAM(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CTCR_PAM_MASK)
|
||||
#define STM32_MDMA_CTCR_PAM(n) FIELD_PREP(STM32_MDMA_CTCR_PAM_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_PKE BIT(25)
|
||||
#define STM32_MDMA_CTCR_TLEN_MSK GENMASK(24, 18)
|
||||
#define STM32_MDMA_CTCR_TLEN(n) STM32_MDMA_SET((n), \
|
||||
STM32_MDMA_CTCR_TLEN_MSK)
|
||||
#define STM32_MDMA_CTCR_TLEN_GET(n) STM32_MDMA_GET((n), \
|
||||
STM32_MDMA_CTCR_TLEN_MSK)
|
||||
#define STM32_MDMA_CTCR_TLEN(n) FIELD_PREP(STM32_MDMA_CTCR_TLEN_MSK, (n))
|
||||
#define STM32_MDMA_CTCR_TLEN_GET(n) FIELD_GET(STM32_MDMA_CTCR_TLEN_MSK, (n))
|
||||
#define STM32_MDMA_CTCR_LEN2_MSK GENMASK(25, 18)
|
||||
#define STM32_MDMA_CTCR_LEN2(n) STM32_MDMA_SET((n), \
|
||||
STM32_MDMA_CTCR_LEN2_MSK)
|
||||
#define STM32_MDMA_CTCR_LEN2_GET(n) STM32_MDMA_GET((n), \
|
||||
STM32_MDMA_CTCR_LEN2_MSK)
|
||||
#define STM32_MDMA_CTCR_LEN2(n) FIELD_PREP(STM32_MDMA_CTCR_LEN2_MSK, (n))
|
||||
#define STM32_MDMA_CTCR_LEN2_GET(n) FIELD_GET(STM32_MDMA_CTCR_LEN2_MSK, (n))
|
||||
#define STM32_MDMA_CTCR_DBURST_MASK GENMASK(17, 15)
|
||||
#define STM32_MDMA_CTCR_DBURST(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CTCR_DBURST_MASK)
|
||||
#define STM32_MDMA_CTCR_DBURST(n) FIELD_PREP(STM32_MDMA_CTCR_DBURST_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_SBURST_MASK GENMASK(14, 12)
|
||||
#define STM32_MDMA_CTCR_SBURST(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CTCR_SBURST_MASK)
|
||||
#define STM32_MDMA_CTCR_SBURST(n) FIELD_PREP(STM32_MDMA_CTCR_SBURST_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_DINCOS_MASK GENMASK(11, 10)
|
||||
#define STM32_MDMA_CTCR_DINCOS(n) STM32_MDMA_SET((n), \
|
||||
STM32_MDMA_CTCR_DINCOS_MASK)
|
||||
#define STM32_MDMA_CTCR_DINCOS(n) FIELD_PREP(STM32_MDMA_CTCR_DINCOS_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_SINCOS_MASK GENMASK(9, 8)
|
||||
#define STM32_MDMA_CTCR_SINCOS(n) STM32_MDMA_SET((n), \
|
||||
STM32_MDMA_CTCR_SINCOS_MASK)
|
||||
#define STM32_MDMA_CTCR_SINCOS(n) FIELD_PREP(STM32_MDMA_CTCR_SINCOS_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_DSIZE_MASK GENMASK(7, 6)
|
||||
#define STM32_MDMA_CTCR_DSIZE(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CTCR_DSIZE_MASK)
|
||||
#define STM32_MDMA_CTCR_DSIZE(n) FIELD_PREP(STM32_MDMA_CTCR_DSIZE_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_SSIZE_MASK GENMASK(5, 4)
|
||||
#define STM32_MDMA_CTCR_SSIZE(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CTCR_SSIZE_MASK)
|
||||
#define STM32_MDMA_CTCR_SSIZE(n) FIELD_PREP(STM32_MDMA_CTCR_SSIZE_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_DINC_MASK GENMASK(3, 2)
|
||||
#define STM32_MDMA_CTCR_DINC(n) STM32_MDMA_SET((n), \
|
||||
STM32_MDMA_CTCR_DINC_MASK)
|
||||
#define STM32_MDMA_CTCR_DINC(n) FIELD_PREP(STM32_MDMA_CTCR_DINC_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_SINC_MASK GENMASK(1, 0)
|
||||
#define STM32_MDMA_CTCR_SINC(n) STM32_MDMA_SET((n), \
|
||||
STM32_MDMA_CTCR_SINC_MASK)
|
||||
#define STM32_MDMA_CTCR_SINC(n) FIELD_PREP(STM32_MDMA_CTCR_SINC_MASK, (n))
|
||||
#define STM32_MDMA_CTCR_CFG_MASK (STM32_MDMA_CTCR_SINC_MASK \
|
||||
| STM32_MDMA_CTCR_DINC_MASK \
|
||||
| STM32_MDMA_CTCR_SINCOS_MASK \
|
||||
@ -151,16 +129,13 @@
|
||||
/* MDMA Channel x block number of data register */
|
||||
#define STM32_MDMA_CBNDTR(x) (0x54 + 0x40 * (x))
|
||||
#define STM32_MDMA_CBNDTR_BRC_MK GENMASK(31, 20)
|
||||
#define STM32_MDMA_CBNDTR_BRC(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CBNDTR_BRC_MK)
|
||||
#define STM32_MDMA_CBNDTR_BRC_GET(n) STM32_MDMA_GET((n), \
|
||||
STM32_MDMA_CBNDTR_BRC_MK)
|
||||
#define STM32_MDMA_CBNDTR_BRC(n) FIELD_PREP(STM32_MDMA_CBNDTR_BRC_MK, (n))
|
||||
#define STM32_MDMA_CBNDTR_BRC_GET(n) FIELD_GET(STM32_MDMA_CBNDTR_BRC_MK, (n))
|
||||
|
||||
#define STM32_MDMA_CBNDTR_BRDUM BIT(19)
|
||||
#define STM32_MDMA_CBNDTR_BRSUM BIT(18)
|
||||
#define STM32_MDMA_CBNDTR_BNDT_MASK GENMASK(16, 0)
|
||||
#define STM32_MDMA_CBNDTR_BNDT(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CBNDTR_BNDT_MASK)
|
||||
#define STM32_MDMA_CBNDTR_BNDT(n) FIELD_PREP(STM32_MDMA_CBNDTR_BNDT_MASK, (n))
|
||||
|
||||
/* MDMA Channel x source address register */
|
||||
#define STM32_MDMA_CSAR(x) (0x58 + 0x40 * (x))
|
||||
@ -171,11 +146,9 @@
|
||||
/* MDMA Channel x block repeat address update register */
|
||||
#define STM32_MDMA_CBRUR(x) (0x60 + 0x40 * (x))
|
||||
#define STM32_MDMA_CBRUR_DUV_MASK GENMASK(31, 16)
|
||||
#define STM32_MDMA_CBRUR_DUV(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CBRUR_DUV_MASK)
|
||||
#define STM32_MDMA_CBRUR_DUV(n) FIELD_PREP(STM32_MDMA_CBRUR_DUV_MASK, (n))
|
||||
#define STM32_MDMA_CBRUR_SUV_MASK GENMASK(15, 0)
|
||||
#define STM32_MDMA_CBRUR_SUV(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CBRUR_SUV_MASK)
|
||||
#define STM32_MDMA_CBRUR_SUV(n) FIELD_PREP(STM32_MDMA_CBRUR_SUV_MASK, (n))
|
||||
|
||||
/* MDMA Channel x link address register */
|
||||
#define STM32_MDMA_CLAR(x) (0x64 + 0x40 * (x))
|
||||
@ -185,8 +158,7 @@
|
||||
#define STM32_MDMA_CTBR_DBUS BIT(17)
|
||||
#define STM32_MDMA_CTBR_SBUS BIT(16)
|
||||
#define STM32_MDMA_CTBR_TSEL_MASK GENMASK(7, 0)
|
||||
#define STM32_MDMA_CTBR_TSEL(n) STM32_MDMA_SET(n, \
|
||||
STM32_MDMA_CTBR_TSEL_MASK)
|
||||
#define STM32_MDMA_CTBR_TSEL(n) FIELD_PREP(STM32_MDMA_CTBR_TSEL_MASK, (n))
|
||||
|
||||
/* MDMA Channel x mask address register */
|
||||
#define STM32_MDMA_CMAR(x) (0x70 + 0x40 * (x))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user