diff --git a/drivers/staging/rtl8723au/hal/rtl8723a_phycfg.c b/drivers/staging/rtl8723au/hal/rtl8723a_phycfg.c index bac3f3bd5311..8400e6e2fca8 100644 --- a/drivers/staging/rtl8723au/hal/rtl8723a_phycfg.c +++ b/drivers/staging/rtl8723au/hal/rtl8723a_phycfg.c @@ -462,20 +462,12 @@ phy_InitBBRFRegisterDefinition(struct rtw_adapter *Adapter) pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; - /* 16 LSBs if read 32-bit from 0x874 */ - pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; - /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ - pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; /* RF Interface Readback Value */ /* 16 LSBs if read 32-bit from 0x8E0 */ pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; - /* 16 LSBs if read 32-bit from 0x8E4 */ - pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; - /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ - pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; /* RF Interface Output (and Enable) */ /* 16 LSBs if read 32-bit from 0x860 */ @@ -497,14 +489,10 @@ phy_InitBBRFRegisterDefinition(struct rtw_adapter *Adapter) /* BB Band Select */ pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; - pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; - pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; - pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; - pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; /* Tranceiver A~D HSSI Parameter-1 */ /* wire control parameter1 */ @@ -523,63 +511,40 @@ phy_InitBBRFRegisterDefinition(struct rtw_adapter *Adapter) rFPGA0_XAB_SwitchControl; /* TR/Ant switch control */ pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; - pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = - rFPGA0_XCD_SwitchControl; - pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = - rFPGA0_XCD_SwitchControl; /* AGC control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; - pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; - pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; /* AGC control 2 */ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; - pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; - pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; /* RX AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; - pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; - pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; /* RX AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; - pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; - pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; /* Tx AFE control 1 */ pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; - pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; - pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; /* Tx AFE control 2 */ pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; - pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; - pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; /* Tranceiver LSSI Readback SI mode */ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; /* Tranceiver LSSI Readback PI mode */ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; - /* pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = - rFPGA0_XC_LSSIReadBack; */ - /* pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = - rFPGA0_XD_LSSIReadBack; */ - } /* The following is for High Power PA */ diff --git a/drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c b/drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c index 2a7238bacdc8..ed39c18c3f84 100644 --- a/drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c +++ b/drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c @@ -434,11 +434,9 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter) /*----Store original RFENV control type----*/ switch (eRFPath) { case RF_PATH_A: - case RF_PATH_C: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF_PATH_B: - case RF_PATH_D: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } @@ -468,20 +466,14 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter) if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile23a(&pHalData->odmpriv, (enum RF_RADIO_PATH)eRFPath, (enum RF_RADIO_PATH)eRFPath)) rtStatus = _FAIL; break; - case RF_PATH_C: - break; - case RF_PATH_D: - break; } /*----Restore RFENV control type----*/; switch (eRFPath) { case RF_PATH_A: - case RF_PATH_C: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF_PATH_B: - case RF_PATH_D: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } diff --git a/drivers/staging/rtl8723au/include/Hal8723APhyCfg.h b/drivers/staging/rtl8723au/include/Hal8723APhyCfg.h index 1478d311683a..4b7f3479c0a9 100644 --- a/drivers/staging/rtl8723au/include/Hal8723APhyCfg.h +++ b/drivers/staging/rtl8723au/include/Hal8723APhyCfg.h @@ -60,8 +60,6 @@ enum HW90_BLOCK { enum RF_RADIO_PATH { RF_PATH_A = 0, /* Radio Path A */ RF_PATH_B = 1, /* Radio Path B */ - RF_PATH_C = 2, /* Radio Path C */ - RF_PATH_D = 3, /* Radio Path D */ RF_PATH_MAX /* Max RF number 90 support */ };