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[SCSI] mvsas: split driver into multiple files
Split mvsas driver into multiple source codes, based on the split and function distribution found in Marvell's mvsas update. Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
This commit is contained in:
Jeff Garzik
James Bottomley
parent
2ad52f473b
commit
dd4969a892
@ -22,5 +22,6 @@
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# USA
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obj-$(CONFIG_SCSI_MVSAS) += mvsas.o
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mvsas-y += mv_sas.o
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mvsas-y += mv_init.o \
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mv_sas.o \
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mv_64xx.o
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184
drivers/scsi/mvsas/mv_64xx.c
Normal file
184
drivers/scsi/mvsas/mv_64xx.c
Normal file
@ -0,0 +1,184 @@
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/*
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mv_64xx.c - Marvell 88SE6440 SAS/SATA support
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Copyright 2007 Red Hat, Inc.
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Copyright 2008 Marvell. <kewei@marvell.com>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2,
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or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty
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of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public
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License along with this program; see the file COPYING. If not,
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write to the Free Software Foundation, 675 Mass Ave, Cambridge,
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MA 02139, USA.
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*/
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#include "mv_sas.h"
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#include "mv_64xx.h"
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#include "mv_chips.h"
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void mvs_detect_porttype(struct mvs_info *mvi, int i)
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{
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void __iomem *regs = mvi->regs;
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u32 reg;
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struct mvs_phy *phy = &mvi->phy[i];
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/* TODO check & save device type */
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reg = mr32(GBL_PORT_TYPE);
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if (reg & MODE_SAS_SATA & (1 << i))
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phy->phy_type |= PORT_TYPE_SAS;
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else
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phy->phy_type |= PORT_TYPE_SATA;
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}
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void mvs_enable_xmt(struct mvs_info *mvi, int PhyId)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(PCS);
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if (mvi->chip->n_phy <= 4)
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tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT);
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else
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tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT2);
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mw32(PCS, tmp);
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}
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void __devinit mvs_phy_hacks(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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/* workaround for SATA R-ERR, to ignore phy glitch */
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tmp = mvs_cr32(regs, CMD_PHY_TIMER);
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tmp &= ~(1 << 9);
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tmp |= (1 << 10);
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mvs_cw32(regs, CMD_PHY_TIMER, tmp);
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/* enable retry 127 times */
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mvs_cw32(regs, CMD_SAS_CTL1, 0x7f7f);
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/* extend open frame timeout to max */
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tmp = mvs_cr32(regs, CMD_SAS_CTL0);
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tmp &= ~0xffff;
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tmp |= 0x3fff;
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mvs_cw32(regs, CMD_SAS_CTL0, tmp);
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/* workaround for WDTIMEOUT , set to 550 ms */
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mvs_cw32(regs, CMD_WD_TIMER, 0x86470);
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/* not to halt for different port op during wideport link change */
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mvs_cw32(regs, CMD_APP_ERR_CONFIG, 0xffefbf7d);
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/* workaround for Seagate disk not-found OOB sequence, recv
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* COMINIT before sending out COMWAKE */
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tmp = mvs_cr32(regs, CMD_PHY_MODE_21);
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tmp &= 0x0000ffff;
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tmp |= 0x00fa0000;
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mvs_cw32(regs, CMD_PHY_MODE_21, tmp);
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tmp = mvs_cr32(regs, CMD_PHY_TIMER);
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tmp &= 0x1fffffff;
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tmp |= (2U << 29); /* 8 ms retry */
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mvs_cw32(regs, CMD_PHY_TIMER, tmp);
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/* TEST - for phy decoding error, adjust voltage levels */
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mw32(P0_VSR_ADDR + 0, 0x8);
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mw32(P0_VSR_DATA + 0, 0x2F0);
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mw32(P0_VSR_ADDR + 8, 0x8);
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mw32(P0_VSR_DATA + 8, 0x2F0);
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mw32(P0_VSR_ADDR + 16, 0x8);
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mw32(P0_VSR_DATA + 16, 0x2F0);
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mw32(P0_VSR_ADDR + 24, 0x8);
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mw32(P0_VSR_DATA + 24, 0x2F0);
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}
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void mvs_hba_interrupt_enable(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(GBL_CTL);
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mw32(GBL_CTL, tmp | INT_EN);
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}
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void mvs_hba_interrupt_disable(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp;
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tmp = mr32(GBL_CTL);
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mw32(GBL_CTL, tmp & ~INT_EN);
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}
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void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port)
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{
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void __iomem *regs = mvi->regs;
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u32 tmp, offs;
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u8 *tfs = &port->taskfileset;
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if (*tfs == MVS_ID_NOT_MAPPED)
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return;
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offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
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if (*tfs < 16) {
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tmp = mr32(PCS);
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mw32(PCS, tmp & ~offs);
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} else {
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tmp = mr32(CTL);
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mw32(CTL, tmp & ~offs);
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}
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tmp = mr32(INT_STAT_SRS) & (1U << *tfs);
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if (tmp)
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mw32(INT_STAT_SRS, tmp);
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*tfs = MVS_ID_NOT_MAPPED;
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}
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u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port)
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{
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int i;
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u32 tmp, offs;
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void __iomem *regs = mvi->regs;
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if (port->taskfileset != MVS_ID_NOT_MAPPED)
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return 0;
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tmp = mr32(PCS);
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for (i = 0; i < mvi->chip->srs_sz; i++) {
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if (i == 16)
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tmp = mr32(CTL);
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offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
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if (!(tmp & offs)) {
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port->taskfileset = i;
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if (i < 16)
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mw32(PCS, tmp | offs);
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else
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mw32(CTL, tmp | offs);
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tmp = mr32(INT_STAT_SRS) & (1U << i);
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if (tmp)
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mw32(INT_STAT_SRS, tmp);
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return 0;
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}
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}
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return MVS_ID_NOT_MAPPED;
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}
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92
drivers/scsi/mvsas/mv_64xx.h
Normal file
92
drivers/scsi/mvsas/mv_64xx.h
Normal file
@ -0,0 +1,92 @@
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#ifndef _MVS64XX_REG_H_
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#define _MVS64XX_REG_H_
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/* enhanced mode registers (BAR4) */
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enum hw_registers {
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MVS_GBL_CTL = 0x04, /* global control */
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MVS_GBL_INT_STAT = 0x08, /* global irq status */
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MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
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MVS_GBL_PORT_TYPE = 0xa0, /* port type */
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MVS_CTL = 0x100, /* SAS/SATA port configuration */
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MVS_PCS = 0x104, /* SAS/SATA port control/status */
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MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
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MVS_CMD_LIST_HI = 0x10C,
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MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
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MVS_RX_FIS_HI = 0x114,
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MVS_TX_CFG = 0x120, /* TX configuration */
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MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
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MVS_TX_HI = 0x128,
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MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
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MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
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MVS_RX_CFG = 0x134, /* RX configuration */
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MVS_RX_LO = 0x138, /* RX (completion) ring addr */
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MVS_RX_HI = 0x13C,
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MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
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MVS_INT_COAL = 0x148, /* Int coalescing config */
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MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
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MVS_INT_STAT = 0x150, /* Central int status */
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MVS_INT_MASK = 0x154, /* Central int enable */
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MVS_INT_STAT_SRS = 0x158, /* SATA register set status */
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MVS_INT_MASK_SRS = 0x15C,
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/* ports 1-3 follow after this */
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MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */
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MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */
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MVS_P4_INT_STAT = 0x200, /* Port 4 interrupt status */
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MVS_P4_INT_MASK = 0x204, /* Port 4 interrupt enable mask */
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/* ports 1-3 follow after this */
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MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */
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MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */
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MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */
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MVS_CMD_DATA = 0x1BC, /* Command register port (data) */
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/* ports 1-3 follow after this */
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MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */
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MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */
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MVS_P4_CFG_ADDR = 0x230, /* Port 4 config address */
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MVS_P4_CFG_DATA = 0x234, /* Port 4 config data */
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/* ports 1-3 follow after this */
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MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */
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MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */
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MVS_P4_VSR_ADDR = 0x250, /* port 4 VSR addr */
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MVS_P4_VSR_DATA = 0x254, /* port 4 VSR data */
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};
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enum pci_cfg_registers {
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PCR_PHY_CTL = 0x40,
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PCR_PHY_CTL2 = 0x90,
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PCR_DEV_CTRL = 0xE8,
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};
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/* SAS/SATA Vendor Specific Port Registers */
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enum sas_sata_vsp_regs {
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VSR_PHY_STAT = 0x00, /* Phy Status */
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VSR_PHY_MODE1 = 0x01, /* phy tx */
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VSR_PHY_MODE2 = 0x02, /* tx scc */
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VSR_PHY_MODE3 = 0x03, /* pll */
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VSR_PHY_MODE4 = 0x04, /* VCO */
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VSR_PHY_MODE5 = 0x05, /* Rx */
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VSR_PHY_MODE6 = 0x06, /* CDR */
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VSR_PHY_MODE7 = 0x07, /* Impedance */
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VSR_PHY_MODE8 = 0x08, /* Voltage */
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VSR_PHY_MODE9 = 0x09, /* Test */
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VSR_PHY_MODE10 = 0x0A, /* Power */
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VSR_PHY_MODE11 = 0x0B, /* Phy Mode */
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VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */
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VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */
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};
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struct mvs_prd {
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__le64 addr; /* 64-bit buffer address */
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__le32 reserved;
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__le32 len; /* 16-bit length */
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};
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#endif
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118
drivers/scsi/mvsas/mv_chips.h
Normal file
118
drivers/scsi/mvsas/mv_chips.h
Normal file
@ -0,0 +1,118 @@
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#ifndef _MV_CHIPS_H_
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#define _MV_CHIPS_H_
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#define mr32(reg) readl(regs + MVS_##reg)
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#define mw32(reg,val) writel((val), regs + MVS_##reg)
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#define mw32_f(reg,val) do { \
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writel((val), regs + MVS_##reg); \
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readl(regs + MVS_##reg); \
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} while (0)
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static inline u32 mvs_cr32(void __iomem *regs, u32 addr)
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{
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mw32(CMD_ADDR, addr);
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return mr32(CMD_DATA);
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}
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static inline void mvs_cw32(void __iomem *regs, u32 addr, u32 val)
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{
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mw32(CMD_ADDR, addr);
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mw32(CMD_DATA, val);
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}
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static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
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{
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void __iomem *regs = mvi->regs;
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return (port < 4)?mr32(P0_SER_CTLSTAT + port * 4):
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mr32(P4_SER_CTLSTAT + (port - 4) * 4);
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}
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static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
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{
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void __iomem *regs = mvi->regs;
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if (port < 4)
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mw32(P0_SER_CTLSTAT + port * 4, val);
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else
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mw32(P4_SER_CTLSTAT + (port - 4) * 4, val);
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}
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static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off, u32 off2, u32 port)
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{
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void __iomem *regs = mvi->regs + off;
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void __iomem *regs2 = mvi->regs + off2;
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return (port < 4)?readl(regs + port * 8):
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readl(regs2 + (port - 4) * 8);
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}
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static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
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u32 port, u32 val)
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{
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void __iomem *regs = mvi->regs + off;
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void __iomem *regs2 = mvi->regs + off2;
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if (port < 4)
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writel(val, regs + port * 8);
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else
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writel(val, regs2 + (port - 4) * 8);
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}
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static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
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{
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return mvs_read_port(mvi, MVS_P0_CFG_DATA,
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MVS_P4_CFG_DATA, port);
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}
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static inline void mvs_write_port_cfg_data(struct mvs_info *mvi, u32 port, u32 val)
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{
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mvs_write_port(mvi, MVS_P0_CFG_DATA,
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MVS_P4_CFG_DATA, port, val);
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}
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static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi, u32 port, u32 addr)
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{
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mvs_write_port(mvi, MVS_P0_CFG_ADDR,
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MVS_P4_CFG_ADDR, port, addr);
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}
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static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
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{
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return mvs_read_port(mvi, MVS_P0_VSR_DATA,
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MVS_P4_VSR_DATA, port);
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}
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static inline void mvs_write_port_vsr_data(struct mvs_info *mvi, u32 port, u32 val)
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{
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mvs_write_port(mvi, MVS_P0_VSR_DATA,
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MVS_P4_VSR_DATA, port, val);
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}
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static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi, u32 port, u32 addr)
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{
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mvs_write_port(mvi, MVS_P0_VSR_ADDR,
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MVS_P4_VSR_ADDR, port, addr);
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}
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static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
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{
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return mvs_read_port(mvi, MVS_P0_INT_STAT,
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MVS_P4_INT_STAT, port);
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}
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static inline void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val)
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{
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mvs_write_port(mvi, MVS_P0_INT_STAT,
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MVS_P4_INT_STAT, port, val);
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}
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static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
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{
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return mvs_read_port(mvi, MVS_P0_INT_MASK,
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MVS_P4_INT_MASK, port);
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}
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static inline void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val)
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{
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mvs_write_port(mvi, MVS_P0_INT_MASK,
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MVS_P4_INT_MASK, port, val);
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}
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#endif
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441
drivers/scsi/mvsas/mv_defs.h
Normal file
441
drivers/scsi/mvsas/mv_defs.h
Normal file
@ -0,0 +1,441 @@
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/*
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mv_defs.h - Marvell 88SE6440 SAS/SATA support
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Copyright 2007 Red Hat, Inc.
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Copyright 2008 Marvell. <kewei@marvell.com>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2,
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or (at your option) any later version.
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|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty
|
||||
of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public
|
||||
License along with this program; see the file COPYING. If not,
|
||||
write to the Free Software Foundation, 675 Mass Ave, Cambridge,
|
||||
MA 02139, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _MV_DEFS_H_
|
||||
#define _MV_DEFS_H_
|
||||
|
||||
/* driver compile-time configuration */
|
||||
enum driver_configuration {
|
||||
MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
|
||||
MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
|
||||
/* software requires power-of-2
|
||||
ring size */
|
||||
|
||||
MVS_SLOTS = 512, /* command slots */
|
||||
MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
|
||||
MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */
|
||||
MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
|
||||
MVS_OAF_SZ = 64, /* Open address frame buffer size */
|
||||
|
||||
MVS_RX_FIS_COUNT = 17, /* Optional rx'd FISs (max 17) */
|
||||
|
||||
MVS_QUEUE_SIZE = 30, /* Support Queue depth */
|
||||
MVS_CAN_QUEUE = MVS_SLOTS - 1, /* SCSI Queue depth */
|
||||
};
|
||||
|
||||
/* unchangeable hardware details */
|
||||
enum hardware_details {
|
||||
MVS_MAX_PHYS = 8, /* max. possible phys */
|
||||
MVS_MAX_PORTS = 8, /* max. possible ports */
|
||||
MVS_RX_FISL_SZ = 0x400 + (MVS_RX_FIS_COUNT * 0x100),
|
||||
};
|
||||
|
||||
/* peripheral registers (BAR2) */
|
||||
enum peripheral_registers {
|
||||
SPI_CTL = 0x10, /* EEPROM control */
|
||||
SPI_CMD = 0x14, /* EEPROM command */
|
||||
SPI_DATA = 0x18, /* EEPROM data */
|
||||
};
|
||||
|
||||
enum peripheral_register_bits {
|
||||
TWSI_RDY = (1U << 7), /* EEPROM interface ready */
|
||||
TWSI_RD = (1U << 4), /* EEPROM read access */
|
||||
|
||||
SPI_ADDR_MASK = 0x3ffff, /* bits 17:0 */
|
||||
};
|
||||
|
||||
enum hw_register_bits {
|
||||
/* MVS_GBL_CTL */
|
||||
INT_EN = (1U << 1), /* Global int enable */
|
||||
HBA_RST = (1U << 0), /* HBA reset */
|
||||
|
||||
/* MVS_GBL_INT_STAT */
|
||||
INT_XOR = (1U << 4), /* XOR engine event */
|
||||
INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
|
||||
|
||||
/* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
|
||||
SATA_TARGET = (1U << 16), /* port0 SATA target enable */
|
||||
MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */
|
||||
MODE_AUTO_DET_PORT6 = (1U << 14),
|
||||
MODE_AUTO_DET_PORT5 = (1U << 13),
|
||||
MODE_AUTO_DET_PORT4 = (1U << 12),
|
||||
MODE_AUTO_DET_PORT3 = (1U << 11),
|
||||
MODE_AUTO_DET_PORT2 = (1U << 10),
|
||||
MODE_AUTO_DET_PORT1 = (1U << 9),
|
||||
MODE_AUTO_DET_PORT0 = (1U << 8),
|
||||
MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
|
||||
MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
|
||||
MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
|
||||
MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
|
||||
MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
|
||||
MODE_SAS_PORT6_MASK = (1U << 6),
|
||||
MODE_SAS_PORT5_MASK = (1U << 5),
|
||||
MODE_SAS_PORT4_MASK = (1U << 4),
|
||||
MODE_SAS_PORT3_MASK = (1U << 3),
|
||||
MODE_SAS_PORT2_MASK = (1U << 2),
|
||||
MODE_SAS_PORT1_MASK = (1U << 1),
|
||||
MODE_SAS_PORT0_MASK = (1U << 0),
|
||||
MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
|
||||
MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
|
||||
MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
|
||||
MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
|
||||
|
||||
/* SAS_MODE value may be
|
||||
* dictated (in hw) by values
|
||||
* of SATA_TARGET & AUTO_DET
|
||||
*/
|
||||
|
||||
/* MVS_TX_CFG */
|
||||
TX_EN = (1U << 16), /* Enable TX */
|
||||
TX_RING_SZ_MASK = 0xfff, /* TX ring size, bits 11:0 */
|
||||
|
||||
/* MVS_RX_CFG */
|
||||
RX_EN = (1U << 16), /* Enable RX */
|
||||
RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */
|
||||
|
||||
/* MVS_INT_COAL */
|
||||
COAL_EN = (1U << 16), /* Enable int coalescing */
|
||||
|
||||
/* MVS_INT_STAT, MVS_INT_MASK */
|
||||
CINT_I2C = (1U << 31), /* I2C event */
|
||||
CINT_SW0 = (1U << 30), /* software event 0 */
|
||||
CINT_SW1 = (1U << 29), /* software event 1 */
|
||||
CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
|
||||
CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
|
||||
CINT_MEM = (1U << 26), /* int mem parity err */
|
||||
CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */
|
||||
CINT_SRS = (1U << 3), /* SRS event */
|
||||
CINT_CI_STOP = (1U << 1), /* cmd issue stopped */
|
||||
CINT_DONE = (1U << 0), /* cmd completion */
|
||||
|
||||
/* shl for ports 1-3 */
|
||||
CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */
|
||||
CINT_PORT = (1U << 8), /* port0 event */
|
||||
CINT_PORT_MASK_OFFSET = 8,
|
||||
CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
|
||||
|
||||
/* TX (delivery) ring bits */
|
||||
TXQ_CMD_SHIFT = 29,
|
||||
TXQ_CMD_SSP = 1, /* SSP protocol */
|
||||
TXQ_CMD_SMP = 2, /* SMP protocol */
|
||||
TXQ_CMD_STP = 3, /* STP/SATA protocol */
|
||||
TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP targ free list */
|
||||
TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
|
||||
TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
|
||||
TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
|
||||
TXQ_SRS_SHIFT = 20, /* SATA register set */
|
||||
TXQ_SRS_MASK = 0x7f,
|
||||
TXQ_PHY_SHIFT = 12, /* PHY bitmap */
|
||||
TXQ_PHY_MASK = 0xff,
|
||||
TXQ_SLOT_MASK = 0xfff, /* slot number */
|
||||
|
||||
/* RX (completion) ring bits */
|
||||
RXQ_GOOD = (1U << 23), /* Response good */
|
||||
RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */
|
||||
RXQ_CMD_RX = (1U << 20), /* target cmd received */
|
||||
RXQ_ATTN = (1U << 19), /* attention */
|
||||
RXQ_RSP = (1U << 18), /* response frame xfer'd */
|
||||
RXQ_ERR = (1U << 17), /* err info rec xfer'd */
|
||||
RXQ_DONE = (1U << 16), /* cmd complete */
|
||||
RXQ_SLOT_MASK = 0xfff, /* slot number */
|
||||
|
||||
/* mvs_cmd_hdr bits */
|
||||
MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
|
||||
MCH_SSP_FR_TYPE_SHIFT = 13, /* SSP frame type */
|
||||
|
||||
/* SSP initiator only */
|
||||
MCH_SSP_FR_CMD = 0x0, /* COMMAND frame */
|
||||
|
||||
/* SSP initiator or target */
|
||||
MCH_SSP_FR_TASK = 0x1, /* TASK frame */
|
||||
|
||||
/* SSP target only */
|
||||
MCH_SSP_FR_XFER_RDY = 0x4, /* XFER_RDY frame */
|
||||
MCH_SSP_FR_RESP = 0x5, /* RESPONSE frame */
|
||||
MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */
|
||||
MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */
|
||||
|
||||
MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
|
||||
MCH_FBURST = (1U << 11), /* first burst (SSP) */
|
||||
MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
|
||||
MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */
|
||||
MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */
|
||||
MCH_RESET = (1U << 7), /* Reset (STP/SATA) */
|
||||
MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */
|
||||
MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */
|
||||
MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */
|
||||
MCH_PMP_MASK = 0xf, /* PMP from cmd FIS (STP/SATA)*/
|
||||
|
||||
CCTL_RST = (1U << 5), /* port logic reset */
|
||||
|
||||
/* 0(LSB first), 1(MSB first) */
|
||||
CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
|
||||
CCTL_ENDIAN_RSP = (1U << 2), /* response frame */
|
||||
CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */
|
||||
CCTL_ENDIAN_CMD = (1U << 0), /* command table */
|
||||
|
||||
/* MVS_Px_SER_CTLSTAT (per-phy control) */
|
||||
PHY_SSP_RST = (1U << 3), /* reset SSP link layer */
|
||||
PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
|
||||
PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
|
||||
PHY_RST = (1U << 0), /* phy reset */
|
||||
PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
|
||||
PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
|
||||
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
|
||||
PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
|
||||
(0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
|
||||
PHY_READY_MASK = (1U << 20),
|
||||
|
||||
/* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
|
||||
PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
|
||||
PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
|
||||
PHYEV_AN = (1U << 18), /* SATA async notification */
|
||||
PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
|
||||
PHYEV_SIG_FIS = (1U << 16), /* signature FIS */
|
||||
PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
|
||||
PHYEV_IU_BIG = (1U << 11), /* IU too long err */
|
||||
PHYEV_IU_SMALL = (1U << 10), /* IU too short err */
|
||||
PHYEV_UNK_TAG = (1U << 9), /* unknown tag */
|
||||
PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */
|
||||
PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
|
||||
PHYEV_PORT_SEL = (1U << 6), /* port selector present */
|
||||
PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
|
||||
PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */
|
||||
PHYEV_ID_FAIL = (1U << 3), /* identify failed */
|
||||
PHYEV_ID_DONE = (1U << 2), /* identify done */
|
||||
PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */
|
||||
PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */
|
||||
|
||||
/* MVS_PCS */
|
||||
PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */
|
||||
PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */
|
||||
PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6480 */
|
||||
PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
|
||||
PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
|
||||
PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
|
||||
PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
|
||||
PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
|
||||
PCS_CMD_RST = (1U << 1), /* reset cmd issue */
|
||||
PCS_CMD_EN = (1U << 0), /* enable cmd issue */
|
||||
|
||||
/* Port n Attached Device Info */
|
||||
PORT_DEV_SSP_TRGT = (1U << 19),
|
||||
PORT_DEV_SMP_TRGT = (1U << 18),
|
||||
PORT_DEV_STP_TRGT = (1U << 17),
|
||||
PORT_DEV_SSP_INIT = (1U << 11),
|
||||
PORT_DEV_SMP_INIT = (1U << 10),
|
||||
PORT_DEV_STP_INIT = (1U << 9),
|
||||
PORT_PHY_ID_MASK = (0xFFU << 24),
|
||||
PORT_DEV_TRGT_MASK = (0x7U << 17),
|
||||
PORT_DEV_INIT_MASK = (0x7U << 9),
|
||||
PORT_DEV_TYPE_MASK = (0x7U << 0),
|
||||
|
||||
/* Port n PHY Status */
|
||||
PHY_RDY = (1U << 2),
|
||||
PHY_DW_SYNC = (1U << 1),
|
||||
PHY_OOB_DTCTD = (1U << 0),
|
||||
|
||||
/* VSR */
|
||||
/* PHYMODE 6 (CDB) */
|
||||
PHY_MODE6_LATECLK = (1U << 29), /* Lock Clock */
|
||||
PHY_MODE6_DTL_SPEED = (1U << 27), /* Digital Loop Speed */
|
||||
PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/
|
||||
PHY_MODE6_MUCNT_EN = (1U << 24), /* u Count Enable */
|
||||
PHY_MODE6_SEL_MUCNT_LEN = (1U << 22), /* Training Length Select */
|
||||
PHY_MODE6_SELMUPI = (1U << 20), /* Phase Multi Select (init) */
|
||||
PHY_MODE6_SELMUPF = (1U << 18), /* Phase Multi Select (final) */
|
||||
PHY_MODE6_SELMUFF = (1U << 16), /* Freq Loop Multi Sel(final) */
|
||||
PHY_MODE6_SELMUFI = (1U << 14), /* Freq Loop Multi Sel(init) */
|
||||
PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
|
||||
PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
|
||||
PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
|
||||
PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
|
||||
PHY_MODE6_RXSAT_DIS = (1U << 0), /* Saturate Ctl */
|
||||
};
|
||||
|
||||
/* SAS/SATA configuration port registers, aka phy registers */
|
||||
enum sas_sata_config_port_regs {
|
||||
PHYR_IDENTIFY = 0x00, /* info for IDENTIFY frame */
|
||||
PHYR_ADDR_LO = 0x04, /* my SAS address (low) */
|
||||
PHYR_ADDR_HI = 0x08, /* my SAS address (high) */
|
||||
PHYR_ATT_DEV_INFO = 0x0C, /* attached device info */
|
||||
PHYR_ATT_ADDR_LO = 0x10, /* attached dev SAS addr (low) */
|
||||
PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */
|
||||
PHYR_SATA_CTL = 0x18, /* SATA control */
|
||||
PHYR_PHY_STAT = 0x1C, /* PHY status */
|
||||
PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
|
||||
PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
|
||||
PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
|
||||
PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
|
||||
PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */
|
||||
PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */
|
||||
PHYR_WIDE_PORT = 0x38, /* wide port participating */
|
||||
PHYR_CURRENT0 = 0x80, /* current connection info 0 */
|
||||
PHYR_CURRENT1 = 0x84, /* current connection info 1 */
|
||||
PHYR_CURRENT2 = 0x88, /* current connection info 2 */
|
||||
};
|
||||
|
||||
enum mvs_info_flags {
|
||||
MVF_MSI = (1U << 0), /* MSI is enabled */
|
||||
MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */
|
||||
};
|
||||
|
||||
enum sas_cmd_port_registers {
|
||||
CMD_CMRST_OOB_DET = 0x100, /* COMRESET OOB detect register */
|
||||
CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */
|
||||
CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */
|
||||
CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
|
||||
CMD_OOB_SPACE = 0x110, /* OOB space control register */
|
||||
CMD_OOB_BURST = 0x114, /* OOB burst control register */
|
||||
CMD_PHY_TIMER = 0x118, /* PHY timer control register */
|
||||
CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
|
||||
CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
|
||||
CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */
|
||||
CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */
|
||||
CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */
|
||||
CMD_SAS_CTL3 = 0x130, /* SAS control register 3 */
|
||||
CMD_ID_TEST = 0x134, /* ID test register */
|
||||
CMD_PL_TIMER = 0x138, /* PL timer register */
|
||||
CMD_WD_TIMER = 0x13c, /* WD timer register */
|
||||
CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */
|
||||
CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
|
||||
CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
|
||||
CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
|
||||
CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
|
||||
CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
|
||||
CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
|
||||
CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */
|
||||
CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */
|
||||
CMD_XOR_MEM_BIST_STAT = 0x164, /* XOR Memroy BIST Status */
|
||||
CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */
|
||||
CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */
|
||||
CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */
|
||||
CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
|
||||
CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
|
||||
CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */
|
||||
CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */
|
||||
CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */
|
||||
CMD_RESET_COUNT = 0x188, /* Reset Count */
|
||||
CMD_MONTR_DATA_SEL = 0x18C, /* Monitor Data/Select */
|
||||
CMD_PLL_PHY_CONFIG = 0x190, /* PLL/PHY Configuration */
|
||||
CMD_PHY_CTL = 0x194, /* PHY Control and Status */
|
||||
CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */
|
||||
CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */
|
||||
CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */
|
||||
CMD_APP_ERR_CONFIG = 0x1A4, /* Application Error Configuration */
|
||||
CMD_PND_FIFO_CTL0 = 0x1A8, /* Pending FIFO Control 0 */
|
||||
CMD_HOST_CTL = 0x1AC, /* Host Control Status */
|
||||
CMD_HOST_WR_DATA = 0x1B0, /* Host Write Data */
|
||||
CMD_HOST_RD_DATA = 0x1B4, /* Host Read Data */
|
||||
CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */
|
||||
CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */
|
||||
CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */
|
||||
CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
|
||||
};
|
||||
|
||||
enum pci_cfg_register_bits {
|
||||
PCTL_PWR_ON = (0xFU << 24),
|
||||
PCTL_OFF = (0xFU << 12),
|
||||
PRD_REQ_SIZE = (0x4000),
|
||||
PRD_REQ_MASK = (0x00007000),
|
||||
};
|
||||
|
||||
enum nvram_layout_offsets {
|
||||
NVR_SIG = 0x00, /* 0xAA, 0x55 */
|
||||
NVR_SAS_ADDR = 0x02, /* 8-byte SAS address */
|
||||
};
|
||||
|
||||
enum chip_flavors {
|
||||
chip_6320,
|
||||
chip_6440,
|
||||
chip_6480,
|
||||
};
|
||||
|
||||
enum port_type {
|
||||
PORT_TYPE_SAS = (1L << 1),
|
||||
PORT_TYPE_SATA = (1L << 0),
|
||||
};
|
||||
|
||||
/* Command Table Format */
|
||||
enum ct_format {
|
||||
/* SSP */
|
||||
SSP_F_H = 0x00,
|
||||
SSP_F_IU = 0x18,
|
||||
SSP_F_MAX = 0x4D,
|
||||
/* STP */
|
||||
STP_CMD_FIS = 0x00,
|
||||
STP_ATAPI_CMD = 0x40,
|
||||
STP_F_MAX = 0x10,
|
||||
/* SMP */
|
||||
SMP_F_T = 0x00,
|
||||
SMP_F_DEP = 0x01,
|
||||
SMP_F_MAX = 0x101,
|
||||
};
|
||||
|
||||
enum status_buffer {
|
||||
SB_EIR_OFF = 0x00, /* Error Information Record */
|
||||
SB_RFB_OFF = 0x08, /* Response Frame Buffer */
|
||||
SB_RFB_MAX = 0x400, /* RFB size*/
|
||||
};
|
||||
|
||||
enum error_info_rec {
|
||||
CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */
|
||||
CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */
|
||||
RSP_OVER = (1U << 29), /* rsp buffer overflow */
|
||||
RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */
|
||||
UNK_FIS = (1U << 27), /* unknown FIS */
|
||||
DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
|
||||
SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
|
||||
TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */
|
||||
R_ERR = (1U << 23), /* SATA returned R_ERR prim */
|
||||
RD_OFS = (1U << 20), /* Read DATA frame invalid offset */
|
||||
XFER_RDY_OFS = (1U << 19), /* XFER_RDY offset error */
|
||||
UNEXP_XFER_RDY = (1U << 18), /* unexpected XFER_RDY error */
|
||||
DATA_OVER_UNDER = (1U << 16), /* data overflow/underflow */
|
||||
INTERLOCK = (1U << 15), /* interlock error */
|
||||
NAK = (1U << 14), /* NAK rx'd */
|
||||
ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */
|
||||
CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */
|
||||
OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
|
||||
PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */
|
||||
NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
|
||||
STP_RES_BSY = (1U << 8), /* STP resources busy */
|
||||
BREAK = (1U << 7), /* break received */
|
||||
BAD_DEST = (1U << 6), /* bad destination */
|
||||
BAD_PROTO = (1U << 5), /* protocol not supported */
|
||||
BAD_RATE = (1U << 4), /* cxn rate not supported */
|
||||
WRONG_DEST = (1U << 3), /* wrong destination error */
|
||||
CREDIT_TO = (1U << 2), /* credit timeout */
|
||||
WDOG_TO = (1U << 1), /* watchdog timeout */
|
||||
BUF_PAR = (1U << 0), /* buffer parity error */
|
||||
};
|
||||
|
||||
enum error_info_rec_2 {
|
||||
SLOT_BSY_ERR = (1U << 31), /* Slot Busy Error */
|
||||
GRD_CHK_ERR = (1U << 14), /* Guard Check Error */
|
||||
APP_CHK_ERR = (1U << 13), /* Application Check error */
|
||||
REF_CHK_ERR = (1U << 12), /* Reference Check Error */
|
||||
USR_BLK_NM = (1U << 0), /* User Block Number */
|
||||
};
|
||||
|
||||
#endif
|
||||
524
drivers/scsi/mvsas/mv_init.c
Normal file
524
drivers/scsi/mvsas/mv_init.c
Normal file
@ -0,0 +1,524 @@
|
||||
/*
|
||||
mv_init.c - Marvell 88SE6440 SAS/SATA init support
|
||||
|
||||
Copyright 2007 Red Hat, Inc.
|
||||
Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License as
|
||||
published by the Free Software Foundation; either version 2,
|
||||
or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty
|
||||
of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public
|
||||
License along with this program; see the file COPYING. If not,
|
||||
write to the Free Software Foundation, 675 Mass Ave, Cambridge,
|
||||
MA 02139, USA.
|
||||
|
||||
*/
|
||||
|
||||
#include "mv_sas.h"
|
||||
#include "mv_64xx.h"
|
||||
#include "mv_chips.h"
|
||||
|
||||
static struct scsi_transport_template *mvs_stt;
|
||||
|
||||
static const struct mvs_chip_info mvs_chips[] = {
|
||||
[chip_6320] = { 2, 16, 9 },
|
||||
[chip_6440] = { 4, 16, 9 },
|
||||
[chip_6480] = { 8, 32, 10 },
|
||||
};
|
||||
|
||||
static struct scsi_host_template mvs_sht = {
|
||||
.module = THIS_MODULE,
|
||||
.name = DRV_NAME,
|
||||
.queuecommand = sas_queuecommand,
|
||||
.target_alloc = sas_target_alloc,
|
||||
.slave_configure = mvs_slave_configure,
|
||||
.slave_destroy = sas_slave_destroy,
|
||||
.scan_finished = mvs_scan_finished,
|
||||
.scan_start = mvs_scan_start,
|
||||
.change_queue_depth = sas_change_queue_depth,
|
||||
.change_queue_type = sas_change_queue_type,
|
||||
.bios_param = sas_bios_param,
|
||||
.can_queue = 1,
|
||||
.cmd_per_lun = 1,
|
||||
.this_id = -1,
|
||||
.sg_tablesize = SG_ALL,
|
||||
.max_sectors = SCSI_DEFAULT_MAX_SECTORS,
|
||||
.use_clustering = ENABLE_CLUSTERING,
|
||||
.eh_device_reset_handler = sas_eh_device_reset_handler,
|
||||
.eh_bus_reset_handler = sas_eh_bus_reset_handler,
|
||||
.slave_alloc = sas_slave_alloc,
|
||||
.target_destroy = sas_target_destroy,
|
||||
.ioctl = sas_ioctl,
|
||||
};
|
||||
|
||||
static struct sas_domain_function_template mvs_transport_ops = {
|
||||
.lldd_execute_task = mvs_task_exec,
|
||||
.lldd_control_phy = mvs_phy_control,
|
||||
.lldd_abort_task = mvs_task_abort,
|
||||
.lldd_port_formed = mvs_port_formed,
|
||||
.lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
|
||||
};
|
||||
|
||||
static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
|
||||
{
|
||||
struct mvs_phy *phy = &mvi->phy[phy_id];
|
||||
struct asd_sas_phy *sas_phy = &phy->sas_phy;
|
||||
|
||||
sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
|
||||
sas_phy->class = SAS;
|
||||
sas_phy->iproto = SAS_PROTOCOL_ALL;
|
||||
sas_phy->tproto = 0;
|
||||
sas_phy->type = PHY_TYPE_PHYSICAL;
|
||||
sas_phy->role = PHY_ROLE_INITIATOR;
|
||||
sas_phy->oob_mode = OOB_NOT_CONNECTED;
|
||||
sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
|
||||
|
||||
sas_phy->id = phy_id;
|
||||
sas_phy->sas_addr = &mvi->sas_addr[0];
|
||||
sas_phy->frame_rcvd = &phy->frame_rcvd[0];
|
||||
sas_phy->ha = &mvi->sas;
|
||||
sas_phy->lldd_phy = phy;
|
||||
}
|
||||
|
||||
static void mvs_free(struct mvs_info *mvi)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (!mvi)
|
||||
return;
|
||||
|
||||
for (i = 0; i < MVS_SLOTS; i++) {
|
||||
struct mvs_slot_info *slot = &mvi->slot_info[i];
|
||||
|
||||
if (slot->buf)
|
||||
dma_free_coherent(&mvi->pdev->dev, MVS_SLOT_BUF_SZ,
|
||||
slot->buf, slot->buf_dma);
|
||||
}
|
||||
|
||||
if (mvi->tx)
|
||||
dma_free_coherent(&mvi->pdev->dev,
|
||||
sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
|
||||
mvi->tx, mvi->tx_dma);
|
||||
if (mvi->rx_fis)
|
||||
dma_free_coherent(&mvi->pdev->dev, MVS_RX_FISL_SZ,
|
||||
mvi->rx_fis, mvi->rx_fis_dma);
|
||||
if (mvi->rx)
|
||||
dma_free_coherent(&mvi->pdev->dev,
|
||||
sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
|
||||
mvi->rx, mvi->rx_dma);
|
||||
if (mvi->slot)
|
||||
dma_free_coherent(&mvi->pdev->dev,
|
||||
sizeof(*mvi->slot) * MVS_SLOTS,
|
||||
mvi->slot, mvi->slot_dma);
|
||||
#ifdef MVS_ENABLE_PERI
|
||||
if (mvi->peri_regs)
|
||||
iounmap(mvi->peri_regs);
|
||||
#endif
|
||||
if (mvi->regs)
|
||||
iounmap(mvi->regs);
|
||||
if (mvi->shost)
|
||||
scsi_host_put(mvi->shost);
|
||||
kfree(mvi->sas.sas_port);
|
||||
kfree(mvi->sas.sas_phy);
|
||||
kfree(mvi);
|
||||
}
|
||||
|
||||
#ifdef MVS_USE_TASKLET
|
||||
static void mvs_tasklet(unsigned long data)
|
||||
{
|
||||
struct mvs_info *mvi = (struct mvs_info *) data;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mvi->lock, flags);
|
||||
|
||||
#ifdef MVS_DISABLE_MSI
|
||||
mvs_int_full(mvi);
|
||||
#else
|
||||
mvs_int_rx(mvi, true);
|
||||
#endif
|
||||
spin_unlock_irqrestore(&mvi->lock, flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
static irqreturn_t mvs_interrupt(int irq, void *opaque)
|
||||
{
|
||||
struct mvs_info *mvi = opaque;
|
||||
void __iomem *regs = mvi->regs;
|
||||
u32 stat;
|
||||
|
||||
stat = mr32(GBL_INT_STAT);
|
||||
|
||||
if (stat == 0 || stat == 0xffffffff)
|
||||
return IRQ_NONE;
|
||||
|
||||
/* clear CMD_CMPLT ASAP */
|
||||
mw32_f(INT_STAT, CINT_DONE);
|
||||
|
||||
#ifndef MVS_USE_TASKLET
|
||||
spin_lock(&mvi->lock);
|
||||
|
||||
mvs_int_full(mvi);
|
||||
|
||||
spin_unlock(&mvi->lock);
|
||||
#else
|
||||
tasklet_schedule(&mvi->tasklet);
|
||||
#endif
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct mvs_info *__devinit mvs_alloc(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
struct mvs_info *mvi;
|
||||
unsigned long res_start, res_len, res_flag;
|
||||
struct asd_sas_phy **arr_phy;
|
||||
struct asd_sas_port **arr_port;
|
||||
const struct mvs_chip_info *chip = &mvs_chips[ent->driver_data];
|
||||
int i;
|
||||
|
||||
/*
|
||||
* alloc and init our per-HBA mvs_info struct
|
||||
*/
|
||||
|
||||
mvi = kzalloc(sizeof(*mvi), GFP_KERNEL);
|
||||
if (!mvi)
|
||||
return NULL;
|
||||
|
||||
spin_lock_init(&mvi->lock);
|
||||
#ifdef MVS_USE_TASKLET
|
||||
tasklet_init(&mvi->tasklet, mvs_tasklet, (unsigned long)mvi);
|
||||
#endif
|
||||
mvi->pdev = pdev;
|
||||
mvi->chip = chip;
|
||||
|
||||
if (pdev->device == 0x6440 && pdev->revision == 0)
|
||||
mvi->flags |= MVF_PHY_PWR_FIX;
|
||||
|
||||
/*
|
||||
* alloc and init SCSI, SAS glue
|
||||
*/
|
||||
|
||||
mvi->shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
|
||||
if (!mvi->shost)
|
||||
goto err_out;
|
||||
|
||||
arr_phy = kcalloc(MVS_MAX_PHYS, sizeof(void *), GFP_KERNEL);
|
||||
arr_port = kcalloc(MVS_MAX_PHYS, sizeof(void *), GFP_KERNEL);
|
||||
if (!arr_phy || !arr_port)
|
||||
goto err_out;
|
||||
|
||||
for (i = 0; i < MVS_MAX_PHYS; i++) {
|
||||
mvs_phy_init(mvi, i);
|
||||
arr_phy[i] = &mvi->phy[i].sas_phy;
|
||||
arr_port[i] = &mvi->port[i].sas_port;
|
||||
mvi->port[i].taskfileset = MVS_ID_NOT_MAPPED;
|
||||
mvi->port[i].wide_port_phymap = 0;
|
||||
mvi->port[i].port_attached = 0;
|
||||
INIT_LIST_HEAD(&mvi->port[i].list);
|
||||
}
|
||||
|
||||
SHOST_TO_SAS_HA(mvi->shost) = &mvi->sas;
|
||||
mvi->shost->transportt = mvs_stt;
|
||||
mvi->shost->max_id = 21;
|
||||
mvi->shost->max_lun = ~0;
|
||||
mvi->shost->max_channel = 0;
|
||||
mvi->shost->max_cmd_len = 16;
|
||||
|
||||
mvi->sas.sas_ha_name = DRV_NAME;
|
||||
mvi->sas.dev = &pdev->dev;
|
||||
mvi->sas.lldd_module = THIS_MODULE;
|
||||
mvi->sas.sas_addr = &mvi->sas_addr[0];
|
||||
mvi->sas.sas_phy = arr_phy;
|
||||
mvi->sas.sas_port = arr_port;
|
||||
mvi->sas.num_phys = chip->n_phy;
|
||||
mvi->sas.lldd_max_execute_num = 1;
|
||||
mvi->sas.lldd_queue_size = MVS_QUEUE_SIZE;
|
||||
mvi->shost->can_queue = MVS_CAN_QUEUE;
|
||||
mvi->shost->cmd_per_lun = MVS_SLOTS / mvi->sas.num_phys;
|
||||
mvi->sas.lldd_ha = mvi;
|
||||
mvi->sas.core.shost = mvi->shost;
|
||||
|
||||
mvs_tag_init(mvi);
|
||||
|
||||
/*
|
||||
* ioremap main and peripheral registers
|
||||
*/
|
||||
|
||||
#ifdef MVS_ENABLE_PERI
|
||||
res_start = pci_resource_start(pdev, 2);
|
||||
res_len = pci_resource_len(pdev, 2);
|
||||
if (!res_start || !res_len)
|
||||
goto err_out;
|
||||
|
||||
mvi->peri_regs = ioremap_nocache(res_start, res_len);
|
||||
if (!mvi->peri_regs)
|
||||
goto err_out;
|
||||
#endif
|
||||
|
||||
res_start = pci_resource_start(pdev, 4);
|
||||
res_len = pci_resource_len(pdev, 4);
|
||||
if (!res_start || !res_len)
|
||||
goto err_out;
|
||||
|
||||
res_flag = pci_resource_flags(pdev, 4);
|
||||
if (res_flag & IORESOURCE_CACHEABLE)
|
||||
mvi->regs = ioremap(res_start, res_len);
|
||||
else
|
||||
mvi->regs = ioremap_nocache(res_start, res_len);
|
||||
|
||||
if (!mvi->regs)
|
||||
goto err_out;
|
||||
|
||||
/*
|
||||
* alloc and init our DMA areas
|
||||
*/
|
||||
|
||||
mvi->tx = dma_alloc_coherent(&pdev->dev,
|
||||
sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
|
||||
&mvi->tx_dma, GFP_KERNEL);
|
||||
if (!mvi->tx)
|
||||
goto err_out;
|
||||
memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
|
||||
|
||||
mvi->rx_fis = dma_alloc_coherent(&pdev->dev, MVS_RX_FISL_SZ,
|
||||
&mvi->rx_fis_dma, GFP_KERNEL);
|
||||
if (!mvi->rx_fis)
|
||||
goto err_out;
|
||||
memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
|
||||
|
||||
mvi->rx = dma_alloc_coherent(&pdev->dev,
|
||||
sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
|
||||
&mvi->rx_dma, GFP_KERNEL);
|
||||
if (!mvi->rx)
|
||||
goto err_out;
|
||||
memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
|
||||
|
||||
mvi->rx[0] = cpu_to_le32(0xfff);
|
||||
mvi->rx_cons = 0xfff;
|
||||
|
||||
mvi->slot = dma_alloc_coherent(&pdev->dev,
|
||||
sizeof(*mvi->slot) * MVS_SLOTS,
|
||||
&mvi->slot_dma, GFP_KERNEL);
|
||||
if (!mvi->slot)
|
||||
goto err_out;
|
||||
memset(mvi->slot, 0, sizeof(*mvi->slot) * MVS_SLOTS);
|
||||
|
||||
for (i = 0; i < MVS_SLOTS; i++) {
|
||||
struct mvs_slot_info *slot = &mvi->slot_info[i];
|
||||
|
||||
slot->buf = dma_alloc_coherent(&pdev->dev, MVS_SLOT_BUF_SZ,
|
||||
&slot->buf_dma, GFP_KERNEL);
|
||||
if (!slot->buf)
|
||||
goto err_out;
|
||||
memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
|
||||
}
|
||||
|
||||
/* finally, read NVRAM to get our SAS address */
|
||||
if (mvs_nvram_read(mvi, NVR_SAS_ADDR, &mvi->sas_addr, 8))
|
||||
goto err_out;
|
||||
return mvi;
|
||||
|
||||
err_out:
|
||||
mvs_free(mvi);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* move to PCI layer or libata core? */
|
||||
static int pci_go_64(struct pci_dev *pdev)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
|
||||
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
|
||||
if (rc) {
|
||||
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"64-bit DMA enable failed\n");
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"32-bit DMA enable failed\n");
|
||||
return rc;
|
||||
}
|
||||
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
||||
if (rc) {
|
||||
dev_printk(KERN_ERR, &pdev->dev,
|
||||
"32-bit consistent DMA enable failed\n");
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int __devinit mvs_pci_init(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
int rc;
|
||||
struct mvs_info *mvi;
|
||||
irq_handler_t irq_handler = mvs_interrupt;
|
||||
|
||||
rc = pci_enable_device(pdev);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
pci_set_master(pdev);
|
||||
|
||||
rc = pci_request_regions(pdev, DRV_NAME);
|
||||
if (rc)
|
||||
goto err_out_disable;
|
||||
|
||||
rc = pci_go_64(pdev);
|
||||
if (rc)
|
||||
goto err_out_regions;
|
||||
|
||||
mvi = mvs_alloc(pdev, ent);
|
||||
if (!mvi) {
|
||||
rc = -ENOMEM;
|
||||
goto err_out_regions;
|
||||
}
|
||||
|
||||
rc = mvs_hw_init(mvi);
|
||||
if (rc)
|
||||
goto err_out_mvi;
|
||||
|
||||
#ifndef MVS_DISABLE_MSI
|
||||
if (!pci_enable_msi(pdev)) {
|
||||
u32 tmp;
|
||||
void __iomem *regs = mvi->regs;
|
||||
mvi->flags |= MVF_MSI;
|
||||
irq_handler = mvs_msi_interrupt;
|
||||
tmp = mr32(PCS);
|
||||
mw32(PCS, tmp | PCS_SELF_CLEAR);
|
||||
}
|
||||
#endif
|
||||
|
||||
rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, DRV_NAME, mvi);
|
||||
if (rc)
|
||||
goto err_out_msi;
|
||||
|
||||
rc = scsi_add_host(mvi->shost, &pdev->dev);
|
||||
if (rc)
|
||||
goto err_out_irq;
|
||||
|
||||
rc = sas_register_ha(&mvi->sas);
|
||||
if (rc)
|
||||
goto err_out_shost;
|
||||
|
||||
pci_set_drvdata(pdev, mvi);
|
||||
|
||||
mvs_print_info(mvi);
|
||||
|
||||
mvs_hba_interrupt_enable(mvi);
|
||||
|
||||
scsi_scan_host(mvi->shost);
|
||||
|
||||
return 0;
|
||||
|
||||
err_out_shost:
|
||||
scsi_remove_host(mvi->shost);
|
||||
err_out_irq:
|
||||
free_irq(pdev->irq, mvi);
|
||||
err_out_msi:
|
||||
if (mvi->flags |= MVF_MSI)
|
||||
pci_disable_msi(pdev);
|
||||
err_out_mvi:
|
||||
mvs_free(mvi);
|
||||
err_out_regions:
|
||||
pci_release_regions(pdev);
|
||||
err_out_disable:
|
||||
pci_disable_device(pdev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __devexit mvs_pci_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct mvs_info *mvi = pci_get_drvdata(pdev);
|
||||
|
||||
pci_set_drvdata(pdev, NULL);
|
||||
|
||||
if (mvi) {
|
||||
sas_unregister_ha(&mvi->sas);
|
||||
mvs_hba_interrupt_disable(mvi);
|
||||
sas_remove_host(mvi->shost);
|
||||
scsi_remove_host(mvi->shost);
|
||||
|
||||
free_irq(pdev->irq, mvi);
|
||||
if (mvi->flags & MVF_MSI)
|
||||
pci_disable_msi(pdev);
|
||||
mvs_free(mvi);
|
||||
pci_release_regions(pdev);
|
||||
}
|
||||
pci_disable_device(pdev);
|
||||
}
|
||||
|
||||
static struct pci_device_id __devinitdata mvs_pci_table[] = {
|
||||
{ PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
|
||||
{ PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_MARVELL,
|
||||
.device = 0x6440,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = 0x6480,
|
||||
.class = 0,
|
||||
.class_mask = 0,
|
||||
.driver_data = chip_6480,
|
||||
},
|
||||
{ PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
|
||||
{ PCI_VDEVICE(MARVELL, 0x6480), chip_6480 },
|
||||
|
||||
{ } /* terminate list */
|
||||
};
|
||||
|
||||
static struct pci_driver mvs_pci_driver = {
|
||||
.name = DRV_NAME,
|
||||
.id_table = mvs_pci_table,
|
||||
.probe = mvs_pci_init,
|
||||
.remove = __devexit_p(mvs_pci_remove),
|
||||
};
|
||||
|
||||
static int __init mvs_init(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
|
||||
if (!mvs_stt)
|
||||
return -ENOMEM;
|
||||
|
||||
rc = pci_register_driver(&mvs_pci_driver);
|
||||
if (rc)
|
||||
goto err_out;
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
sas_release_transport(mvs_stt);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void __exit mvs_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&mvs_pci_driver);
|
||||
sas_release_transport(mvs_stt);
|
||||
}
|
||||
|
||||
module_init(mvs_init);
|
||||
module_exit(mvs_exit);
|
||||
|
||||
MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
|
||||
MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
|
||||
MODULE_VERSION(DRV_VERSION);
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DEVICE_TABLE(pci, mvs_pci_table);
|
||||
File diff suppressed because it is too large
Load Diff
205
drivers/scsi/mvsas/mv_sas.h
Normal file
205
drivers/scsi/mvsas/mv_sas.h
Normal file
@ -0,0 +1,205 @@
|
||||
/*
|
||||
mv_sas.h - Marvell 88SE6440 SAS/SATA support
|
||||
|
||||
Copyright 2007 Red Hat, Inc.
|
||||
Copyright 2008 Marvell. <kewei@marvell.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License as
|
||||
published by the Free Software Foundation; either version 2,
|
||||
or (at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty
|
||||
of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public
|
||||
License along with this program; see the file COPYING. If not,
|
||||
write to the Free Software Foundation, 675 Mass Ave, Cambridge,
|
||||
MA 02139, USA.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _MV_SAS_H_
|
||||
#define _MV_SAS_H_
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <scsi/libsas.h>
|
||||
#include <scsi/scsi_tcq.h>
|
||||
#include <scsi/sas_ata.h>
|
||||
#include <linux/version.h>
|
||||
#include "mv_defs.h"
|
||||
|
||||
#define DRV_NAME "mvsas"
|
||||
#define DRV_VERSION "0.5.2"
|
||||
#define _MV_DUMP 0
|
||||
#define MVS_DISABLE_NVRAM
|
||||
#define MVS_DISABLE_MSI
|
||||
|
||||
#define MVS_ID_NOT_MAPPED 0x7f
|
||||
#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
|
||||
|
||||
#define for_each_phy(__lseq_mask, __mc, __lseq, __rest) \
|
||||
for ((__mc) = (__lseq_mask), (__lseq) = 0; \
|
||||
(__mc) != 0 && __rest; \
|
||||
(++__lseq), (__mc) >>= 1)
|
||||
|
||||
struct mvs_chip_info {
|
||||
u32 n_phy;
|
||||
u32 srs_sz;
|
||||
u32 slot_width;
|
||||
};
|
||||
|
||||
struct mvs_err_info {
|
||||
__le32 flags;
|
||||
__le32 flags2;
|
||||
};
|
||||
|
||||
struct mvs_cmd_hdr {
|
||||
__le32 flags; /* PRD tbl len; SAS, SATA ctl */
|
||||
__le32 lens; /* cmd, max resp frame len */
|
||||
__le32 tags; /* targ port xfer tag; tag */
|
||||
__le32 data_len; /* data xfer len */
|
||||
__le64 cmd_tbl; /* command table address */
|
||||
__le64 open_frame; /* open addr frame address */
|
||||
__le64 status_buf; /* status buffer address */
|
||||
__le64 prd_tbl; /* PRD tbl address */
|
||||
__le32 reserved[4];
|
||||
};
|
||||
|
||||
struct mvs_port {
|
||||
struct asd_sas_port sas_port;
|
||||
u8 port_attached;
|
||||
u8 taskfileset;
|
||||
u8 wide_port_phymap;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
struct mvs_phy {
|
||||
struct mvs_port *port;
|
||||
struct asd_sas_phy sas_phy;
|
||||
struct sas_identify identify;
|
||||
struct scsi_device *sdev;
|
||||
u64 dev_sas_addr;
|
||||
u64 att_dev_sas_addr;
|
||||
u32 att_dev_info;
|
||||
u32 dev_info;
|
||||
u32 phy_type;
|
||||
u32 phy_status;
|
||||
u32 irq_status;
|
||||
u32 frame_rcvd_size;
|
||||
u8 frame_rcvd[32];
|
||||
u8 phy_attached;
|
||||
enum sas_linkrate minimum_linkrate;
|
||||
enum sas_linkrate maximum_linkrate;
|
||||
};
|
||||
|
||||
struct mvs_slot_info {
|
||||
struct list_head list;
|
||||
struct sas_task *task;
|
||||
u32 n_elem;
|
||||
u32 tx;
|
||||
|
||||
/* DMA buffer for storing cmd tbl, open addr frame, status buffer,
|
||||
* and PRD table
|
||||
*/
|
||||
void *buf;
|
||||
dma_addr_t buf_dma;
|
||||
#if _MV_DUMP
|
||||
u32 cmd_size;
|
||||
#endif
|
||||
|
||||
void *response;
|
||||
struct mvs_port *port;
|
||||
};
|
||||
|
||||
struct mvs_info {
|
||||
unsigned long flags;
|
||||
|
||||
/* host-wide lock */
|
||||
spinlock_t lock;
|
||||
|
||||
/* our device */
|
||||
struct pci_dev *pdev;
|
||||
|
||||
/* enhanced mode registers */
|
||||
void __iomem *regs;
|
||||
|
||||
/* peripheral registers */
|
||||
void __iomem *peri_regs;
|
||||
|
||||
u8 sas_addr[SAS_ADDR_SIZE];
|
||||
|
||||
/* SCSI/SAS glue */
|
||||
struct sas_ha_struct sas;
|
||||
struct Scsi_Host *shost;
|
||||
|
||||
/* TX (delivery) DMA ring */
|
||||
__le32 *tx;
|
||||
dma_addr_t tx_dma;
|
||||
|
||||
/* cached next-producer idx */
|
||||
u32 tx_prod;
|
||||
|
||||
/* RX (completion) DMA ring */
|
||||
__le32 *rx;
|
||||
dma_addr_t rx_dma;
|
||||
|
||||
/* RX consumer idx */
|
||||
u32 rx_cons;
|
||||
|
||||
/* RX'd FIS area */
|
||||
__le32 *rx_fis;
|
||||
dma_addr_t rx_fis_dma;
|
||||
|
||||
/* DMA command header slots */
|
||||
struct mvs_cmd_hdr *slot;
|
||||
dma_addr_t slot_dma;
|
||||
|
||||
const struct mvs_chip_info *chip;
|
||||
|
||||
u8 tags[MVS_SLOTS];
|
||||
struct mvs_slot_info slot_info[MVS_SLOTS];
|
||||
/* further per-slot information */
|
||||
struct mvs_phy phy[MVS_MAX_PHYS];
|
||||
struct mvs_port port[MVS_MAX_PHYS];
|
||||
#ifdef MVS_USE_TASKLET
|
||||
struct tasklet_struct tasklet;
|
||||
#endif
|
||||
};
|
||||
|
||||
int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
|
||||
void *funcdata);
|
||||
int mvs_slave_configure(struct scsi_device *sdev);
|
||||
void mvs_scan_start(struct Scsi_Host *shost);
|
||||
int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
|
||||
int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags);
|
||||
int mvs_task_abort(struct sas_task *task);
|
||||
void mvs_port_formed(struct asd_sas_phy *sas_phy);
|
||||
int mvs_I_T_nexus_reset(struct domain_device *dev);
|
||||
void mvs_int_full(struct mvs_info *mvi);
|
||||
void mvs_tag_init(struct mvs_info *mvi);
|
||||
int mvs_nvram_read(struct mvs_info *mvi, u32 addr, void *buf, u32 buflen);
|
||||
int __devinit mvs_hw_init(struct mvs_info *mvi);
|
||||
void __devinit mvs_print_info(struct mvs_info *mvi);
|
||||
void mvs_hba_interrupt_enable(struct mvs_info *mvi);
|
||||
void mvs_hba_interrupt_disable(struct mvs_info *mvi);
|
||||
void mvs_detect_porttype(struct mvs_info *mvi, int i);
|
||||
u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port);
|
||||
void mvs_enable_xmt(struct mvs_info *mvi, int PhyId);
|
||||
void __devinit mvs_phy_hacks(struct mvs_info *mvi);
|
||||
void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user